2 * Copyright (C) 2012 Freescale Semiconductor, Inc.
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
22 #include <asm/arch/clock.h>
23 #include <asm/arch/imx-regs.h>
24 #include <asm/arch/iomux.h>
25 #include <asm/arch/mx6q_pins.h>
26 #include <asm/errno.h>
28 #include <asm/imx-common/iomux-v3.h>
30 #include <fsl_esdhc.h>
33 DECLARE_GLOBAL_DATA_PTR;
35 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
36 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
37 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
39 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
40 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
41 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
43 #define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
44 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
45 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
49 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
54 iomux_v3_cfg_t const uart1_pads[] = {
55 MX6_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
56 MX6_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
59 iomux_v3_cfg_t const enet_pads[] = {
60 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
61 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
62 MX6_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
63 MX6_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
64 MX6_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
65 MX6_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
66 MX6_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
67 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
68 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
69 MX6_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
70 MX6_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
71 MX6_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
72 MX6_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
73 MX6_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
74 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
75 /* AR8031 PHY Reset */
76 MX6_PAD_ENET_CRS_DV__GPIO_1_25 | MUX_PAD_CTRL(NO_PAD_CTRL),
79 static void setup_iomux_enet(void)
81 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
83 /* Reset AR8031 PHY */
84 gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
86 gpio_set_value(IMX_GPIO_NR(1, 25), 1);
89 iomux_v3_cfg_t const usdhc2_pads[] = {
90 MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
91 MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
92 MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
93 MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
94 MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
95 MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
96 MX6_PAD_NANDF_D4__USDHC2_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
97 MX6_PAD_NANDF_D5__USDHC2_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
98 MX6_PAD_NANDF_D6__USDHC2_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
99 MX6_PAD_NANDF_D7__USDHC2_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
100 MX6_PAD_NANDF_D2__GPIO_2_2 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
103 iomux_v3_cfg_t const usdhc3_pads[] = {
104 MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
105 MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
106 MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
107 MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
108 MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
109 MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
110 MX6_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
111 MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
112 MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
113 MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
114 MX6_PAD_NANDF_D0__GPIO_2_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
117 iomux_v3_cfg_t const usdhc4_pads[] = {
118 MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
119 MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
120 MX6_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
121 MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
122 MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
123 MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
124 MX6_PAD_SD4_DAT4__USDHC4_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
125 MX6_PAD_SD4_DAT5__USDHC4_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
126 MX6_PAD_SD4_DAT6__USDHC4_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
127 MX6_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
130 static void setup_iomux_uart(void)
132 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
135 #ifdef CONFIG_FSL_ESDHC
136 struct fsl_esdhc_cfg usdhc_cfg[3] = {
142 #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2)
143 #define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)
145 int board_mmc_getcd(struct mmc *mmc)
147 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
149 switch (cfg->esdhc_base) {
150 case USDHC2_BASE_ADDR:
151 return !gpio_get_value(USDHC2_CD_GPIO);
152 case USDHC3_BASE_ADDR:
153 return !gpio_get_value(USDHC3_CD_GPIO);
155 return 1; /* eMMC/uSDHC4 is always present */
159 int board_mmc_init(bd_t *bis)
163 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
166 imx_iomux_v3_setup_multiple_pads(
167 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
168 gpio_direction_input(USDHC2_CD_GPIO);
169 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
172 imx_iomux_v3_setup_multiple_pads(
173 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
174 gpio_direction_input(USDHC3_CD_GPIO);
175 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
178 imx_iomux_v3_setup_multiple_pads(
179 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
180 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
183 printf("Warning: you configured more USDHC controllers"
184 "(%d) than supported by the board\n", i + 1);
188 if (fsl_esdhc_initialize(bis, &usdhc_cfg[i]))
189 printf("Warning: failed to initialize mmc dev %d\n", i);
196 int mx6_rgmii_rework(struct phy_device *phydev)
200 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
201 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
202 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
203 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
205 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
208 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
210 /* introduce tx clock delay */
211 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
212 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
214 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
219 int board_phy_config(struct phy_device *phydev)
221 mx6_rgmii_rework(phydev);
223 if (phydev->drv->config)
224 phydev->drv->config(phydev);
229 int board_eth_init(bd_t *bis)
235 ret = cpu_eth_init(bis);
237 printf("FEC MXC: %s:failed\n", __func__);
242 u32 get_board_rev(void)
247 int board_early_init_f(void)
256 /* address of boot parameters */
257 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
264 puts("Board: MX6Q-SabreSD\n");