2 * Copyright (C) 2014 Freescale Semiconductor, Inc.
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
6 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/clock.h>
10 #include <asm/arch/crm_regs.h>
11 #include <asm/arch/iomux.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/mx6-pins.h>
14 #include <asm/arch/sys_proto.h>
16 #include <asm/imx-common/iomux-v3.h>
18 #include <asm/imx-common/mxc_i2c.h>
19 #include <linux/sizes.h>
21 #include <fsl_esdhc.h>
26 #include <power/pmic.h>
27 #include <power/pfuze100_pmic.h>
28 #include "../common/pfuze.h"
30 #include <usb/ehci-fsl.h>
32 DECLARE_GLOBAL_DATA_PTR;
34 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
35 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
36 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
38 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
39 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
40 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
42 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
43 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
44 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
47 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
48 PAD_CTL_SPEED_HIGH | \
49 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
51 #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
52 PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
54 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
55 PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
57 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
58 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
59 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
64 gd->ram_size = PHYS_SDRAM_SIZE;
69 static iomux_v3_cfg_t const uart1_pads[] = {
70 MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
71 MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
74 static iomux_v3_cfg_t const usdhc2_pads[] = {
75 MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
76 MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
77 MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
78 MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
79 MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
80 MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
83 static iomux_v3_cfg_t const usdhc3_pads[] = {
84 MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
85 MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
86 MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
87 MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
88 MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
89 MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
90 MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
91 MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
92 MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
93 MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
96 MX6_PAD_KEY_COL0__GPIO2_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL),
98 /* RST_B, used for power reset cycle */
99 MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
102 static iomux_v3_cfg_t const usdhc4_pads[] = {
103 MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
104 MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
105 MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
106 MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
107 MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
108 MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
109 MX6_PAD_SD4_DATA7__GPIO6_IO_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
112 static iomux_v3_cfg_t const fec1_pads[] = {
113 MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
114 MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
115 MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
116 MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
117 MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
118 MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
119 MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
120 MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
121 MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
122 MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
123 MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
124 MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
125 MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
126 MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
129 static iomux_v3_cfg_t const peri_3v3_pads[] = {
130 MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
133 static iomux_v3_cfg_t const phy_control_pads[] = {
134 /* 25MHz Ethernet PHY Clock */
135 MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
138 MX6_PAD_ENET2_COL__GPIO2_IO_6 | MUX_PAD_CTRL(NO_PAD_CTRL),
140 /* AR8031 PHY Reset */
141 MX6_PAD_ENET2_CRS__GPIO2_IO_7 | MUX_PAD_CTRL(NO_PAD_CTRL),
144 static void setup_iomux_uart(void)
146 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
149 static int setup_fec(void)
151 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
152 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
155 /* Use 125MHz anatop loopback REF_CLK1 for ENET1 */
156 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0);
158 imx_iomux_v3_setup_multiple_pads(phy_control_pads,
159 ARRAY_SIZE(phy_control_pads));
161 /* Enable the ENET power, active low */
162 gpio_direction_output(IMX_GPIO_NR(2, 6) , 0);
164 /* Reset AR8031 PHY */
165 gpio_direction_output(IMX_GPIO_NR(2, 7) , 0);
167 gpio_set_value(IMX_GPIO_NR(2, 7), 1);
169 reg = readl(&anatop->pll_enet);
170 reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
171 writel(reg, &anatop->pll_enet);
173 return enable_fec_anatop_clock(ENET_125MHZ);
176 int board_eth_init(bd_t *bis)
178 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
181 return cpu_eth_init(bis);
184 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
186 static struct i2c_pads_info i2c_pad_info1 = {
188 .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
189 .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
190 .gp = IMX_GPIO_NR(1, 0),
193 .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
194 .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
195 .gp = IMX_GPIO_NR(1, 1),
199 int power_init_board(void)
204 p = pfuze_common_init(I2C_PMIC);
208 /* Enable power of VGEN5 3V3, needed for SD3 */
209 pmic_reg_read(p, PFUZE100_VGEN5VOL, ®);
210 reg &= ~LDO_VOL_MASK;
211 reg |= (LDOB_3_30V | (1 << LDO_EN));
212 pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
217 #ifdef CONFIG_USB_EHCI_MX6
218 #define USB_OTHERREGS_OFFSET 0x800
219 #define UCTRL_PWR_POL (1 << 9)
221 static iomux_v3_cfg_t const usb_otg_pads[] = {
223 MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
224 MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
226 MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
229 static void setup_usb(void)
231 imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
232 ARRAY_SIZE(usb_otg_pads));
235 int board_usb_phy_mode(int port)
238 return USB_INIT_HOST;
240 return usb_phy_mode(port);
243 int board_ehci_hcd_init(int port)
250 usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
253 /* Set Power polarity */
254 setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
260 int board_phy_config(struct phy_device *phydev)
263 * Enable 1.8V(SEL_1P5_1P8_POS_REG) on
264 * Phy control debug reg 0
266 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
267 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
269 /* rgmii tx clock delay enable */
270 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
271 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
273 if (phydev->drv->config)
274 phydev->drv->config(phydev);
279 int board_early_init_f(void)
283 /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
284 imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
285 ARRAY_SIZE(peri_3v3_pads));
287 /* Active high for ncp692 */
288 gpio_direction_output(IMX_GPIO_NR(4, 16) , 1);
290 #ifdef CONFIG_USB_EHCI_MX6
297 static struct fsl_esdhc_cfg usdhc_cfg[3] = {
298 {USDHC2_BASE_ADDR, 0, 4},
303 #define USDHC3_CD_GPIO IMX_GPIO_NR(2, 10)
304 #define USDHC3_PWR_GPIO IMX_GPIO_NR(2, 11)
305 #define USDHC4_CD_GPIO IMX_GPIO_NR(6, 21)
307 int board_mmc_getcd(struct mmc *mmc)
309 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
312 switch (cfg->esdhc_base) {
313 case USDHC2_BASE_ADDR:
314 ret = 1; /* Assume uSDHC2 is always present */
316 case USDHC3_BASE_ADDR:
317 ret = !gpio_get_value(USDHC3_CD_GPIO);
319 case USDHC4_BASE_ADDR:
320 ret = !gpio_get_value(USDHC4_CD_GPIO);
327 int board_mmc_init(bd_t *bis)
332 * According to the board_mmc_init() the following map is done:
333 * (U-boot device node) (Physical Port)
338 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
341 imx_iomux_v3_setup_multiple_pads(
342 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
343 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
346 imx_iomux_v3_setup_multiple_pads(
347 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
348 gpio_direction_input(USDHC3_CD_GPIO);
349 gpio_direction_output(USDHC3_PWR_GPIO, 1);
350 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
353 imx_iomux_v3_setup_multiple_pads(
354 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
355 gpio_direction_input(USDHC4_CD_GPIO);
356 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
359 printf("Warning: you configured more USDHC controllers"
360 "(%d) than supported by the board\n", i + 1);
364 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
366 printf("Warning: failed to initialize mmc dev %d\n", i);
376 /* Address of boot parameters */
377 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
379 #ifdef CONFIG_SYS_I2C_MXC
380 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
386 int board_late_init(void)
393 puts("Board: MX6SX SABRE SDB\n");