2 * Copyright 2007-2010 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
28 #include <asm/cache.h>
29 #include <asm/immap_85xx.h>
30 #include <asm/fsl_pci.h>
31 #include <asm/fsl_ddr_sdram.h>
33 #include <asm/fsl_serdes.h>
36 #include <fdt_support.h>
38 #include <asm/fsl_law.h>
42 #include "../common/ngpixis.h"
43 #include "../common/sgmii_riser.h"
45 DECLARE_GLOBAL_DATA_PTR;
51 puts("Board: P2020DS ");
52 #ifdef CONFIG_PHYS_64BIT
53 puts("(36-bit addrmap) ");
56 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
57 in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
59 sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
60 sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT;
63 /* The lower two bits are the actual vbank number */
64 printf("vBank: %d\n", sw & 3);
71 #if !defined(CONFIG_DDR_SPD)
73 * Fixed sdram init -- doesn't use serial presence detect.
76 phys_size_t fixed_sdram(void)
78 volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
81 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
82 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
83 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
84 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
85 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
86 ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTRL;
87 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
88 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
89 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
90 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
91 ddr->ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL;
92 ddr->ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL;
93 ddr->ddr_cdr1 = CONFIG_SYS_DDR_CDR1;
94 ddr->timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4;
95 ddr->timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5;
97 if (!strcmp("performance", getenv("perf_mode"))) {
98 /* Performance Mode Values */
100 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG_PERF;
101 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS_PERF;
102 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS_PERF;
103 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_PERF;
104 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_PERF;
110 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL_PERF;
112 /* Stable Mode Values */
114 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
115 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
116 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
117 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
118 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
120 /* ECC will be assumed in stable mode */
121 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
122 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
123 ddr->err_sbe = CONFIG_SYS_DDR_SBE;
129 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
132 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
134 debug("DDR - 1st controller: memory initializing\n");
136 * Poll until memory is initialized.
137 * 512 Meg at 400 might hit this 200 times or so.
139 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
141 debug("DDR: memory initialized\n\n");
146 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
147 CONFIG_SYS_SDRAM_SIZE * 1024 * 1024,
148 LAW_TRGT_IF_DDR) < 0) {
149 printf("ERROR setting Local Access Windows for DDR\n");
153 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
159 static struct pci_controller pcie1_hose;
163 static struct pci_controller pcie2_hose;
167 static struct pci_controller pcie3_hose;
171 void pci_init_board(void)
173 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
174 struct fsl_pci_info pci_info[3];
175 u32 devdisr, pordevsr, io_sel;
176 int first_free_busno = 0;
179 int pcie_ep, pcie_configured;
181 devdisr = in_be32(&gur->devdisr);
182 pordevsr = in_be32(&gur->pordevsr);
183 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
185 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
189 pcie_configured = is_serdes_configured(PCIE2);
191 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)) {
192 SET_STD_PCIE_INFO(pci_info[num], 2);
193 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
194 printf("PCIE2: connected to ULI as %s (base addr %lx)\n",
195 pcie_ep ? "Endpoint" : "Root Complex",
197 first_free_busno = fsl_pci_init_port(&pci_info[num++],
198 &pcie2_hose, first_free_busno);
201 * The workaround doesn't work on p2020 because the location
202 * we try and read isn't valid on p2020, fix this later
206 * Activate ULI1575 legacy chip by performing a fake
207 * memory access. Needed to make ULI RTC work.
208 * Device 1d has the first on-board memory BAR.
211 pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0),
212 PCI_BASE_ADDRESS_1, &temp32);
213 if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
214 void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
216 debug(" uli1575 read to %p\n", p);
221 printf("PCIE2: disabled\n");
225 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
229 pcie_configured = is_serdes_configured(PCIE3);
231 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)) {
232 SET_STD_PCIE_INFO(pci_info[num], 3);
233 pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
234 printf("PCIE3: connected to Slot 1 as %s (base addr %lx)\n",
235 pcie_ep ? "Endpoint" : "Root Complex",
237 first_free_busno = fsl_pci_init_port(&pci_info[num++],
238 &pcie3_hose, first_free_busno);
240 printf("PCIE3: disabled\n");
244 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
248 pcie_configured = is_serdes_configured(PCIE1);
250 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
251 SET_STD_PCIE_INFO(pci_info[num], 1);
252 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
253 printf("PCIE1: connected to Slot 2 as %s (base addr %lx)\n",
254 pcie_ep ? "Endpoint" : "Root Complex",
256 first_free_busno = fsl_pci_init_port(&pci_info[num++],
257 &pcie1_hose, first_free_busno);
259 printf("PCIE1: disabled\n");
263 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
268 int board_early_init_r(void)
270 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
271 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
274 * Remap Boot flash + PROMJET region to caching-inhibited
275 * so that flash can be erased properly.
278 /* Flush d-cache and invalidate i-cache of any FLASH data */
282 /* invalidate existing TLB entry for flash + promjet */
283 disable_tlb(flash_esel);
285 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
286 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
287 0, flash_esel, BOOKE_PAGESZ_256M, 1);
292 #ifdef CONFIG_TSEC_ENET
293 int board_eth_init(bd_t *bis)
295 struct tsec_info_struct tsec_info[4];
299 SET_STD_TSEC_INFO(tsec_info[num], 1);
303 SET_STD_TSEC_INFO(tsec_info[num], 2);
304 if (is_serdes_configured(SGMII_TSEC2)) {
305 puts("eTSEC2 is in sgmii mode.\n");
306 tsec_info[num].flags |= TSEC_SGMII;
311 SET_STD_TSEC_INFO(tsec_info[num], 3);
312 if (is_serdes_configured(SGMII_TSEC3)) {
313 puts("eTSEC3 is in sgmii mode.\n");
314 tsec_info[num].flags |= TSEC_SGMII;
320 printf("No TSECs initialized\n");
325 #ifdef CONFIG_FSL_SGMII_RISER
326 fsl_sgmii_riser_init(tsec_info, num);
329 tsec_eth_init(bis, tsec_info, num);
331 return pci_eth_init(bis);
335 #if defined(CONFIG_OF_BOARD_SETUP)
336 void ft_board_setup(void *blob, bd_t *bd)
341 ft_cpu_setup(blob, bd);
343 base = getenv_bootm_low();
344 size = getenv_bootm_size();
346 fdt_fixup_memory(blob, (u64)base, (u64)size);
350 #ifdef CONFIG_FSL_SGMII_RISER
351 fsl_sgmii_riser_fdt_fixup(blob);
357 void board_lmb_reserve(struct lmb *lmb)
359 cpu_mp_lmb_reserve(lmb);