2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
13 #include <asm/fsl_ddr_sdram.h>
14 #include <asm/fsl_ddr_dimm_params.h>
15 #include <asm/fsl_law.h>
20 * Fixed sdram init -- doesn't use serial presence detect.
23 phys_size_t fixed_sdram(void)
27 fsl_ddr_cfg_regs_t ddr_cfg_regs;
29 unsigned int lawbar1_target_id;
30 ulong ddr_freq, ddr_freq_mhz;
32 ddr_freq = get_ddr_freq(0);
33 ddr_freq_mhz = ddr_freq / 1000000;
35 printf("Configuring DDR for %s MT/s data rate\n",
36 strmhz(buf, ddr_freq));
38 for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
39 if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
40 (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
42 fixed_ddr_parm_0[i].ddr_settings,
43 sizeof(ddr_cfg_regs));
48 if (fixed_ddr_parm_0[i].max_freq == 0)
49 panic("Unsupported DDR data rate %s MT/s data rate\n",
50 strmhz(buf, ddr_freq));
52 ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
53 ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
54 fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
57 * setup laws for DDR. If not interleaving, presuming half memory on
58 * DDR1 and the other half on DDR2
60 if (fixed_ddr_parm_0[i].ddr_settings->cs[0].config & 0x20000000) {
61 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
63 LAW_TRGT_IF_DDR_INTRLV) < 0) {
64 printf("ERROR setting Local Access Windows for DDR\n");
68 lawbar1_target_id = LAW_TRGT_IF_DDR_1;
69 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
71 lawbar1_target_id) < 0) {
72 printf("ERROR setting Local Access Windows for DDR\n");
79 struct board_specific_params {
81 u32 datarate_mhz_high;
90 * This table contains all valid speeds we want to override with board
91 * specific parameters. datarate_mhz_high values need to be in ascending order
92 * for each n_ranks group.
94 static const struct board_specific_params udimm[] = {
97 * num| hi| clk| wrlvl | cpo |wrdata|2T
98 * ranks| mhz|adjst| start | |delay |
100 {4, 850, 4, 6, 0xff, 2, 0},
101 {4, 950, 5, 7, 0xff, 2, 0},
102 {4, 1050, 5, 8, 0xff, 2, 0},
103 {4, 1250, 5, 10, 0xff, 2, 0},
104 {4, 1350, 5, 11, 0xff, 2, 0},
105 {4, 1666, 5, 12, 0xff, 2, 0},
106 {2, 850, 5, 6, 0xff, 2, 0},
107 {2, 950, 5, 7, 0xff, 2, 0},
108 {2, 1250, 4, 6, 0xff, 2, 0},
109 {2, 1350, 5, 7, 0xff, 2, 0},
110 {2, 1666, 5, 8, 0xff, 2, 0},
111 {1, 850, 4, 5, 0xff, 2, 0},
112 {1, 950, 4, 7, 0xff, 2, 0},
113 {1, 1666, 4, 8, 0xff, 2, 0},
117 static const struct board_specific_params rdimm[] = {
119 * memory controller 0
120 * num| hi| clk| wrlvl | cpo |wrdata|2T
121 * ranks| mhz|adjst| start | |delay |
123 {4, 850, 4, 6, 0xff, 2, 0},
124 {4, 950, 5, 7, 0xff, 2, 0},
125 {4, 1050, 5, 8, 0xff, 2, 0},
126 {4, 1250, 5, 10, 0xff, 2, 0},
127 {4, 1350, 5, 11, 0xff, 2, 0},
128 {4, 1666, 5, 12, 0xff, 2, 0},
129 {2, 850, 4, 6, 0xff, 2, 0},
130 {2, 1050, 4, 7, 0xff, 2, 0},
131 {2, 1666, 4, 8, 0xff, 2, 0},
132 {1, 850, 4, 5, 0xff, 2, 0},
133 {1, 950, 4, 7, 0xff, 2, 0},
134 {1, 1666, 4, 8, 0xff, 2, 0},
138 void fsl_ddr_board_options(memctl_options_t *popts,
139 dimm_params_t *pdimm,
140 unsigned int ctrl_num)
142 const struct board_specific_params *pbsp, *pbsp_highest = NULL;
146 printf("Wrong parameter for controller number %d", ctrl_num);
152 if (popts->registered_dimm_en)
157 /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
158 * freqency and n_banks specified in board_specific_parameters table.
160 ddr_freq = get_ddr_freq(0) / 1000000;
161 while (pbsp->datarate_mhz_high) {
162 if (pbsp->n_ranks == pdimm->n_ranks) {
163 if (ddr_freq <= pbsp->datarate_mhz_high) {
164 popts->cpo_override = pbsp->cpo;
165 popts->write_data_delay =
166 pbsp->write_data_delay;
167 popts->clk_adjust = pbsp->clk_adjust;
168 popts->wrlvl_start = pbsp->wrlvl_start;
169 popts->twoT_en = pbsp->force_2T;
178 printf("Error: board specific timing not found "
179 "for data rate %lu MT/s!\n"
180 "Trying to use the highest speed (%u) parameters\n",
181 ddr_freq, pbsp_highest->datarate_mhz_high);
182 popts->cpo_override = pbsp_highest->cpo;
183 popts->write_data_delay = pbsp_highest->write_data_delay;
184 popts->clk_adjust = pbsp_highest->clk_adjust;
185 popts->wrlvl_start = pbsp_highest->wrlvl_start;
186 popts->twoT_en = pbsp_highest->force_2T;
188 panic("DIMM is not supported by this board");
195 * The datasheet of HMT125U7BFR8C-H9 blocks CL=7 as reservered.
196 * However SPD still claims CL=7 is supported. Extensive tests
197 * confirmed this board cannot work stably with CL=7 with this
200 if (ddr_freq >= 800 && ddr_freq < 1066 && \
201 !strncmp(pdimm[0].mpart, "HMT125U7BFR8C-H9", 16)) {
202 popts->cas_latency_override = 1;
203 popts->cas_latency_override_value = 8;
204 debug("Override CL to 8\n");
207 * Factors to consider for half-strength driver enable:
208 * - number of DIMMs installed
210 popts->half_strength_driver_enable = 0;
212 * Write leveling override
214 popts->wrlvl_override = 1;
215 popts->wrlvl_sample = 0xf;
218 * Rtt and Rtt_WR override
220 popts->rtt_override = 0;
222 /* Enable ZQ calibration */
225 /* DHC_EN =1, ODT = 60 Ohm */
226 popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
229 phys_size_t initdram(int board_type)
231 phys_size_t dram_size;
233 puts("Initializing....");
237 dram_size = fsl_ddr_sdram();
239 puts("using fixed parameters\n");
240 dram_size = fixed_sdram();
243 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
244 dram_size *= 0x100000;