2 * Copyright 2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/processor.h>
28 #include <asm/cache.h>
29 #include <asm/immap_85xx.h>
30 #include <asm/fsl_law.h>
31 #include <asm/fsl_ddr_sdram.h>
32 #include <asm/fsl_serdes.h>
33 #include <asm/fsl_portals.h>
34 #include <asm/fsl_liodn.h>
40 #include <asm/fsl_dtsec.h>
42 #include "../common/qixis.h"
43 #include "../common/fman.h"
45 #include "p3060qds_qixis.h"
47 #define EMI_NONE 0xffffffff
54 static int mdio_mux[NUM_FM_PORTS];
56 static char *mdio_names[5] = {
65 * Mapping of all 18 SERDES lanes to board slots.
66 * A value of '0' here means that the mapping must be determined
67 * dynamically, Lane 8/9/16/17 map to Slot1 or Aurora debug
69 static u8 lane_to_slot[] = {
70 4, 4, 4, 4, 3, 3, 3, 3, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0
73 static char *p3060qds_mdio_name_for_muxval(u32 muxval)
75 return mdio_names[muxval];
78 struct mii_dev *mii_dev_for_muxval(u32 muxval)
81 char *name = p3060qds_mdio_name_for_muxval(muxval);
84 printf("No bus for muxval %x\n", muxval);
88 bus = miiphy_get_dev_by_name(name);
91 printf("No bus by name %s\n", name);
98 struct p3060qds_mdio {
100 struct mii_dev *realbus;
103 static void p3060qds_mux_mdio(u32 muxval)
107 brdcfg4 = QIXIS_READ(brdcfg[4]);
108 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
109 brdcfg4 |= (muxval << 4);
110 QIXIS_WRITE(brdcfg[4], brdcfg4);
113 static int p3060qds_mdio_read(struct mii_dev *bus, int addr, int devad,
116 struct p3060qds_mdio *priv = bus->priv;
118 p3060qds_mux_mdio(priv->muxval);
120 return priv->realbus->read(priv->realbus, addr, devad, regnum);
123 static int p3060qds_mdio_write(struct mii_dev *bus, int addr, int devad,
124 int regnum, u16 value)
126 struct p3060qds_mdio *priv = bus->priv;
128 p3060qds_mux_mdio(priv->muxval);
130 return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
133 static int p3060qds_mdio_reset(struct mii_dev *bus)
135 struct p3060qds_mdio *priv = bus->priv;
137 return priv->realbus->reset(priv->realbus);
140 static int p3060qds_mdio_init(char *realbusname, u32 muxval)
142 struct p3060qds_mdio *pmdio;
143 struct mii_dev *bus = mdio_alloc();
146 printf("Failed to allocate P3060QDS MDIO bus\n");
150 pmdio = malloc(sizeof(*pmdio));
152 printf("Failed to allocate P3060QDS private data\n");
157 bus->read = p3060qds_mdio_read;
158 bus->write = p3060qds_mdio_write;
159 bus->reset = p3060qds_mdio_reset;
160 sprintf(bus->name, p3060qds_mdio_name_for_muxval(muxval));
162 pmdio->realbus = miiphy_get_dev_by_name(realbusname);
164 if (!pmdio->realbus) {
165 printf("No bus with name %s\n", realbusname);
171 pmdio->muxval = muxval;
174 return mdio_register(bus);
177 void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
178 enum fm_port port, int offset)
180 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
181 int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
182 FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
184 if (mdio_mux[port] == EMI1_RGMII1)
185 fdt_set_phy_handle(blob, prop, pa, "phy_rgmii1");
187 if (mdio_mux[port] == EMI1_RGMII2)
188 fdt_set_phy_handle(blob, prop, pa, "phy_rgmii2");
190 if ((mdio_mux[port] == EMI1_SLOT1) && ((srds_prtcl == 0x3)
191 || (srds_prtcl == 0x6))) {
194 fdt_set_phy_handle(blob, prop, pa, "phy2_slot1");
197 fdt_set_phy_handle(blob, prop, pa, "phy3_slot1");
204 if (mdio_mux[port] == EMI1_SLOT3) {
207 fdt_set_phy_handle(blob, prop, pa, "phy0_slot3");
210 fdt_set_phy_handle(blob, prop, pa, "phy1_slot3");
218 void fdt_fixup_board_enet(void *fdt)
222 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
223 idx = i - FM1_DTSEC1;
224 switch (fm_info_get_enet_if(i)) {
225 case PHY_INTERFACE_MODE_SGMII:
226 lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
230 switch (mdio_mux[i]) {
233 fdt_status_okay_by_alias(fdt,
235 fdt_status_disabled_by_alias(fdt,
238 fdt_status_disabled_by_alias(fdt,
240 fdt_status_okay_by_alias(fdt,
245 fdt_status_okay_by_alias(fdt, "emi1_slot2");
248 fdt_status_okay_by_alias(fdt, "emi1_slot3");
252 case PHY_INTERFACE_MODE_RGMII:
254 fdt_status_okay_by_alias(fdt, "emi1_rgmii1");
257 fdt_status_okay_by_alias(fdt, "emi1_rgmii2");
263 #if (CONFIG_SYS_NUM_FMAN == 2)
264 for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
265 idx = i - FM2_DTSEC1;
266 switch (fm_info_get_enet_if(i)) {
267 case PHY_INTERFACE_MODE_SGMII:
268 lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
270 switch (mdio_mux[i]) {
273 fdt_status_okay_by_alias(fdt,
276 fdt_status_okay_by_alias(fdt,
280 fdt_status_okay_by_alias(fdt,
284 fdt_status_okay_by_alias(fdt,
297 static void initialize_lane_to_slot(void)
299 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
300 int sdprtl = (in_be32(&gur->rcwsr[4]) &
301 FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
307 lane_to_slot[9] = lane_to_slot[8];
308 lane_to_slot[16] = 5;
309 lane_to_slot[17] = lane_to_slot[16];
315 lane_to_slot[9] = lane_to_slot[8];
316 lane_to_slot[16] = 1;
317 lane_to_slot[17] = lane_to_slot[16];
320 puts("Invalid SerDes protocol for P3060QDS\n");
325 int board_eth_init(bd_t *bis)
327 #ifdef CONFIG_FMAN_ENET
328 struct dtsec *tsec = (void *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR;
330 struct fsl_pq_mdio_info dtsec_mdio_info;
331 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
332 int srds_cfg = (in_be32(&gur->rcwsr[4]) &
333 FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
335 initialize_lane_to_slot();
338 * Set TBIPA on FM1@DTSEC1. This is needed for configurations
339 * where FM1@DTSEC1 isn't used directly, since it provides
340 * MDIO for other ports.
342 out_be32(&tsec->tbipa, CONFIG_SYS_TBIPA_VALUE);
344 /* Initialize the mdio_mux array so we can recognize empty elements */
345 for (i = 0; i < NUM_FM_PORTS; i++)
346 mdio_mux[i] = EMI_NONE;
348 dtsec_mdio_info.regs =
349 (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
350 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
352 /* Register the 1G MDIO bus */
353 fsl_pq_mdio_init(bis, &dtsec_mdio_info);
355 /* Register the 5 muxing front-ends to the MDIO buses */
356 if (fm_info_get_enet_if(FM1_DTSEC1) == PHY_INTERFACE_MODE_RGMII)
357 p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
359 if (fm_info_get_enet_if(FM1_DTSEC2) == PHY_INTERFACE_MODE_RGMII)
360 p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
361 p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
362 p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
363 p3060qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
365 if (fm_info_get_enet_if(FM1_DTSEC1) == PHY_INTERFACE_MODE_RGMII)
366 fm_info_set_phy_address(FM1_DTSEC1, 1); /* RGMII1 */
367 else if (fm_info_get_enet_if(FM1_DTSEC1) == PHY_INTERFACE_MODE_SGMII)
368 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT2_PHY_ADDR);
370 if (fm_info_get_enet_if(FM1_DTSEC2) == PHY_INTERFACE_MODE_RGMII)
371 fm_info_set_phy_address(FM1_DTSEC2, 2); /* RGMII2 */
372 else if (fm_info_get_enet_if(FM1_DTSEC2) == PHY_INTERFACE_MODE_SGMII)
373 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
375 fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
376 fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT3_PHY_ADDR);
381 fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR);
382 fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT4_PHY_ADDR);
383 fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT1_PHY_ADDR);
384 fm_info_set_phy_address(FM1_DTSEC4, SGMII_CARD_PORT2_PHY_ADDR);
389 fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR);
390 fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT2_PHY_ADDR);
391 fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT3_PHY_ADDR);
392 fm_info_set_phy_address(FM1_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR);
395 puts("Invalid SerDes protocol for P3060QDS\n");
399 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
400 int idx = i - FM1_DTSEC1, lane, slot;
401 switch (fm_info_get_enet_if(i)) {
402 case PHY_INTERFACE_MODE_SGMII:
403 lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
406 slot = lane_to_slot[lane];
407 if (QIXIS_READ(present) & (1 << (slot - 1)))
411 mdio_mux[i] = EMI1_SLOT1;
413 mii_dev_for_muxval(mdio_mux[i]));
416 mdio_mux[i] = EMI1_SLOT2;
418 mii_dev_for_muxval(mdio_mux[i]));
421 mdio_mux[i] = EMI1_SLOT3;
423 mii_dev_for_muxval(mdio_mux[i]));
427 case PHY_INTERFACE_MODE_RGMII:
428 if (i == FM1_DTSEC1) {
429 mdio_mux[i] = EMI1_RGMII1;
431 mii_dev_for_muxval(mdio_mux[i]));
432 } else if (i == FM1_DTSEC2) {
433 mdio_mux[i] = EMI1_RGMII2;
435 mii_dev_for_muxval(mdio_mux[i]));
443 #if (CONFIG_SYS_NUM_FMAN == 2)
444 for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
445 int idx = i - FM2_DTSEC1, lane, slot;
446 switch (fm_info_get_enet_if(i)) {
447 case PHY_INTERFACE_MODE_SGMII:
448 lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
451 slot = lane_to_slot[lane];
452 if (QIXIS_READ(present) & (1 << (slot - 1)))
456 mdio_mux[i] = EMI1_SLOT1;
458 mii_dev_for_muxval(mdio_mux[i]));
461 mdio_mux[i] = EMI1_SLOT2;
463 mii_dev_for_muxval(mdio_mux[i]));
466 mdio_mux[i] = EMI1_SLOT3;
468 mii_dev_for_muxval(mdio_mux[i]));
476 #endif /* CONFIG_SYS_NUM_FMAN */
479 #endif /* CONFIG_FMAN_ENET */
481 return pci_eth_init(bis);