board/freescale/t104xrdb/eth.c

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <netdev.h>
   9 #include <asm/fsl_serdes.h>
  10 #include <asm/immap_85xx.h>
  11 #include <fm_eth.h>
  12 #include <fsl_mdio.h>
  13 #include <malloc.h>
  14 #include <asm/fsl_dtsec.h>
  15 #include <vsc9953.h>
  16
  17 #include "../common/fman.h"
  18
  19 int board_eth_init(bd_t *bis)
  20 {
  21 #ifdef CONFIG_FMAN_ENET
  22         struct memac_mdio_info memac_mdio_info;
  23         unsigned int i;
  24         int phy_addr = 0;
  25 #ifdef CONFIG_VSC9953
  26         phy_interface_t phy_int;
  27         struct mii_dev *bus;
  28 #endif
  29
  30         printf("Initializing Fman\n");
  31
  32         memac_mdio_info.regs =
  33                 (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
  34         memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
  35
  36         /* Register the real 1G MDIO bus */
  37         fm_memac_mdio_init(bis, &memac_mdio_info);
  38
  39         /*
  40          * Program on board RGMII, SGMII PHY addresses.
  41          */
  42         for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
  43                 int idx = i - FM1_DTSEC1;
  44
  45                 switch (fm_info_get_enet_if(i)) {
  46 #ifdef CONFIG_T1040RDB
  47                 case PHY_INTERFACE_MODE_SGMII:
  48                         /* T1040RDB only supports SGMII on DTSEC3 */
  49                         fm_info_set_phy_address(FM1_DTSEC3,
  50                                                 CONFIG_SYS_SGMII1_PHY_ADDR);
  51                         break;
  52 #endif
  53 #ifdef CONFIG_T1042RDB
  54                 case PHY_INTERFACE_MODE_SGMII:
  55                         /* T1042RDB doesn't supports SGMII on DTSEC1 & DTSEC2 */
  56                         if ((FM1_DTSEC1 == i) || (FM1_DTSEC2 == i))
  57                                 fm_info_set_phy_address(i, 0);
  58                         /* T1042RDB only supports SGMII on DTSEC3 */
  59                         fm_info_set_phy_address(FM1_DTSEC3,
  60                                                 CONFIG_SYS_SGMII1_PHY_ADDR);
  61                         break;
  62 #endif
  63                 case PHY_INTERFACE_MODE_RGMII:
  64                         if (FM1_DTSEC4 == i)
  65                                 phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR;
  66                         if (FM1_DTSEC5 == i)
  67                                 phy_addr = CONFIG_SYS_RGMII2_PHY_ADDR;
  68                         fm_info_set_phy_address(i, phy_addr);
  69                         break;
  70                 case PHY_INTERFACE_MODE_QSGMII:
  71                         fm_info_set_phy_address(i, 0);
  72                         break;
  73                 case PHY_INTERFACE_MODE_NONE:
  74                         fm_info_set_phy_address(i, 0);
  75                         break;
  76                 default:
  77                         printf("Fman1: DTSEC%u set to unknown interface %i\n",
  78                                idx + 1, fm_info_get_enet_if(i));
  79                         fm_info_set_phy_address(i, 0);
  80                         break;
  81                 }
  82                 if (fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_QSGMII ||
  83                     fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_NONE)
  84                         fm_info_set_mdio(i, NULL);
  85                 else
  86                         fm_info_set_mdio(i,
  87                                          miiphy_get_dev_by_name(
  88                                                         DEFAULT_FM_MDIO_NAME));
  89         }
  90
  91 #ifdef CONFIG_VSC9953
  92         /* SerDes configured for QSGMII */
  93         if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A) >= 0) {
  94                 for (i = 0; i < 4; i++) {
  95                         bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
  96                         phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR + i;
  97                         phy_int = PHY_INTERFACE_MODE_QSGMII;
  98
  99                         vsc9953_port_info_set_mdio(i, bus);
 100                         vsc9953_port_info_set_phy_address(i, phy_addr);
 101                         vsc9953_port_info_set_phy_int(i, phy_int);
 102                         vsc9953_port_enable(i);
 103                 }
 104         }
 105         if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B) >= 0) {
 106                 for (i = 4; i < 8; i++) {
 107                         bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
 108                         phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR + i - 4;
 109                         phy_int = PHY_INTERFACE_MODE_QSGMII;
 110
 111                         vsc9953_port_info_set_mdio(i, bus);
 112                         vsc9953_port_info_set_phy_address(i, phy_addr);
 113                         vsc9953_port_info_set_phy_int(i, phy_int);
 114                         vsc9953_port_enable(i);
 115                 }
 116         }
 117
 118         /* Connect DTSEC1 to L2 switch if it doesn't have a PHY */
 119         if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1) < 0)
 120                 vsc9953_port_enable(8);
 121
 122         /* Connect DTSEC2 to L2 switch if it doesn't have a PHY */
 123         if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC2) < 0) {
 124                 /* Enable L2 On MAC2 using SCFG */
 125                 struct ccsr_scfg *scfg = (struct ccsr_scfg *)
 126                                 CONFIG_SYS_MPC85xx_SCFG;
 127
 128                 out_be32(&scfg->esgmiiselcr, in_be32(&scfg->esgmiiselcr) |
 129                          (0x80000000));
 130                 vsc9953_port_enable(9);
 131         }
 132 #endif
 133
 134         cpu_eth_init(bis);
 135 #endif
 136
 137         return pci_eth_init(bis);
 138 }