2 * Copyright 2009-2013 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/compiler.h>
13 #include <asm/processor.h>
14 #include <asm/immap_85xx.h>
15 #include <asm/fsl_law.h>
16 #include <asm/fsl_serdes.h>
17 #include <asm/fsl_portals.h>
18 #include <asm/fsl_liodn.h>
21 #include "../common/qixis.h"
22 #include "../common/vsc3316_3308.h"
24 #include "t2080qds_qixis.h"
26 DECLARE_GLOBAL_DATA_PTR;
32 struct cpu_type *cpu = gd->arch.cpu;
33 static const char *freq[4] = {
34 "100.00MHZ(from 8T49N222A)", "125.00MHz",
35 "156.25MHZ", "100.00MHz"
38 printf("Board: %sQDS, ", cpu->name);
39 sw = QIXIS_READ(arch);
40 printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
41 printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
48 sw = QIXIS_READ(brdcfg[0]);
49 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
52 printf("vBank%d\n", sw);
58 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
61 printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver),
62 qixis_read_tag(buf), (int)qixis_read_minor());
63 /* the timestamp string contains "\n" at the end */
64 printf(" on %s", qixis_read_time(buf));
66 puts("SERDES Reference Clocks:\n");
67 sw = QIXIS_READ(brdcfg[2]);
68 printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[sw >> 6],
69 freq[(sw >> 4) & 0x3]);
70 printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[(sw & 0xf) >> 2],
76 int select_i2c_ch_pca9547(u8 ch)
80 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
82 puts("PCA: failed to select proper channel\n");
89 int brd_mux_lane_to_slot(void)
91 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
92 u32 srds_prtcl_s1, srds_prtcl_s2;
94 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
95 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
96 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
97 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
98 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
99 srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
101 switch (srds_prtcl_s1) {
103 /* SerDes1 is not enabled */
107 /* SD1(A:D) => SLOT3 SGMII
108 * SD1(G:H) => SLOT1 SGMII
110 QIXIS_WRITE(brdcfg[12], 0x1a);
114 /* SD1(A:B) => SLOT3 SGMII@1.25bps
115 * SD1(C:D) => SFP Module, SGMII@3.125bps
116 * SD1(E:H) => SLOT1 SGMII@1.25bps
119 /* SD1(A:B) => SLOT3 SGMII@1.25bps
120 * SD1(C) => SFP Module, SGMII@3.125bps
121 * SD1(D) => SFP Module, SGMII@1.25bps
122 * SD1(E:H) => SLOT1 PCIe4 x4
124 QIXIS_WRITE(brdcfg[12], 0x3a);
127 /* SD1(A:D) => SLOT3 XAUI
128 * SD1(E) => SLOT1 PCIe4
129 * SD1(F:H) => SLOT2 SGMII
131 QIXIS_WRITE(brdcfg[12], 0x15);
135 /* SD1(A:D) => XFI cage
136 * SD1(E:H) => SLOT1 PCIe4
138 QIXIS_WRITE(brdcfg[12], 0xfe);
141 /* SD1(A:D) => XFI cage
142 * SD1(E) => SLOT1 PCIe4
143 * SD1(F:H) => SLOT2 SGMII
145 QIXIS_WRITE(brdcfg[12], 0xf1);
149 /* SD1(A:B) => XFI cage
150 * SD1(C:D) => SLOT3 SGMII
151 * SD1(E:H) => SLOT1 PCIe4
153 QIXIS_WRITE(brdcfg[12], 0xda);
156 /* SD1(A:B) => SFP Module, XFI
157 * SD1(C:D) => SLOT3 SGMII
158 * SD1(E:F) => SLOT1 PCIe4 x2
159 * SD1(G:H) => SLOT2 SGMII
161 QIXIS_WRITE(brdcfg[12], 0xd9);
164 /* SD1(A:H) => SLOT3 PCIe3 x8
166 QIXIS_WRITE(brdcfg[12], 0x0);
169 /* SD1(A) => SLOT3 PCIe3 x1
170 * SD1(B) => SFP Module, SGMII@1.25bps
171 * SD1(C:D) => SFP Module, SGMII@3.125bps
172 * SD1(E:F) => SLOT1 PCIe4 x2
173 * SD1(G:H) => SLOT2 SGMII
175 QIXIS_WRITE(brdcfg[12], 0x79);
178 /* SD1(A:D) => SLOT3 PCIe3 x4
179 * SD1(E:H) => SLOT1 PCIe4 x4
181 QIXIS_WRITE(brdcfg[12], 0x1a);
184 printf("WARNING: unsupported for SerDes1 Protocol %d\n",
189 switch (srds_prtcl_s2) {
191 /* SerDes2 is not enabled */
195 /* SD2(A:H) => SLOT4 PCIe1 */
196 QIXIS_WRITE(brdcfg[13], 0x10);
201 * SD2(A:D) => SLOT4 PCIe1
202 * SD2(E:F) => SLOT5 PCIe2
203 * SD2(G:H) => SATA1,SATA2
205 QIXIS_WRITE(brdcfg[13], 0xb0);
209 * SD2(A:D) => SLOT4 PCIe1
210 * SD2(E:F) => SLOT5 Aurora
211 * SD2(G:H) => SATA1,SATA2
213 QIXIS_WRITE(brdcfg[13], 0x78);
217 * SD2(A:D) => SLOT4 PCIe1
218 * SD2(E:H) => SLOT5 PCIe2
220 QIXIS_WRITE(brdcfg[13], 0xa0);
226 * SD2(A:D) => SLOT4 SRIO2
227 * SD2(E:H) => SLOT5 SRIO1
229 QIXIS_WRITE(brdcfg[13], 0xa0);
233 * SD2(A:D) => SLOT4 SRIO2
235 * SD2(G:H) => SATA1,SATA2
237 QIXIS_WRITE(brdcfg[13], 0x78);
240 printf("WARNING: unsupported for SerDes2 Protocol %d\n",
247 int board_early_init_r(void)
249 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
250 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
253 * Remap Boot flash + PROMJET region to caching-inhibited
254 * so that flash can be erased properly.
257 /* Flush d-cache and invalidate i-cache of any FLASH data */
261 /* invalidate existing TLB entry for flash + promjet */
262 disable_tlb(flash_esel);
264 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
265 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
266 0, flash_esel, BOOKE_PAGESZ_256M, 1);
269 #ifdef CONFIG_SYS_DPAA_QBMAN
273 /* Disable remote I2C connection to qixis fpga */
274 QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
276 brd_mux_lane_to_slot();
277 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
282 unsigned long get_board_sys_clk(void)
284 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
285 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
286 /* use accurate clock measurement */
287 int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
288 int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
293 debug("SYS Clock measurement is: %d\n", val);
296 printf("Warning: SYS clock measurement is invalid, ");
297 printf("using value from brdcfg1.\n");
301 switch (sysclk_conf & 0x0F) {
302 case QIXIS_SYSCLK_83:
304 case QIXIS_SYSCLK_100:
306 case QIXIS_SYSCLK_125:
308 case QIXIS_SYSCLK_133:
310 case QIXIS_SYSCLK_150:
312 case QIXIS_SYSCLK_160:
314 case QIXIS_SYSCLK_166:
320 unsigned long get_board_ddr_clk(void)
322 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
323 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
324 /* use accurate clock measurement */
325 int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
326 int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
331 debug("DDR Clock measurement is: %d\n", val);
334 printf("Warning: DDR clock measurement is invalid, ");
335 printf("using value from brdcfg1.\n");
339 switch ((ddrclk_conf & 0x30) >> 4) {
340 case QIXIS_DDRCLK_100:
342 case QIXIS_DDRCLK_125:
344 case QIXIS_DDRCLK_133:
350 int misc_init_r(void)
355 void ft_board_setup(void *blob, bd_t *bd)
360 ft_cpu_setup(blob, bd);
362 base = getenv_bootm_low();
363 size = getenv_bootm_size();
365 fdt_fixup_memory(blob, (u64)base, (u64)size);
368 pci_of_setup(blob, bd);
371 fdt_fixup_liodn(blob);
372 fdt_fixup_dr_usb(blob, bd);
374 #ifdef CONFIG_SYS_DPAA_FMAN
375 fdt_fixup_fman_ethernet(blob);
376 fdt_fixup_board_enet(blob);