2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * Shengzhou Liu <Shengzhou.Liu@freescale.com>
6 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/processor.h>
14 #include <asm/immap_85xx.h>
15 #include <asm/fsl_law.h>
16 #include <asm/fsl_serdes.h>
17 #include <asm/fsl_portals.h>
18 #include <asm/fsl_liodn.h>
24 #include <asm/fsl_dtsec.h>
25 #include <asm/fsl_serdes.h>
26 #include "../common/qixis.h"
27 #include "../common/fman.h"
28 #include "t208xqds_qixis.h"
30 #define EMI_NONE 0xFFFFFFFF
34 #if defined(CONFIG_T2080QDS)
39 #elif defined(CONFIG_T2081QDS)
48 static int mdio_mux[NUM_FM_PORTS];
50 static const char * const mdio_names[] = {
51 #if defined(CONFIG_T2080QDS)
52 "T2080QDS_MDIO_RGMII1",
53 "T2080QDS_MDIO_RGMII2",
54 "T2080QDS_MDIO_SLOT1",
55 "T2080QDS_MDIO_SLOT3",
56 "T2080QDS_MDIO_SLOT4",
57 "T2080QDS_MDIO_SLOT5",
58 "T2080QDS_MDIO_SLOT2",
60 #elif defined(CONFIG_T2081QDS)
61 "T2081QDS_MDIO_RGMII1",
62 "T2081QDS_MDIO_RGMII2",
63 "T2081QDS_MDIO_SLOT1",
64 "T2081QDS_MDIO_SLOT2",
65 "T2081QDS_MDIO_SLOT3",
66 "T2081QDS_MDIO_SLOT5",
67 "T2081QDS_MDIO_SLOT6",
68 "T2081QDS_MDIO_SLOT7",
73 /* Map SerDes1 8 lanes to default slot, will be initialized dynamically */
74 #if defined(CONFIG_T2080QDS)
75 static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1};
76 #elif defined(CONFIG_T2081QDS)
77 static u8 lane_to_slot[] = {2, 2, 2, 2, 1, 1, 1, 1};
80 static const char *t208xqds_mdio_name_for_muxval(u8 muxval)
82 return mdio_names[muxval];
85 struct mii_dev *mii_dev_for_muxval(u8 muxval)
88 const char *name = t208xqds_mdio_name_for_muxval(muxval);
91 printf("No bus for muxval %x\n", muxval);
95 bus = miiphy_get_dev_by_name(name);
98 printf("No bus by name %s\n", name);
105 struct t208xqds_mdio {
107 struct mii_dev *realbus;
110 static void t208xqds_mux_mdio(u8 muxval)
114 brdcfg4 = QIXIS_READ(brdcfg[4]);
115 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
116 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
117 QIXIS_WRITE(brdcfg[4], brdcfg4);
121 static int t208xqds_mdio_read(struct mii_dev *bus, int addr, int devad,
124 struct t208xqds_mdio *priv = bus->priv;
126 t208xqds_mux_mdio(priv->muxval);
128 return priv->realbus->read(priv->realbus, addr, devad, regnum);
131 static int t208xqds_mdio_write(struct mii_dev *bus, int addr, int devad,
132 int regnum, u16 value)
134 struct t208xqds_mdio *priv = bus->priv;
136 t208xqds_mux_mdio(priv->muxval);
138 return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
141 static int t208xqds_mdio_reset(struct mii_dev *bus)
143 struct t208xqds_mdio *priv = bus->priv;
145 return priv->realbus->reset(priv->realbus);
148 static int t208xqds_mdio_init(char *realbusname, u8 muxval)
150 struct t208xqds_mdio *pmdio;
151 struct mii_dev *bus = mdio_alloc();
154 printf("Failed to allocate t208xqds MDIO bus\n");
158 pmdio = malloc(sizeof(*pmdio));
160 printf("Failed to allocate t208xqds private data\n");
165 bus->read = t208xqds_mdio_read;
166 bus->write = t208xqds_mdio_write;
167 bus->reset = t208xqds_mdio_reset;
168 sprintf(bus->name, t208xqds_mdio_name_for_muxval(muxval));
170 pmdio->realbus = miiphy_get_dev_by_name(realbusname);
172 if (!pmdio->realbus) {
173 printf("No bus with name %s\n", realbusname);
179 pmdio->muxval = muxval;
181 return mdio_register(bus);
184 void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
185 enum fm_port port, int offset)
189 struct fixed_link f_link;
190 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
191 u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
192 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
194 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
196 if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
197 phy = fm_info_get_phy_address(port);
199 #if defined(CONFIG_T2080QDS)
204 if (mdio_mux[port] == EMI1_SLOT2) {
205 sprintf(alias, "phy_sgmii_s2_%x", phy);
206 fdt_set_phy_handle(fdt, compat, addr, alias);
207 fdt_status_okay_by_alias(fdt, "emi1_slot2");
208 } else if (mdio_mux[port] == EMI1_SLOT3) {
209 sprintf(alias, "phy_sgmii_s3_%x", phy);
210 fdt_set_phy_handle(fdt, compat, addr, alias);
211 fdt_status_okay_by_alias(fdt, "emi1_slot3");
216 if (mdio_mux[port] == EMI1_SLOT1) {
217 sprintf(alias, "phy_sgmii_s1_%x", phy);
218 fdt_set_phy_handle(fdt, compat, addr, alias);
219 fdt_status_okay_by_alias(fdt, "emi1_slot1");
220 } else if (mdio_mux[port] == EMI1_SLOT2) {
221 sprintf(alias, "phy_sgmii_s2_%x", phy);
222 fdt_set_phy_handle(fdt, compat, addr, alias);
223 fdt_status_okay_by_alias(fdt, "emi1_slot2");
226 #elif defined(CONFIG_T2081QDS)
233 if (mdio_mux[port] == EMI1_SLOT2) {
234 sprintf(alias, "phy_sgmii_s2_%x", phy);
235 fdt_set_phy_handle(fdt, compat, addr, alias);
236 fdt_status_okay_by_alias(fdt, "emi1_slot2");
237 } else if (mdio_mux[port] == EMI1_SLOT3) {
238 sprintf(alias, "phy_sgmii_s3_%x", phy);
239 fdt_set_phy_handle(fdt, compat, addr, alias);
240 fdt_status_okay_by_alias(fdt, "emi1_slot3");
241 } else if (mdio_mux[port] == EMI1_SLOT5) {
242 sprintf(alias, "phy_sgmii_s5_%x", phy);
243 fdt_set_phy_handle(fdt, compat, addr, alias);
244 fdt_status_okay_by_alias(fdt, "emi1_slot5");
245 } else if (mdio_mux[port] == EMI1_SLOT6) {
246 sprintf(alias, "phy_sgmii_s6_%x", phy);
247 fdt_set_phy_handle(fdt, compat, addr, alias);
248 fdt_status_okay_by_alias(fdt, "emi1_slot6");
249 } else if (mdio_mux[port] == EMI1_SLOT7) {
250 sprintf(alias, "phy_sgmii_s7_%x", phy);
251 fdt_set_phy_handle(fdt, compat, addr, alias);
252 fdt_status_okay_by_alias(fdt, "emi1_slot7");
260 } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
262 case 0x66: /* XFI interface */
267 f_link.phy_id = port;
269 f_link.link_speed = 10000;
271 f_link.asym_pause = 0;
273 fdt_delprop(fdt, offset, "phy-handle");
274 fdt_setprop(fdt, offset, "fixed-link", &f_link,
283 void fdt_fixup_board_enet(void *fdt)
289 * This function reads RCW to check if Serdes1{A:H} is configured
290 * to slot 1/2/3/4/5/6/7 and update the lane_to_slot[] array accordingly
292 static void initialize_lane_to_slot(void)
294 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
295 u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
296 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
298 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
301 #if defined(CONFIG_T2080QDS)
328 #elif defined(CONFIG_T2081QDS)
358 int board_eth_init(bd_t *bis)
360 #if defined(CONFIG_FMAN_ENET)
361 int i, idx, lane, slot, interface;
362 struct memac_mdio_info dtsec_mdio_info;
363 struct memac_mdio_info tgec_mdio_info;
364 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
365 u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
368 srds_s1 = in_be32(&gur->rcwsr[4]) &
369 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
370 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
372 initialize_lane_to_slot();
374 /* Initialize the mdio_mux array so we can recognize empty elements */
375 for (i = 0; i < NUM_FM_PORTS; i++)
376 mdio_mux[i] = EMI_NONE;
378 dtsec_mdio_info.regs =
379 (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
381 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
383 /* Register the 1G MDIO bus */
384 fm_memac_mdio_init(bis, &dtsec_mdio_info);
386 tgec_mdio_info.regs =
387 (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
388 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
390 /* Register the 10G MDIO bus */
391 fm_memac_mdio_init(bis, &tgec_mdio_info);
393 /* Register the muxing front-ends to the MDIO buses */
394 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
395 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
396 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
397 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
398 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
399 #if defined(CONFIG_T2080QDS)
400 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
402 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
403 #if defined(CONFIG_T2081QDS)
404 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6);
405 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
407 t208xqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
409 /* Set the two on-board RGMII PHY address */
410 fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
411 if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
412 FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII)
413 fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
415 fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR);
422 /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot2 */
423 fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
424 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
425 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
426 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
427 /* T2080QDS: SGMII in Slot2; T2081QDS: SGMII in Slot1 */
428 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
429 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
434 /* T2080QDS: XAUI/HiGig in Slot3; T2081QDS: in Slot2 */
435 fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
436 /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */
437 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
438 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
442 * XFI does not need a PHY to work, but to avoid U-boot use
443 * default PHY address which is zero to a MAC when it found
444 * a MAC has no PHY address, we give a PHY address to XFI
445 * MAC, and should not use a real XAUI PHY address, since
446 * MDIO can access it successfully, and then MDIO thinks
447 * the XAUI card is used for the XFI MAC, which will cause
450 fm_info_set_phy_address(FM1_10GEC1, 4);
451 fm_info_set_phy_address(FM1_10GEC2, 5);
452 fm_info_set_phy_address(FM1_10GEC3, 6);
453 fm_info_set_phy_address(FM1_10GEC4, 7);
456 fm_info_set_phy_address(FM1_10GEC1, 4);
457 fm_info_set_phy_address(FM1_10GEC2, 5);
458 fm_info_set_phy_address(FM1_10GEC3, 6);
459 fm_info_set_phy_address(FM1_10GEC4, 7);
460 /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */
461 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
462 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
466 fm_info_set_phy_address(FM1_10GEC1, 4);
467 fm_info_set_phy_address(FM1_10GEC2, 5);
468 /* T2080QDS: SGMII in Slot3; T2081QDS: in Slot2 */
469 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
470 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
474 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
475 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
477 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
478 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
486 fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
487 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
488 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
489 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
491 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
492 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
498 fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
499 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
500 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
501 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
503 #if defined(CONFIG_T2080QDS)
508 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
509 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
510 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
512 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
513 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
515 #elif defined(CONFIG_T2081QDS)
519 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
520 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
522 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
524 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
526 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
530 /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot7 */
531 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
532 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
533 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
534 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
540 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
541 idx = i - FM1_DTSEC1;
542 interface = fm_info_get_enet_if(i);
544 case PHY_INTERFACE_MODE_SGMII:
545 lane = serdes_get_first_lane(FSL_SRDS_1,
546 SGMII_FM1_DTSEC1 + idx);
549 slot = lane_to_slot[lane];
550 debug("FM1@DTSEC%u expects SGMII in slot %u\n",
552 if (QIXIS_READ(present2) & (1 << (slot - 1)))
557 mdio_mux[i] = EMI1_SLOT1;
558 fm_info_set_mdio(i, mii_dev_for_muxval(
562 mdio_mux[i] = EMI1_SLOT2;
563 fm_info_set_mdio(i, mii_dev_for_muxval(
567 mdio_mux[i] = EMI1_SLOT3;
568 fm_info_set_mdio(i, mii_dev_for_muxval(
571 #if defined(CONFIG_T2081QDS)
573 mdio_mux[i] = EMI1_SLOT5;
574 fm_info_set_mdio(i, mii_dev_for_muxval(
578 mdio_mux[i] = EMI1_SLOT6;
579 fm_info_set_mdio(i, mii_dev_for_muxval(
583 mdio_mux[i] = EMI1_SLOT7;
584 fm_info_set_mdio(i, mii_dev_for_muxval(
590 case PHY_INTERFACE_MODE_RGMII:
592 mdio_mux[i] = EMI1_RGMII1;
593 else if (i == FM1_DTSEC4 || FM1_DTSEC10)
594 mdio_mux[i] = EMI1_RGMII2;
595 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
602 for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
603 idx = i - FM1_10GEC1;
604 switch (fm_info_get_enet_if(i)) {
605 case PHY_INTERFACE_MODE_XGMII:
606 if (srds_s1 == 0x51) {
607 lane = serdes_get_first_lane(FSL_SRDS_1,
608 XAUI_FM1_MAC9 + idx);
609 } else if ((srds_s1 == 0x5f) || (srds_s1 == 0x65)) {
610 lane = serdes_get_first_lane(FSL_SRDS_1,
611 HIGIG_FM1_MAC9 + idx);
613 if (i == FM1_10GEC1 || i == FM1_10GEC2)
614 lane = serdes_get_first_lane(FSL_SRDS_1,
617 lane = serdes_get_first_lane(FSL_SRDS_1,
624 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
626 if ((srds_s1 == 0x66) || (srds_s1 == 0x6b) ||
627 (srds_s1 == 0x6c) || (srds_s1 == 0x6d) ||
629 /* As XFI is in cage intead of a slot, so
630 * ensure doesn't disable the corresponding port
635 slot = lane_to_slot[lane];
636 if (QIXIS_READ(present2) & (1 << (slot - 1)))
645 #endif /* CONFIG_FMAN_ENET */
647 return pci_eth_init(bis);