2 * Copyright 2009-2012 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <linux/compiler.h>
29 #include <asm/processor.h>
30 #include <asm/cache.h>
31 #include <asm/immap_85xx.h>
32 #include <asm/fsl_law.h>
33 #include <asm/fsl_serdes.h>
34 #include <asm/fsl_portals.h>
35 #include <asm/fsl_liodn.h>
38 #include "../common/qixis.h"
39 #include "../common/vsc3316_3308.h"
41 #include "t4240qds_qixis.h"
43 DECLARE_GLOBAL_DATA_PTR;
45 static const int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
46 {8, 8}, {9, 9}, {14, 14}, {15, 15} };
48 static const int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
49 {10, 10}, {11, 11}, {12, 12}, {13, 13} };
51 static const int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4},
52 {10, 11}, {11, 10}, {12, 2}, {13, 3} };
54 static const int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6},
55 {8, 9}, {9, 8}, {14, 1}, {15, 0} };
60 struct cpu_type *cpu = gd->cpu;
61 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
64 printf("Board: %sQDS, ", cpu->name);
65 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
66 QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver));
68 sw = QIXIS_READ(brdcfg[0]);
69 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
72 printf("vBank: %d\n", sw);
78 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
80 /* Display the RCW, so that no one gets confused as to what RCW
81 * we're actually using for this boot.
83 puts("Reset Configuration Word (RCW):");
84 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
85 u32 rcw = in_be32(&gur->rcwsr[i]);
88 printf("\n %08x:", i * 4);
94 * Display the actual SERDES reference clocks as configured by the
95 * dip switches on the board. Note that the SWx registers could
96 * technically be set to force the reference clocks to match the
97 * values that the SERDES expects (or vice versa). For now, however,
98 * we just display both values and hope the user notices when they
101 puts("SERDES Reference Clocks: ");
102 sw = QIXIS_READ(brdcfg[2]);
103 for (i = 0; i < MAX_SERDES; i++) {
104 static const char *freq[] = {
105 "100", "125", "156.25", "161.1328125"};
106 unsigned int clock = (sw >> (2 * i)) & 3;
108 printf("SERDES%u=%sMHz ", i+1, freq[clock]);
115 int select_i2c_ch_pca9547(u8 ch)
119 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
121 puts("PCA: failed to select proper channel\n");
128 /* Configure Crossbar switches for Front-Side SerDes Ports */
129 int config_frontside_crossbar_vsc3316(void)
131 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
132 u32 srds_prtcl_s1, srds_prtcl_s2;
135 ret = select_i2c_ch_pca9547(I2C_MUX_CH_VSC3316_FS);
139 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
140 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
141 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
143 ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm1_tx, 8);
146 ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm1_rx, 8);
151 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
152 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
153 srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
155 ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm2_tx, 8);
158 ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm2_rx, 8);
166 int config_backside_crossbar_mux(void)
168 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
169 u32 srds_prtcl_s3, srds_prtcl_s4;
172 srds_prtcl_s3 = in_be32(&gur->rcwsr[4]) &
173 FSL_CORENET2_RCWSR4_SRDS3_PRTCL;
174 srds_prtcl_s3 >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT;
175 switch (srds_prtcl_s3) {
177 /* SerDes3 is not enabled */
182 /* SD3(0:7) => SLOT5(0:7) */
183 brdcfg = QIXIS_READ(brdcfg[12]);
184 brdcfg &= ~BRDCFG12_SD3MX_MASK;
185 brdcfg |= BRDCFG12_SD3MX_SLOT5;
186 QIXIS_WRITE(brdcfg[12], brdcfg);
197 /* SD3(4:7) => SLOT6(0:3) */
198 brdcfg = QIXIS_READ(brdcfg[12]);
199 brdcfg &= ~BRDCFG12_SD3MX_MASK;
200 brdcfg |= BRDCFG12_SD3MX_SLOT6;
201 QIXIS_WRITE(brdcfg[12], brdcfg);
204 printf("WARNING: unsupported for SerDes3 Protocol %d\n",
209 srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &
210 FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
211 srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
212 switch (srds_prtcl_s4) {
214 /* SerDes4 is not enabled */
217 /* 10b, SD4(0:7) => SLOT7(0:7) */
218 brdcfg = QIXIS_READ(brdcfg[12]);
219 brdcfg &= ~BRDCFG12_SD4MX_MASK;
220 brdcfg |= BRDCFG12_SD4MX_SLOT7;
221 QIXIS_WRITE(brdcfg[12], brdcfg);
226 /* x1b, SD4(4:7) => SLOT8(0:3) */
227 brdcfg = QIXIS_READ(brdcfg[12]);
228 brdcfg &= ~BRDCFG12_SD4MX_MASK;
229 brdcfg |= BRDCFG12_SD4MX_SLOT8;
230 QIXIS_WRITE(brdcfg[12], brdcfg);
237 /* 00b, SD4(4:5) => AURORA, SD4(6:7) => SATA */
238 brdcfg = QIXIS_READ(brdcfg[12]);
239 brdcfg &= ~BRDCFG12_SD4MX_MASK;
240 brdcfg |= BRDCFG12_SD4MX_AURO_SATA;
241 QIXIS_WRITE(brdcfg[12], brdcfg);
244 printf("WARNING: unsupported for SerDes4 Protocol %d\n",
252 int board_early_init_r(void)
254 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
255 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
258 * Remap Boot flash + PROMJET region to caching-inhibited
259 * so that flash can be erased properly.
262 /* Flush d-cache and invalidate i-cache of any FLASH data */
266 /* invalidate existing TLB entry for flash + promjet */
267 disable_tlb(flash_esel);
269 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
270 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
271 0, flash_esel, BOOKE_PAGESZ_256M, 1);
274 #ifdef CONFIG_SYS_DPAA_QBMAN
278 /* Disable remote I2C connectoin */
279 QIXIS_WRITE(brdcfg[5], BRDCFG5_RESET);
281 /* Configure board SERDES ports crossbar */
282 config_frontside_crossbar_vsc3316();
283 config_backside_crossbar_mux();
284 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
289 unsigned long get_board_sys_clk(void)
291 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
293 switch (sysclk_conf & 0x0F) {
294 case QIXIS_SYSCLK_83:
296 case QIXIS_SYSCLK_100:
298 case QIXIS_SYSCLK_125:
300 case QIXIS_SYSCLK_133:
302 case QIXIS_SYSCLK_150:
304 case QIXIS_SYSCLK_160:
306 case QIXIS_SYSCLK_166:
312 unsigned long get_board_ddr_clk(void)
314 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
316 switch ((ddrclk_conf & 0x30) >> 4) {
317 case QIXIS_DDRCLK_100:
319 case QIXIS_DDRCLK_125:
321 case QIXIS_DDRCLK_133:
327 static const char *serdes_clock_to_string(u32 clock)
330 case SRDS_PLLCR0_RFCK_SEL_100:
332 case SRDS_PLLCR0_RFCK_SEL_125:
334 case SRDS_PLLCR0_RFCK_SEL_156_25:
336 case SRDS_PLLCR0_RFCK_SEL_161_13:
337 return "161.1328125";
343 int misc_init_r(void)
346 serdes_corenet_t *srds_regs =
347 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
348 u32 actual[MAX_SERDES];
351 sw = QIXIS_READ(brdcfg[2]);
352 for (i = 0; i < MAX_SERDES; i++) {
353 unsigned int clock = (sw >> (2 * i)) & 3;
356 actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
359 actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
362 actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
365 actual[i] = SRDS_PLLCR0_RFCK_SEL_161_13;
370 for (i = 0; i < MAX_SERDES; i++) {
371 u32 pllcr0 = srds_regs->bank[i].pllcr0;
372 u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
373 if (expected != actual[i]) {
374 printf("Warning: SERDES%u expects reference clock"
375 " %sMHz, but actual is %sMHz\n", i + 1,
376 serdes_clock_to_string(expected),
377 serdes_clock_to_string(actual[i]));
384 void ft_board_setup(void *blob, bd_t *bd)
389 ft_cpu_setup(blob, bd);
391 base = getenv_bootm_low();
392 size = getenv_bootm_size();
394 fdt_fixup_memory(blob, (u64)base, (u64)size);
397 pci_of_setup(blob, bd);
400 fdt_fixup_liodn(blob);
401 fdt_fixup_dr_usb(blob, bd);
403 #ifdef CONFIG_SYS_DPAA_FMAN
404 fdt_fixup_fman_ethernet(blob);
405 fdt_fixup_board_enet(blob);
410 * Reverse engineering switch settings.
411 * Some bits cannot be figured out. They will be displayed as
412 * underscore in binary format. mask[] has those bits.
413 * Some bits are calculated differently than the actual switches
414 * if booting with overriding by FPGA.
416 void qixis_dump_switch(void)
422 * Any bit with 1 means that bit cannot be reverse engineered.
423 * It will be displayed as _ in binary format.
425 static const u8 mask[] = {0, 0, 0, 0, 0, 0x1, 0xdf, 0x3f, 0x1f};
427 u8 brdcfg[16], dutcfg[16];
429 for (i = 0; i < 16; i++) {
430 brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
431 dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
435 sw[1] = (dutcfg[1] << 0x07) | \
436 ((dutcfg[12] & 0xC0) >> 1) | \
437 ((dutcfg[11] & 0xE0) >> 3) | \
438 ((dutcfg[6] & 0x80) >> 6) | \
439 ((dutcfg[1] & 0x80) >> 7);
440 sw[2] = ((brdcfg[1] & 0x0f) << 4) | \
441 ((brdcfg[1] & 0x30) >> 2) | \
442 ((brdcfg[1] & 0x40) >> 5) | \
443 ((brdcfg[1] & 0x80) >> 7);
445 sw[4] = ((dutcfg[2] & 0x01) << 7) | \
446 ((dutcfg[2] & 0x06) << 4) | \
447 ((~QIXIS_READ(present)) & 0x10) | \
448 ((brdcfg[3] & 0x80) >> 4) | \
449 ((brdcfg[3] & 0x01) << 2) | \
450 ((brdcfg[6] == 0x62) ? 3 : \
451 ((brdcfg[6] == 0x5a) ? 2 : \
452 ((brdcfg[6] == 0x5e) ? 1 : 0)));
453 sw[5] = ((brdcfg[0] & 0x0f) << 4) | \
454 ((QIXIS_READ(rst_ctl) & 0x30) >> 2) | \
455 ((brdcfg[0] & 0x40) >> 5);
456 sw[6] = (brdcfg[11] & 0x20);
457 sw[7] = (((~QIXIS_READ(rst_ctl)) & 0x40) << 1) | \
458 ((brdcfg[5] & 0x10) << 2);
459 sw[8] = ((brdcfg[12] & 0x08) << 4) | \
460 ((brdcfg[12] & 0x03) << 5);
462 puts("DIP switch (reverse-engineering)\n");
463 for (i = 0; i < 9; i++) {
464 printf("SW%d = 0b%s (0x%02x)\n",
465 i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]);