2 * Copyright 2009-2012 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <linux/compiler.h>
29 #include <asm/processor.h>
30 #include <asm/cache.h>
31 #include <asm/immap_85xx.h>
32 #include <asm/fsl_law.h>
33 #include <asm/fsl_serdes.h>
34 #include <asm/fsl_portals.h>
35 #include <asm/fsl_liodn.h>
38 #include "../common/qixis.h"
39 #include "../common/vsc3316_3308.h"
41 #include "t4240qds_qixis.h"
43 DECLARE_GLOBAL_DATA_PTR;
45 static const int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
46 {8, 8}, {9, 9}, {14, 14}, {15, 15} };
48 static const int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
49 {10, 10}, {11, 11}, {12, 12}, {13, 13} };
51 static const int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4},
52 {10, 11}, {11, 10}, {12, 2}, {13, 3} };
54 static const int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6},
55 {8, 9}, {9, 8}, {14, 1}, {15, 0} };
61 struct cpu_type *cpu = gd->arch.cpu;
62 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
65 printf("Board: %sQDS, ", cpu->name);
66 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
67 QIXIS_READ(id), QIXIS_READ(arch));
69 sw = QIXIS_READ(brdcfg[0]);
70 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
73 printf("vBank: %d\n", sw);
79 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
81 printf("FPGA: v%d (%s), build %d",
82 (int)QIXIS_READ(scver), qixis_read_tag(buf),
83 (int)qixis_read_minor());
84 /* the timestamp string contains "\n" at the end */
85 printf(" on %s", qixis_read_time(buf));
87 /* Display the RCW, so that no one gets confused as to what RCW
88 * we're actually using for this boot.
90 puts("Reset Configuration Word (RCW):");
91 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
92 u32 rcw = in_be32(&gur->rcwsr[i]);
95 printf("\n %08x:", i * 4);
101 * Display the actual SERDES reference clocks as configured by the
102 * dip switches on the board. Note that the SWx registers could
103 * technically be set to force the reference clocks to match the
104 * values that the SERDES expects (or vice versa). For now, however,
105 * we just display both values and hope the user notices when they
108 puts("SERDES Reference Clocks: ");
109 sw = QIXIS_READ(brdcfg[2]);
110 for (i = 0; i < MAX_SERDES; i++) {
111 static const char *freq[] = {
112 "100", "125", "156.25", "161.1328125"};
113 unsigned int clock = (sw >> (6 - 2 * i)) & 3;
115 printf("SERDES%u=%sMHz ", i+1, freq[clock]);
122 int select_i2c_ch_pca9547(u8 ch)
126 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
128 puts("PCA: failed to select proper channel\n");
136 * read_voltage from sensor on I2C bus
137 * We use average of 4 readings, waiting for 532us befor another reading
139 #define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */
140 #define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */
142 static inline int read_voltage(void)
144 int i, ret, voltage_read = 0;
147 for (i = 0; i < NUM_READINGS; i++) {
148 ret = i2c_read(I2C_VOL_MONITOR_ADDR,
149 I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2);
151 printf("VID: failed to read core voltage\n");
154 if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) {
155 printf("VID: Core voltage sensor error\n");
158 debug("VID: bus voltage reads 0x%04x\n", vol_mon);
160 voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4;
161 udelay(WAIT_FOR_ADC);
163 /* calculate the average */
164 voltage_read /= NUM_READINGS;
170 * We need to calculate how long before the voltage starts to drop or increase
171 * It returns with the loop count. Each loop takes several readings (532us)
173 static inline int wait_for_voltage_change(int vdd_last)
175 int timeout, vdd_current;
177 vdd_current = read_voltage();
178 /* wait until voltage starts to drop */
179 for (timeout = 0; abs(vdd_last - vdd_current) <= 4 &&
180 timeout < 100; timeout++) {
181 vdd_current = read_voltage();
183 if (timeout >= 100) {
184 printf("VID: Voltage adjustment timeout\n");
191 * argument 'wait' is the time we know the voltage difference can be measured
192 * this function keeps reading the voltage until it is stable
194 static inline int wait_for_voltage_stable(int wait)
196 int timeout, vdd_current, vdd_last;
198 vdd_last = read_voltage();
199 udelay(wait * NUM_READINGS * WAIT_FOR_ADC);
200 /* wait until voltage is stable */
201 vdd_current = read_voltage();
202 for (timeout = 0; abs(vdd_last - vdd_current) >= 4 &&
203 timeout < 100; timeout++) {
204 vdd_last = vdd_current;
205 udelay(wait * NUM_READINGS * WAIT_FOR_ADC);
206 vdd_current = read_voltage();
208 if (timeout >= 100) {
209 printf("VID: Voltage adjustment timeout\n");
216 static inline int set_voltage(u8 vid)
220 vdd_last = read_voltage();
221 QIXIS_WRITE(brdcfg[6], vid);
222 wait = wait_for_voltage_change(vdd_last);
225 debug("VID: Waited %d us\n", wait * NUM_READINGS * WAIT_FOR_ADC);
226 wait = wait ? wait : 1;
228 vdd_last = wait_for_voltage_stable(wait);
231 debug("VID: Current voltage is %d mV\n", vdd_last);
237 static int adjust_vdd(ulong vdd_override)
239 int re_enable = disable_interrupts();
240 ccsr_gur_t __iomem *gur =
241 (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
244 int vdd_target, vdd_current, vdd_last;
246 unsigned long vdd_string_override;
248 static const uint16_t vdd[32] = {
281 ret = select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR);
283 debug("VID: I2c failed to switch channel\n");
288 /* get the voltage ID from fuse status register */
289 fusesr = in_be32(&gur->dcfg_fusesr);
290 vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
291 FSL_CORENET_DCFG_FUSESR_VID_MASK;
292 if (vid == FSL_CORENET_DCFG_FUSESR_VID_MASK) {
293 vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
294 FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
296 vdd_target = vdd[vid];
298 /* check override variable for overriding VDD */
299 vdd_string = getenv("t4240qds_vdd_mv");
300 if (vdd_override == 0 && vdd_string &&
301 !strict_strtoul(vdd_string, 10, &vdd_string_override))
302 vdd_override = vdd_string_override;
303 if (vdd_override >= 819 && vdd_override <= 1212) {
304 vdd_target = vdd_override * 10; /* convert to 1/10 mV */
305 debug("VDD override is %lu\n", vdd_override);
306 } else if (vdd_override != 0) {
307 printf("Invalid value.\n");
310 if (vdd_target == 0) {
311 debug("VID: VID not used\n");
315 /* round up and divice by 10 to get a value in mV */
316 vdd_target = DIV_ROUND_UP(vdd_target, 10);
317 debug("VID: vid = %d mV\n", vdd_target);
321 * Check current board VID setting
322 * Voltage regulator support output to 6.250mv step
323 * The highes voltage allowed for this board is (vid=0x40) 1.21250V
324 * the lowest is (vid=0x7f) 0.81875V
326 vid_current = QIXIS_READ(brdcfg[6]);
327 vdd_current = 121250 - (vid_current - 0x40) * 625;
328 debug("VID: Current vid setting is (0x%x) %d mV\n",
329 vid_current, vdd_current/100);
332 * Read voltage monitor to check real voltage.
333 * Voltage monitor LSB is 4mv.
335 vdd_last = read_voltage();
337 printf("VID: Could not read voltage sensor abort VID adjustment\n");
341 debug("VID: Core voltage is at %d mV\n", vdd_last);
343 * Adjust voltage to at or 8mV above target.
344 * Each step of adjustment is 6.25mV.
345 * Stepping down too fast may cause over current.
347 while (vdd_last > 0 && vid_current < 0x80 &&
348 vdd_last > (vdd_target + 8)) {
350 vdd_last = set_voltage(vid_current);
353 * Check if we need to step up
354 * This happens when board voltage switch was set too low
356 while (vdd_last > 0 && vid_current >= 0x40 &&
357 vdd_last < vdd_target + 2) {
359 vdd_last = set_voltage(vid_current);
362 printf("VID: Core voltage %d mV\n", vdd_last);
372 /* Configure Crossbar switches for Front-Side SerDes Ports */
373 int config_frontside_crossbar_vsc3316(void)
375 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
376 u32 srds_prtcl_s1, srds_prtcl_s2;
379 ret = select_i2c_ch_pca9547(I2C_MUX_CH_VSC3316_FS);
383 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
384 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
385 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
387 ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm1_tx, 8);
390 ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm1_rx, 8);
395 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
396 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
397 srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
399 ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm2_tx, 8);
402 ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm2_rx, 8);
410 int config_backside_crossbar_mux(void)
412 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
413 u32 srds_prtcl_s3, srds_prtcl_s4;
416 srds_prtcl_s3 = in_be32(&gur->rcwsr[4]) &
417 FSL_CORENET2_RCWSR4_SRDS3_PRTCL;
418 srds_prtcl_s3 >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT;
419 switch (srds_prtcl_s3) {
421 /* SerDes3 is not enabled */
426 /* SD3(0:7) => SLOT5(0:7) */
427 brdcfg = QIXIS_READ(brdcfg[12]);
428 brdcfg &= ~BRDCFG12_SD3MX_MASK;
429 brdcfg |= BRDCFG12_SD3MX_SLOT5;
430 QIXIS_WRITE(brdcfg[12], brdcfg);
441 /* SD3(4:7) => SLOT6(0:3) */
442 brdcfg = QIXIS_READ(brdcfg[12]);
443 brdcfg &= ~BRDCFG12_SD3MX_MASK;
444 brdcfg |= BRDCFG12_SD3MX_SLOT6;
445 QIXIS_WRITE(brdcfg[12], brdcfg);
448 printf("WARNING: unsupported for SerDes3 Protocol %d\n",
453 srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &
454 FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
455 srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
456 switch (srds_prtcl_s4) {
458 /* SerDes4 is not enabled */
461 /* 10b, SD4(0:7) => SLOT7(0:7) */
462 brdcfg = QIXIS_READ(brdcfg[12]);
463 brdcfg &= ~BRDCFG12_SD4MX_MASK;
464 brdcfg |= BRDCFG12_SD4MX_SLOT7;
465 QIXIS_WRITE(brdcfg[12], brdcfg);
470 /* x1b, SD4(4:7) => SLOT8(0:3) */
471 brdcfg = QIXIS_READ(brdcfg[12]);
472 brdcfg &= ~BRDCFG12_SD4MX_MASK;
473 brdcfg |= BRDCFG12_SD4MX_SLOT8;
474 QIXIS_WRITE(brdcfg[12], brdcfg);
481 /* 00b, SD4(4:5) => AURORA, SD4(6:7) => SATA */
482 brdcfg = QIXIS_READ(brdcfg[12]);
483 brdcfg &= ~BRDCFG12_SD4MX_MASK;
484 brdcfg |= BRDCFG12_SD4MX_AURO_SATA;
485 QIXIS_WRITE(brdcfg[12], brdcfg);
488 printf("WARNING: unsupported for SerDes4 Protocol %d\n",
496 int board_early_init_r(void)
498 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
499 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
502 * Remap Boot flash + PROMJET region to caching-inhibited
503 * so that flash can be erased properly.
506 /* Flush d-cache and invalidate i-cache of any FLASH data */
510 /* invalidate existing TLB entry for flash + promjet */
511 disable_tlb(flash_esel);
513 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
514 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
515 0, flash_esel, BOOKE_PAGESZ_256M, 1);
518 #ifdef CONFIG_SYS_DPAA_QBMAN
522 /* Disable remote I2C connection to qixis fpga */
523 QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
526 * Adjust core voltage according to voltage ID
527 * This function changes I2C mux to channel 2.
530 printf("Warning: Adjusting core voltage failed.\n");
532 /* Configure board SERDES ports crossbar */
533 config_frontside_crossbar_vsc3316();
534 config_backside_crossbar_mux();
535 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
540 unsigned long get_board_sys_clk(void)
542 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
543 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
544 /* use accurate clock measurement */
545 int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
546 int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
551 debug("SYS Clock measurement is: %d\n", val);
554 printf("Warning: SYS clock measurement is invalid, using value from brdcfg1.\n");
558 switch (sysclk_conf & 0x0F) {
559 case QIXIS_SYSCLK_83:
561 case QIXIS_SYSCLK_100:
563 case QIXIS_SYSCLK_125:
565 case QIXIS_SYSCLK_133:
567 case QIXIS_SYSCLK_150:
569 case QIXIS_SYSCLK_160:
571 case QIXIS_SYSCLK_166:
577 unsigned long get_board_ddr_clk(void)
579 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
580 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
581 /* use accurate clock measurement */
582 int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
583 int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
588 debug("DDR Clock measurement is: %d\n", val);
591 printf("Warning: DDR clock measurement is invalid, using value from brdcfg1.\n");
595 switch ((ddrclk_conf & 0x30) >> 4) {
596 case QIXIS_DDRCLK_100:
598 case QIXIS_DDRCLK_125:
600 case QIXIS_DDRCLK_133:
606 static const char *serdes_clock_to_string(u32 clock)
609 case SRDS_PLLCR0_RFCK_SEL_100:
611 case SRDS_PLLCR0_RFCK_SEL_125:
613 case SRDS_PLLCR0_RFCK_SEL_156_25:
615 case SRDS_PLLCR0_RFCK_SEL_161_13:
616 return "161.1328125";
622 int misc_init_r(void)
625 serdes_corenet_t *srds_regs =
626 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
627 u32 actual[MAX_SERDES];
630 sw = QIXIS_READ(brdcfg[2]);
631 for (i = 0; i < MAX_SERDES; i++) {
632 unsigned int clock = (sw >> (6 - 2 * i)) & 3;
635 actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
638 actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
641 actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
644 actual[i] = SRDS_PLLCR0_RFCK_SEL_161_13;
649 for (i = 0; i < MAX_SERDES; i++) {
650 u32 pllcr0 = srds_regs->bank[i].pllcr0;
651 u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
652 if (expected != actual[i]) {
653 printf("Warning: SERDES%u expects reference clock"
654 " %sMHz, but actual is %sMHz\n", i + 1,
655 serdes_clock_to_string(expected),
656 serdes_clock_to_string(actual[i]));
663 void ft_board_setup(void *blob, bd_t *bd)
668 ft_cpu_setup(blob, bd);
670 base = getenv_bootm_low();
671 size = getenv_bootm_size();
673 fdt_fixup_memory(blob, (u64)base, (u64)size);
676 pci_of_setup(blob, bd);
679 fdt_fixup_liodn(blob);
680 fdt_fixup_dr_usb(blob, bd);
682 #ifdef CONFIG_SYS_DPAA_FMAN
683 fdt_fixup_fman_ethernet(blob);
684 fdt_fixup_board_enet(blob);
689 * This function is called by bdinfo to print detail board information.
690 * As an exmaple for future board, we organize the messages into
691 * several sections. If applicable, the message is in the format of
693 * It should aligned with normal output of bdinfo command.
695 * Voltage: Core, DDR and another configurable voltages
696 * Clock : Critical clocks which are not printed already
697 * RCW : RCW source if not printed already
698 * Misc : Other important information not in above catagories
700 void board_detail(void)
703 u8 brdcfg[16], dutcfg[16], rst_ctl;
705 static const char * const clk[] = {"66.67", "100", "125", "133.33"};
707 for (i = 0; i < 16; i++) {
708 brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
709 dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
713 if (!select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR)) {
714 vdd = read_voltage();
716 printf("Core voltage= %d mV\n", vdd);
717 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
720 printf("XVDD = 1.%d V\n", ((brdcfg[8] & 0xf) - 4) * 5 + 25);
723 printf("SYSCLK = %s MHz\nDDRCLK = %s MHz\n",
724 clk[(brdcfg[11] >> 2) & 0x3], clk[brdcfg[11] & 3]);
727 rcwsrc = (dutcfg[0] << 1) + (dutcfg[1] & 1);
728 puts("RCW source = ");
736 puts("16-bit NOR\n");
742 puts("SPI 16-bit addressing\n");
745 puts("SPI 24-bit addressing\n");
748 puts("I2C normal addressing\n");
751 puts("I2C extended addressing\n");
757 puts("8-bit NAND, 2KB\n");
760 if ((rcwsrc >= 0x080) && (rcwsrc <= 0x09f))
761 puts("Hard-coded RCW\n");
762 else if ((rcwsrc >= 0x110) && (rcwsrc <= 0x11f))
763 puts("8-bit NAND, 4KB\n");
770 rst_ctl = QIXIS_READ(rst_ctl);
771 puts("HRESET_REQ = ");
772 switch (rst_ctl & 0x30) {
777 puts("Assert HRESET\n");
780 puts("Reset system\n");
789 * Reverse engineering switch settings.
790 * Some bits cannot be figured out. They will be displayed as
791 * underscore in binary format. mask[] has those bits.
792 * Some bits are calculated differently than the actual switches
793 * if booting with overriding by FPGA.
795 void qixis_dump_switch(void)
801 * Any bit with 1 means that bit cannot be reverse engineered.
802 * It will be displayed as _ in binary format.
804 static const u8 mask[] = {0, 0, 0, 0, 0, 0x1, 0xcf, 0x3f, 0x1f};
806 u8 brdcfg[16], dutcfg[16];
808 for (i = 0; i < 16; i++) {
809 brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
810 dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
814 sw[1] = (dutcfg[1] << 0x07) | \
815 ((dutcfg[12] & 0xC0) >> 1) | \
816 ((dutcfg[11] & 0xE0) >> 3) | \
817 ((dutcfg[6] & 0x80) >> 6) | \
818 ((dutcfg[1] & 0x80) >> 7);
819 sw[2] = ((brdcfg[1] & 0x0f) << 4) | \
820 ((brdcfg[1] & 0x30) >> 2) | \
821 ((brdcfg[1] & 0x40) >> 5) | \
822 ((brdcfg[1] & 0x80) >> 7);
824 sw[4] = ((dutcfg[2] & 0x01) << 7) | \
825 ((dutcfg[2] & 0x06) << 4) | \
826 ((~QIXIS_READ(present)) & 0x10) | \
827 ((brdcfg[3] & 0x80) >> 4) | \
828 ((brdcfg[3] & 0x01) << 2) | \
829 ((brdcfg[6] == 0x62) ? 3 : \
830 ((brdcfg[6] == 0x5a) ? 2 : \
831 ((brdcfg[6] == 0x5e) ? 1 : 0)));
832 sw[5] = ((brdcfg[0] & 0x0f) << 4) | \
833 ((QIXIS_READ(rst_ctl) & 0x30) >> 2) | \
834 ((brdcfg[0] & 0x40) >> 5);
835 sw[6] = (brdcfg[11] & 0x20) |
836 ((brdcfg[5] & 0x02) << 3);
837 sw[7] = (((~QIXIS_READ(rst_ctl)) & 0x40) << 1) | \
838 ((brdcfg[5] & 0x10) << 2);
839 sw[8] = ((brdcfg[12] & 0x08) << 4) | \
840 ((brdcfg[12] & 0x03) << 5);
842 puts("DIP switch (reverse-engineering)\n");
843 for (i = 0; i < 9; i++) {
844 printf("SW%d = 0b%s (0x%02x)\n",
845 i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]);
849 static int do_vdd_adjust(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
854 return CMD_RET_USAGE;
855 if (!strict_strtoul(argv[1], 10, &override))
856 adjust_vdd(override); /* the value is checked by callee */
858 return CMD_RET_USAGE;
864 vdd_override, 2, 0, do_vdd_adjust,
866 "- override with the voltage specified in mV, eg. 1050"