3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
28 #include <asm/ppc4xx-gpio.h>
29 #include <asm/global_data.h>
32 #include <gdsys_fpga.h>
34 #define REFLECTION_TESTPATTERN 0xdede
35 #define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
37 DECLARE_GLOBAL_DATA_PTR;
39 int get_fpga_state(unsigned dev)
41 return gd->arch.fpga_state[dev];
44 void print_fpga_state(unsigned dev)
46 if (gd->arch.fpga_state[dev] & FPGA_STATE_DONE_FAILED)
47 puts(" Waiting for FPGA-DONE timed out.\n");
48 if (gd->arch.fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
49 puts(" FPGA reflection test failed.\n");
52 int board_early_init_f(void)
56 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
57 gd->arch.fpga_state[k] = 0;
59 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
60 mtdcr(UIC0ER, 0x00000000); /* disable all ints */
61 mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */
62 mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
63 mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
64 mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest prio */
65 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
68 * EBC Configuration Register: set ready timeout to 512 ebc-clks
71 mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
75 int board_early_init_r(void)
80 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
81 gd->arch.fpga_state[k] = 0;
88 gd405ep_set_fpga_reset(1);
92 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
94 while (!gd405ep_get_fpga_done(k)) {
97 gd->arch.fpga_state[k] |=
98 FPGA_STATE_DONE_FAILED;
106 gd405ep_set_fpga_reset(0);
108 for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
109 struct ihs_fpga *fpga =
110 (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(k);
111 #ifdef CONFIG_SYS_FPGA_NO_RFL_HI
112 u16 *reflection_target = &fpga->reflection_low;
114 u16 *reflection_target = &fpga->reflection_high;
117 * wait for fpga out of reset
121 out_le16(&fpga->reflection_low,
122 REFLECTION_TESTPATTERN);
124 if (in_le16(reflection_target) ==
125 REFLECTION_TESTPATTERN_INV)
130 gd->arch.fpga_state[k] |=
131 FPGA_STATE_REFLECTION_FAILED;