3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #if defined(CONFIG_MPC5200_DDR)
32 #include "mt46v16m16-75.h"
34 #include "mt48lc16m16a2-75.h"
38 static void sdram_start (int hi_addr)
40 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
42 /* unlock mode register */
43 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
44 __asm__ volatile ("sync");
46 /* precharge all banks */
47 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
48 __asm__ volatile ("sync");
51 /* set mode register: extended mode */
52 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
53 __asm__ volatile ("sync");
55 /* set mode register: reset DLL */
56 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
57 __asm__ volatile ("sync");
60 /* precharge all banks */
61 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
62 __asm__ volatile ("sync");
65 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
66 __asm__ volatile ("sync");
68 /* set mode register */
69 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
70 __asm__ volatile ("sync");
72 /* normal operation */
73 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
74 __asm__ volatile ("sync");
79 * ATTENTION: Although partially referenced initdram does NOT make real use
80 * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
81 * is something else than 0x00000000.
84 #if defined(CONFIG_MPC5200)
85 long int initdram (int board_type)
92 /* setup SDRAM chip selects */
93 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
94 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
95 __asm__ volatile ("sync");
97 /* setup config registers */
98 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
99 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
100 __asm__ volatile ("sync");
104 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
105 __asm__ volatile ("sync");
108 /* find RAM size using SDRAM CS0 only */
110 test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
112 test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
120 /* memory smaller than 1MB is impossible */
121 if (dramsize < (1 << 20)) {
125 /* set SDRAM CS0 size according to the amount of RAM found */
127 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
129 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
133 /* let SDRAM CS1 start right after CS0 */
134 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
136 /* find RAM size using SDRAM CS1 only */
138 test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
140 test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
148 /* memory smaller than 1MB is impossible */
149 if (dramsize2 < (1 << 20)) {
153 /* set SDRAM CS1 size according to the amount of RAM found */
155 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
156 | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
158 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
161 #else /* CFG_RAMBOOT */
163 /* retrieve size of memory connected to SDRAM CS0 */
164 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
165 if (dramsize >= 0x13) {
166 dramsize = (1 << (dramsize - 0x13)) << 20;
171 /* retrieve size of memory connected to SDRAM CS1 */
172 dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
173 if (dramsize2 >= 0x13) {
174 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
179 #endif /* CFG_RAMBOOT */
181 return dramsize + dramsize2;
184 #elif defined(CONFIG_MGT5100)
186 long int initdram (int board_type)
192 /* setup and enable SDRAM chip selects */
193 *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
194 *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
195 *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
196 __asm__ volatile ("sync");
198 /* setup config registers */
199 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
200 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
202 /* address select register */
203 *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
204 __asm__ volatile ("sync");
208 test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
210 test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
218 /* set SDRAM end address according to size */
219 *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
221 #else /* CFG_RAMBOOT */
223 /* Retrieve amount of SDRAM available */
224 dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
226 #endif /* CFG_RAMBOOT */
232 #error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
235 int checkboard (void)
237 #if defined(CONFIG_MPC5200)
238 puts ("Board: Motorola MPC5200 (IceCube)\n");
239 #elif defined(CONFIG_MGT5100)
240 puts ("Board: Motorola MGT5100 (IceCube)\n");
245 void flash_preinit(void)
248 * Now, when we are in RAM, enable flash write
249 * access for detection process.
250 * Note that CS_BOOT cannot be cleared when
251 * executing in flash.
253 #if defined(CONFIG_MGT5100)
254 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
255 *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
257 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
260 void flash_afterinit(ulong size)
262 if (size == 0x800000) { /* adjust mapping */
263 *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
264 START_REG(CFG_BOOTCS_START | size);
265 *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
266 STOP_REG(CFG_BOOTCS_START | size, size);
271 static struct pci_controller hose;
273 extern void pci_mpc5xxx_init(struct pci_controller *);
275 void pci_init_board(void)
277 pci_mpc5xxx_init(&hose);
281 #if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
283 #define GPIO_PSC1_4 0x01000000UL
285 void init_ide_reset (void)
287 debug ("init_ide_reset\n");
289 /* Configure PSC1_4 as GPIO output for ATA reset */
290 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
291 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
294 void ide_set_reset (int idereset)
296 debug ("ide_reset(%d)\n", idereset);
299 *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
301 *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
304 #endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */