2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
9 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #if defined(CONFIG_DDR_MT46V16M16)
35 #include "mt46v16m16-75.h"
36 #elif defined(CONFIG_SDR_MT48LC16M16A2)
37 #include "mt48lc16m16a2-75.h"
38 #elif defined(CONFIG_DDR_MT46V32M16)
39 #include "mt46v32m16.h"
40 #elif defined(CONFIG_DDR_HYB25D512160BF)
41 #include "hyb25d512160bf.h"
42 #elif defined(CONFIG_DDR_K4H511638C)
43 #include "k4h511638c.h"
45 #error "INKA4x0 SDRAM: invalid chip type specified!"
48 #ifndef CONFIG_SYS_RAMBOOT
49 static void sdram_start (int hi_addr)
51 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
53 /* unlock mode register */
54 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
55 __asm__ volatile ("sync");
57 /* precharge all banks */
58 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
59 __asm__ volatile ("sync");
62 /* set mode register: extended mode */
63 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
64 __asm__ volatile ("sync");
66 /* set mode register: reset DLL */
67 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
68 __asm__ volatile ("sync");
71 /* precharge all banks */
72 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
73 __asm__ volatile ("sync");
76 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
77 __asm__ volatile ("sync");
79 /* set mode register */
80 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
81 __asm__ volatile ("sync");
83 /* normal operation */
84 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
85 __asm__ volatile ("sync");
90 * ATTENTION: Although partially referenced initdram does NOT make real use
91 * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
92 * is something else than 0x00000000.
95 phys_size_t initdram (int board_type)
98 #ifndef CONFIG_SYS_RAMBOOT
101 /* setup SDRAM chip selects */
102 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
103 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
104 __asm__ volatile ("sync");
106 /* setup config registers */
107 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
108 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
109 __asm__ volatile ("sync");
113 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
114 __asm__ volatile ("sync");
117 /* find RAM size using SDRAM CS0 only */
119 test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
121 test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
129 /* memory smaller than 1MB is impossible */
130 if (dramsize < (1 << 20)) {
134 /* set SDRAM CS0 size according to the amount of RAM found */
136 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
137 __builtin_ffs(dramsize >> 20) - 1;
139 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
142 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
143 #else /* CONFIG_SYS_RAMBOOT */
145 /* retrieve size of memory connected to SDRAM CS0 */
146 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
147 if (dramsize >= 0x13) {
148 dramsize = (1 << (dramsize - 0x13)) << 20;
152 #endif /* CONFIG_SYS_RAMBOOT */
157 int checkboard (void)
159 puts ("Board: INKA 4X0\n");
163 void flash_preinit(void)
166 * Now, when we are in RAM, enable flash write
167 * access for detection process.
168 * Note that CS_BOOT cannot be cleared when
169 * executing in flash.
171 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
174 int misc_init_f (void)
179 i = getenv_r("brightness", tmp, sizeof(tmp));
181 ? (int) simple_strtoul (tmp, NULL, 10)
182 : CONFIG_SYS_BRIGHTNESS;
186 /* Initialize GPIO output pins.
188 /* Configure GPT as GPIO output (and set them as they control low-active LEDs */
189 *(vu_long *)MPC5XXX_GPT0_ENABLE =
190 *(vu_long *)MPC5XXX_GPT1_ENABLE =
191 *(vu_long *)MPC5XXX_GPT2_ENABLE =
192 *(vu_long *)MPC5XXX_GPT3_ENABLE =
193 *(vu_long *)MPC5XXX_GPT4_ENABLE =
194 *(vu_long *)MPC5XXX_GPT5_ENABLE = 0x34;
196 /* Configure GPT7 as PWM timer, 1kHz, no ints. */
197 *(vu_long *)MPC5XXX_GPT7_ENABLE = 0;/* Disable */
198 *(vu_long *)MPC5XXX_GPT7_COUNTER = 0x020000fe;
199 *(vu_long *)MPC5XXX_GPT7_PWMCFG = (br << 16);
200 *(vu_long *)MPC5XXX_GPT7_ENABLE = 0x3;/* Enable PWM mode and start */
202 /* Configure PSC3_6,7 as GPIO output */
203 *(vu_long *)MPC5XXX_GPIO_ENABLE |= 0x00003000;
204 *(vu_long *)MPC5XXX_GPIO_DIR |= 0x00003000;
206 /* Configure PSC3_8 as GPIO output, no interrupt */
207 *(vu_long *)MPC5XXX_GPIO_SI_ENABLE |= 0x04000000;
208 *(vu_long *)MPC5XXX_GPIO_SI_DIR |= 0x04000000;
209 *(vu_long *)MPC5XXX_GPIO_SI_IEN &= ~0x04000000;
211 /* Configure PSC3_9 and GPIO_WKUP6,7 as GPIO output */
212 *(vu_long *)MPC5XXX_WU_GPIO_ENABLE |= 0xc4000000;
213 *(vu_long *)MPC5XXX_WU_GPIO_DIR |= 0xc4000000;
215 /* Set LR mirror bit because it is low-active */
216 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WKUP_7;
218 * Reset Coral-P graphics controller
220 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC3_9;
221 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC3_9;
222 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC3_9;
227 static struct pci_controller hose;
229 extern void pci_mpc5xxx_init(struct pci_controller *);
231 void pci_init_board(void)
233 pci_mpc5xxx_init(&hose);
237 #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
239 void init_ide_reset (void)
241 debug ("init_ide_reset\n");
243 /* Configure PSC1_4 as GPIO output for ATA reset */
244 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
245 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
247 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
250 void ide_set_reset (int idereset)
252 debug ("ide_reset(%d)\n", idereset);
255 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
256 /* Make a delay. MPC5200 spec says 25 usec min */
259 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;