board/isee/igep0033/board.c

   1 /*
   2  * Board functions for IGEP COM AQUILA/CYGNUS based boards
   3  *
   4  * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <errno.h>
  11 #include <spl.h>
  12 #include <asm/arch/cpu.h>
  13 #include <asm/arch/hardware.h>
  14 #include <asm/arch/omap.h>
  15 #include <asm/arch/ddr_defs.h>
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/gpio.h>
  18 #include <asm/arch/mmc_host_def.h>
  19 #include <asm/arch/sys_proto.h>
  20 #include <asm/io.h>
  21 #include <asm/emif.h>
  22 #include <asm/gpio.h>
  23 #include <i2c.h>
  24 #include <miiphy.h>
  25 #include <cpsw.h>
  26 #include "board.h"
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
  31
  32 /* MII mode defines */
  33 #define RMII_MODE_ENABLE        0x4D
  34
  35 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  36
  37 #ifdef CONFIG_SPL_BUILD
  38 static const struct ddr_data ddr3_data = {
  39         .datardsratio0 = K4B2G1646EBIH9_RD_DQS,
  40         .datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
  41         .datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE,
  42         .datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA,
  43         .datadldiff0 = PHY_DLL_LOCK_DIFF,
  44 };
  45
  46 static const struct cmd_control ddr3_cmd_ctrl_data = {
  47         .cmd0csratio = K4B2G1646EBIH9_RATIO,
  48         .cmd0dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
  49         .cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
  50
  51         .cmd1csratio = K4B2G1646EBIH9_RATIO,
  52         .cmd1dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
  53         .cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
  54
  55         .cmd2csratio = K4B2G1646EBIH9_RATIO,
  56         .cmd2dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
  57         .cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
  58 };
  59
  60 static struct emif_regs ddr3_emif_reg_data = {
  61         .sdram_config = K4B2G1646EBIH9_EMIF_SDCFG,
  62         .ref_ctrl = K4B2G1646EBIH9_EMIF_SDREF,
  63         .sdram_tim1 = K4B2G1646EBIH9_EMIF_TIM1,
  64         .sdram_tim2 = K4B2G1646EBIH9_EMIF_TIM2,
  65         .sdram_tim3 = K4B2G1646EBIH9_EMIF_TIM3,
  66         .zq_config = K4B2G1646EBIH9_ZQ_CFG,
  67         .emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY,
  68 };
  69
  70 #define OSC    (V_OSCK/1000000)
  71 const struct dpll_params dpll_ddr = {
  72                 303, OSC-1, 1, -1, -1, -1, -1};
  73
  74 const struct dpll_params *get_dpll_ddr_params(void)
  75 {
  76         return &dpll_ddr;
  77 }
  78
  79 #endif
  80
  81 /*
  82  * Early system init of muxing and clocks.
  83  */
  84 void s_init(void)
  85 {
  86         /*
  87          * Save the boot parameters passed from romcode.
  88          * We cannot delay the saving further than this,
  89          * to prevent overwrites.
  90          */
  91 #ifdef CONFIG_SPL_BUILD
  92         save_omap_boot_params();
  93 #endif
  94
  95         /* WDT1 is already running when the bootloader gets control
  96          * Disable it to avoid "random" resets
  97          */
  98         writel(0xAAAA, &wdtimer->wdtwspr);
  99         while (readl(&wdtimer->wdtwwps) != 0x0)
 100                 ;
 101         writel(0x5555, &wdtimer->wdtwspr);
 102         while (readl(&wdtimer->wdtwwps) != 0x0)
 103                 ;
 104
 105 #ifdef CONFIG_SPL_BUILD
 106         /* Setup the PLLs and the clocks for the peripherals */
 107         pll_init();
 108
 109         /* Enable RTC32K clock */
 110         rtc32k_enable();
 111
 112         enable_uart0_pin_mux();
 113
 114         uart_soft_reset();
 115         gd = &gdata;
 116
 117         preloader_console_init();
 118
 119         /* Configure board pin mux */
 120         enable_board_pin_mux();
 121
 122         config_ddr(303, K4B2G1646EBIH9_IOCTRL_VALUE, &ddr3_data,
 123                    &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
 124 #endif
 125 }
 126
 127 /*
 128  * Basic board specific setup.  Pinmux has been handled already.
 129  */
 130 int board_init(void)
 131 {
 132         gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
 133
 134         gpmc_init();
 135
 136         return 0;
 137 }
 138
 139 #if defined(CONFIG_DRIVER_TI_CPSW)
 140 static void cpsw_control(int enabled)
 141 {
 142         /* VTP can be added here */
 143
 144         return;
 145 }
 146
 147 static struct cpsw_slave_data cpsw_slaves[] = {
 148         {
 149                 .slave_reg_ofs  = 0x208,
 150                 .sliver_reg_ofs = 0xd80,
 151                 .phy_id         = 0,
 152                 .phy_if         = PHY_INTERFACE_MODE_RMII,
 153         },
 154 };
 155
 156 static struct cpsw_platform_data cpsw_data = {
 157         .mdio_base              = CPSW_MDIO_BASE,
 158         .cpsw_base              = CPSW_BASE,
 159         .mdio_div               = 0xff,
 160         .channels               = 8,
 161         .cpdma_reg_ofs          = 0x800,
 162         .slaves                 = 1,
 163         .slave_data             = cpsw_slaves,
 164         .ale_reg_ofs            = 0xd00,
 165         .ale_entries            = 1024,
 166         .host_port_reg_ofs      = 0x108,
 167         .hw_stats_reg_ofs       = 0x900,
 168         .mac_control            = (1 << 5),
 169         .control                = cpsw_control,
 170         .host_port_num          = 0,
 171         .version                = CPSW_CTRL_VERSION_2,
 172 };
 173
 174 int board_eth_init(bd_t *bis)
 175 {
 176         int rv, ret = 0;
 177         uint8_t mac_addr[6];
 178         uint32_t mac_hi, mac_lo;
 179
 180         if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
 181                 /* try reading mac address from efuse */
 182                 mac_lo = readl(&cdev->macid0l);
 183                 mac_hi = readl(&cdev->macid0h);
 184                 mac_addr[0] = mac_hi & 0xFF;
 185                 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 186                 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 187                 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 188                 mac_addr[4] = mac_lo & 0xFF;
 189                 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 190                 if (is_valid_ether_addr(mac_addr))
 191                         eth_setenv_enetaddr("ethaddr", mac_addr);
 192         }
 193
 194         writel(RMII_MODE_ENABLE, &cdev->miisel);
 195
 196         rv = cpsw_register(&cpsw_data);
 197         if (rv < 0)
 198                 printf("Error %d registering CPSW switch\n", rv);
 199         else
 200                 ret += rv;
 201
 202         return ret;
 203 }
 204 #endif
 205