2 * (C) Copyright 2000, 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * Ulrich Lutz, Speech Design GmbH, ulutz@datalab.de.
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #ifdef CONFIG_STATUS_LED
30 # include <status_led.h>
33 /* ------------------------------------------------------------------------- */
35 static long int dram_size (long int, long int *, long int);
37 /* ------------------------------------------------------------------------- */
39 #define _NOT_USED_ 0xFFFFFFFF
42 * 50 MHz SHARC access using UPM A
44 const uint sharc_table[] = {
46 * Single Read. (Offset 0 in UPM RAM)
48 0x0FF3FC04, 0x0FF3EC00, 0x7FFFEC04, 0xFFFFEC04,
49 0xFFFFEC05, /* last */
50 _NOT_USED_, _NOT_USED_, _NOT_USED_,
52 * Burst Read. (Offset 8 in UPM RAM)
55 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
56 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
57 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
58 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
60 * Single Write. (Offset 18 in UPM RAM)
62 0x0FAFFC04, 0x0FAFEC00, 0x7FFFEC04, 0xFFFFEC04,
63 0xFFFFEC05, /* last */
64 _NOT_USED_, _NOT_USED_, _NOT_USED_,
66 * Burst Write. (Offset 20 in UPM RAM)
69 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
70 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
71 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
72 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
74 * Refresh (Offset 30 in UPM RAM)
77 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
78 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
79 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
81 * Exception. (Offset 3c in UPM RAM)
83 0x7FFFFC07, /* last */
84 _NOT_USED_, _NOT_USED_, _NOT_USED_,
89 * 50 MHz SDRAM access using UPM B
91 const uint sdram_table[] = {
93 * Single Read. (Offset 0 in UPM RAM)
95 0x0E26FC04, 0x11ADFC04, 0xEFBBBC00, 0x1FF77C45, /* last */
98 * SDRAM Initialization (offset 5 in UPM RAM)
100 * This is no UPM entry point. The following definition uses
101 * the remaining space to establish an initialization
102 * sequence, which is executed by a RUN command.
105 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */
107 * Burst Read. (Offset 8 in UPM RAM)
109 0x0E26FC04, 0x10ADFC04, 0xF0AFFC00, 0xF0AFFC00,
110 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C45, /* last */
112 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
113 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
115 * Single Write. (Offset 18 in UPM RAM)
117 0x1F27FC04, 0xEEAEBC04, 0x01B93C00, 0x1FF77C45, /* last */
118 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
120 * Burst Write. (Offset 20 in UPM RAM)
122 0x0E26BC00, 0x10AD7C00, 0xF0AFFC00, 0xF0AFFC00,
123 0xE1BBBC04, 0x1FF77C45, /* last */
124 _NOT_USED_, _NOT_USED_,
125 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
126 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
128 * Refresh (Offset 30 in UPM RAM)
130 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC84,
131 0xFFFFFC05, /* last */
132 _NOT_USED_, _NOT_USED_, _NOT_USED_,
133 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
135 * Exception. (Offset 3c in UPM RAM)
137 0x7FFFFC07, /* last */
138 _NOT_USED_, _NOT_USED_, _NOT_USED_,
141 /* ------------------------------------------------------------------------- */
145 * Check Board Identity:
149 int checkboard (void)
152 puts ("Board: IVMS8\n");
155 puts ("Board: IVM-L8/24\n");
160 /* ------------------------------------------------------------------------- */
162 phys_size_t initdram (int board_type)
164 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
165 volatile memctl8xx_t *memctl = &immr->im_memctl;
168 /* enable SDRAM clock ("switch on" SDRAM) */
169 immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_SDRAM_CLKE); /* GPIO */
170 immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_SDRAM_CLKE); /* active output */
171 immr->im_cpm.cp_pbdir |= CONFIG_SYS_PB_SDRAM_CLKE; /* output */
172 immr->im_cpm.cp_pbdat |= CONFIG_SYS_PB_SDRAM_CLKE; /* assert SDRAM CLKE */
176 * Map controller bank 1 for ELIC SACCO
178 memctl->memc_or1 = CONFIG_SYS_OR1;
179 memctl->memc_br1 = CONFIG_SYS_BR1;
182 * Map controller bank 2 for ELIC EPIC
184 memctl->memc_or2 = CONFIG_SYS_OR2;
185 memctl->memc_br2 = CONFIG_SYS_BR2;
188 * Configure UPMA for SHARC
190 upmconfig (UPMA, (uint *) sharc_table,
191 sizeof (sharc_table) / sizeof (uint));
193 #if defined(CONFIG_IVML24)
195 * Map controller bank 4 for HDLC Address space
197 memctl->memc_or4 = CONFIG_SYS_OR4;
198 memctl->memc_br4 = CONFIG_SYS_BR4;
202 * Map controller bank 5 for SHARC
204 memctl->memc_or5 = CONFIG_SYS_OR5;
205 memctl->memc_br5 = CONFIG_SYS_BR5;
207 memctl->memc_mamr = 0x00001000;
210 * Configure UPMB for SDRAM
212 upmconfig (UPMB, (uint *) sdram_table,
213 sizeof (sdram_table) / sizeof (uint));
215 memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K;
217 memctl->memc_mar = 0x00000088;
220 * Map controller bank 3 to the SDRAM bank at preliminary address.
222 memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
223 memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
225 memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL; /* refresh not enabled yet */
228 memctl->memc_mcr = 0x80806105; /* precharge */
230 memctl->memc_mcr = 0x80806106; /* load mode register */
232 memctl->memc_mcr = 0x80806130; /* autorefresh */
234 memctl->memc_mcr = 0x80806130; /* autorefresh */
236 memctl->memc_mcr = 0x80806130; /* autorefresh */
238 memctl->memc_mcr = 0x80806130; /* autorefresh */
240 memctl->memc_mcr = 0x80806130; /* autorefresh */
242 memctl->memc_mcr = 0x80806130; /* autorefresh */
244 memctl->memc_mcr = 0x80806130; /* autorefresh */
246 memctl->memc_mcr = 0x80806130; /* autorefresh */
248 memctl->memc_mbmr |= MBMR_PTBE; /* refresh enabled */
251 * Check Bank 0 Memory Size for re-configuration
254 dram_size (CONFIG_SYS_MBMR_8COL, (long *) SDRAM_BASE3_PRELIM,
257 memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL | MBMR_PTBE;
262 /* ------------------------------------------------------------------------- */
265 * Check memory range for valid RAM. A simple memory test determines
266 * the actually available RAM size between addresses `base' and
267 * `base + maxsize'. Some (not all) hardware errors are detected:
268 * - short between address lines
269 * - short between data lines
272 static long int dram_size (long int mamr_value, long int *base,
275 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
276 volatile memctl8xx_t *memctl = &immr->im_memctl;
278 memctl->memc_mbmr = mamr_value;
280 return (get_ram_size (base, maxsize));
283 /* ------------------------------------------------------------------------- */
285 void reset_phy (void)
287 immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
289 /* De-assert Ethernet Powerdown */
290 immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_ETH_POWERDOWN); /* GPIO */
291 immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_ETH_POWERDOWN); /* active output */
292 immr->im_cpm.cp_pbdir |= CONFIG_SYS_PB_ETH_POWERDOWN; /* output */
293 immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_ETH_POWERDOWN); /* Enable PHY power */
297 * RESET is implemented by a positive pulse of at least 1 us
300 * Configure RESET pins for NS DP83843 PHY, and RESET chip.
302 * Note: The RESET pin is high active, but there is an
303 * inverter on the SPD823TS board...
305 immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_ETH_RESET);
306 immr->im_ioport.iop_pcdir |= CONFIG_SYS_PC_ETH_RESET;
307 /* assert RESET signal of PHY */
308 immr->im_ioport.iop_pcdat &= ~(CONFIG_SYS_PC_ETH_RESET);
310 /* de-assert RESET signal of PHY */
311 immr->im_ioport.iop_pcdat |= CONFIG_SYS_PC_ETH_RESET;
315 /* ------------------------------------------------------------------------- */
317 void show_boot_progress (int status)
319 #if defined(CONFIG_STATUS_LED)
320 # if defined(STATUS_LED_YELLOW)
321 status_led_set (STATUS_LED_YELLOW,
322 (status < 0) ? STATUS_LED_ON : STATUS_LED_OFF);
323 # endif /* STATUS_LED_YELLOW */
324 # if defined(STATUS_LED_BOOT)
326 status_led_set (STATUS_LED_BOOT, STATUS_LED_OFF);
327 # endif /* STATUS_LED_BOOT */
328 #endif /* CONFIG_STATUS_LED */
331 /* ------------------------------------------------------------------------- */
333 void ide_set_reset (int on)
335 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
338 * Configure PC for IDE Reset Pin
340 if (on) { /* assert RESET */
341 immr->im_ioport.iop_pcdat &= ~(CONFIG_SYS_PC_IDE_RESET);
342 } else { /* release RESET */
343 immr->im_ioport.iop_pcdat |= CONFIG_SYS_PC_IDE_RESET;
346 /* program port pin as GPIO output */
347 immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_IDE_RESET);
348 immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_IDE_RESET);
349 immr->im_ioport.iop_pcdir |= CONFIG_SYS_PC_IDE_RESET;
352 /* ------------------------------------------------------------------------- */