2 * board/karo/tx48/spl.c
3 * Copyright (C) 2012 Lothar Waßmann <LW@KARO-electronics.de>
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation version 2.
9 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
10 * kind, whether express or implied; without even the implied warranty
11 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
21 #include <fdt_support.h>
24 #include <linux/mtd/nand.h>
26 #include <asm/cache.h>
27 #include <asm/omap_common.h>
29 #include <asm/arch/cpu.h>
30 #include <asm/arch/hardware.h>
31 #include <asm/arch/mmc_host_def.h>
32 #include <asm/arch/sys_proto.h>
33 #include <asm/arch/nand.h>
34 #include <asm/arch/clock.h>
35 #include <asm/arch/common_def.h>
37 #include <asm/arch/da8xx-fb.h>
39 #define TX48_LED_GPIO AM33XX_GPIO_NR(1, 26)
40 #define TX48_ETH_PHY_RST_GPIO AM33XX_GPIO_NR(3, 8)
41 #define TX48_LCD_RST_GPIO AM33XX_GPIO_NR(1, 19)
42 #define TX48_LCD_PWR_GPIO AM33XX_GPIO_NR(1, 22)
43 #define TX48_LCD_BACKLIGHT_GPIO AM33XX_GPIO_NR(3, 14)
45 #define GMII_SEL (CTRL_BASE + 0x650)
48 #define UART_SYSCFG_OFFSET 0x54
49 #define UART_SYSSTS_OFFSET 0x58
51 #define UART_RESET (0x1 << 1)
52 #define UART_CLK_RUNNING_MASK 0x1
53 #define UART_SMART_IDLE_EN (0x1 << 0x3)
56 #define TSICR_REG 0x54
57 #define TIOCP_CFG_REG 0x10
60 /* RGMII mode define */
61 #define RGMII_MODE_ENABLE 0xA
62 #define RMII_MODE_ENABLE 0x5
63 #define MII_MODE_ENABLE 0x0
65 #define NO_OF_MAC_ADDR 1
68 #define MUX_CFG(value, offset) { \
69 __raw_writel(value, (CTRL_BASE + (offset))); \
72 /* PAD Control Fields */
73 #define SLEWCTRL (0x1 << 6)
74 #define RXACTIVE (0x1 << 5)
75 #define PULLUP_EN (0x1 << 4) /* Pull UP Selection */
76 #define PULLUDEN (0x0 << 3) /* Pull up enabled */
77 #define PULLUDDIS (0x1 << 3) /* Pull up disabled */
78 #define MODE(val) (val)
82 * Field names corresponds to the pad signal name
174 int ecap0_in_pwm0_out;
193 int xdma_event_intr0;
194 int xdma_event_intr1;
298 #define PAD_CTRL_BASE 0x800
299 #define OFFSET(x) (unsigned int) (&((struct pad_signals *) \
302 static struct pin_mux tx48_pins[] = {
303 #ifdef CONFIG_CMD_NAND
304 { OFFSET(gpmc_ad0), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD0 */
305 { OFFSET(gpmc_ad1), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD1 */
306 { OFFSET(gpmc_ad2), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD2 */
307 { OFFSET(gpmc_ad3), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD3 */
308 { OFFSET(gpmc_ad4), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD4 */
309 { OFFSET(gpmc_ad5), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD5 */
310 { OFFSET(gpmc_ad6), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD6 */
311 { OFFSET(gpmc_ad7), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD7 */
312 { OFFSET(gpmc_wait0), MODE(0) | RXACTIVE | PULLUP_EN, }, /* NAND WAIT */
313 { OFFSET(gpmc_wpn), MODE(7) | PULLUP_EN | RXACTIVE, }, /* NAND_WPN */
314 { OFFSET(gpmc_csn0), MODE(0) | PULLUDEN, }, /* NAND_CS0 */
315 { OFFSET(gpmc_advn_ale), MODE(0) | PULLUDEN, }, /* NAND_ADV_ALE */
316 { OFFSET(gpmc_oen_ren), MODE(0) | PULLUDEN, }, /* NAND_OE */
317 { OFFSET(gpmc_wen), MODE(0) | PULLUDEN, }, /* NAND_WEN */
318 { OFFSET(gpmc_be0n_cle), MODE(0) | PULLUDEN, }, /* NAND_BE_CLE */
321 { OFFSET(i2c0_sda), MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL, }, /* I2C_DATA */
322 { OFFSET(i2c0_scl), MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL, }, /* I2C_SCLK */
324 #ifndef CONFIG_NO_ETH
326 { OFFSET(mii1_crs), MODE(1) | RXACTIVE, }, /* RMII1_CRS */
327 { OFFSET(mii1_rxerr), MODE(1) | RXACTIVE | PULLUDEN, }, /* RMII1_RXERR */
328 { OFFSET(mii1_txen), MODE(1), }, /* RMII1_TXEN */
329 { OFFSET(mii1_txd1), MODE(1), }, /* RMII1_TXD1 */
330 { OFFSET(mii1_txd0), MODE(1), }, /* RMII1_TXD0 */
331 { OFFSET(mii1_rxd1), MODE(1) | RXACTIVE | PULLUP_EN, }, /* RMII1_RXD1 */
332 { OFFSET(mii1_rxd0), MODE(1) | RXACTIVE | PULLUP_EN, }, /* RMII1_RXD0 */
333 { OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN, }, /* MDIO_DATA */
334 { OFFSET(mdio_clk), MODE(0) | PULLUP_EN, }, /* MDIO_CLK */
335 { OFFSET(rmii1_refclk), MODE(0) | RXACTIVE, }, /* RMII1_REFCLK */
336 { OFFSET(emu0), MODE(7) | RXACTIVE}, /* nINT */
337 { OFFSET(emu1), MODE(7), }, /* nRST */
341 static struct gpio tx48_gpios[] = {
342 /* configure this pin early to prevent flicker of the LCD */
343 { TX48_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
346 static struct pin_mux tx48_mmc_pins[] = {
347 #ifdef CONFIG_OMAP_HSMMC
349 { OFFSET(mii1_rxd2), MODE(4) | RXACTIVE | PULLUP_EN, }, /* MMC1_DAT3 */
350 { OFFSET(mii1_rxd3), MODE(4) | RXACTIVE | PULLUP_EN, }, /* MMC1_DAT2 */
351 { OFFSET(mii1_rxclk), MODE(4) | RXACTIVE | PULLUP_EN, }, /* MMC1_DAT1 */
352 { OFFSET(mii1_txclk), MODE(4) | RXACTIVE | PULLUP_EN, }, /* MMC1_DAT0 */
353 { OFFSET(gpmc_csn1), MODE(2) | RXACTIVE | PULLUP_EN, }, /* MMC1_CLK */
354 { OFFSET(gpmc_csn2), MODE(2) | RXACTIVE | PULLUP_EN, }, /* MMC1_CMD */
355 { OFFSET(mcasp0_fsx), MODE(4) | RXACTIVE, }, /* MMC1_CD */
360 * Configure the pin mux for the module
362 static inline void tx48_set_pin_mux(const struct pin_mux *pin_mux,
367 for (i = 0; i < num_pins; i++)
368 MUX_CFG(pin_mux[i].val, pin_mux[i].reg_offset);
371 #ifdef CONFIG_SPL_BOARD_INIT
372 void spl_board_init(void)
374 gpio_request_array(tx48_gpios, ARRAY_SIZE(tx48_gpios));
375 tx48_set_pin_mux(tx48_pins, ARRAY_SIZE(tx48_pins));
378 #endif /* CONFIG_SPL_BOARD_INIT */
380 static struct pin_mux tx48_uart0_pins[] = {
381 #ifdef CONFIG_SYS_NS16550_COM1
382 /* UART0 for early boot messages */
383 { OFFSET(uart0_rxd), MODE(0) | PULLUP_EN | RXACTIVE, }, /* UART0_RXD */
384 { OFFSET(uart0_txd), MODE(0) | PULLUDEN, }, /* UART0_TXD */
385 { OFFSET(uart0_ctsn), MODE(0) | PULLUP_EN | RXACTIVE, },/* UART0_CTS */
386 { OFFSET(uart0_rtsn), MODE(0) | PULLUDEN, }, /* UART0_RTS */
388 #ifdef CONFIG_SYS_NS16550_COM2
390 { OFFSET(uart1_rxd), MODE(0) | PULLUP_EN | RXACTIVE, }, /* UART1_RXD */
391 { OFFSET(uart1_txd), MODE(0) | PULLUDEN, }, /* UART1_TXD */
392 { OFFSET(uart1_ctsn), MODE(0) | PULLUP_EN | RXACTIVE, },/* UART1_CTS */
393 { OFFSET(uart1_rtsn), MODE(0) | PULLUDEN, }, /* UART1_RTS */
395 #ifdef CONFIG_SYS_NS16550_COM3
397 { OFFSET(mii1_rxdv), MODE(3) | PULLUP_EN | RXACTIVE, }, /* UART5_RXD */
398 { OFFSET(mii1_col), MODE(3) | PULLUDEN, }, /* UART5_TXD */
399 { OFFSET(mmc0_dat1), MODE(2) | PULLUP_EN | RXACTIVE, }, /* UART5_CTS */
400 { OFFSET(mmc0_dat0), MODE(2) | PULLUDEN, }, /* UART5_RTS */
405 * early system init of muxing and clocks.
407 void enable_uart0_pin_mux(void)
409 tx48_set_pin_mux(tx48_uart0_pins, ARRAY_SIZE(tx48_uart0_pins));
412 void enable_mmc0_pin_mux(void)
414 tx48_set_pin_mux(tx48_mmc_pins, ARRAY_SIZE(tx48_mmc_pins));