2 * Copyright (C) 2012-2013 Lothar Waßmann <LW@KARO-electronics.de>
5 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
24 #include <fdt_support.h>
27 #include <linux/mtd/nand.h>
30 #include <asm/cache.h>
31 #include <asm/omap_common.h>
33 #include <asm/arch/cpu.h>
34 #include <asm/arch/hardware.h>
35 #include <asm/arch/mmc_host_def.h>
36 #include <asm/arch/sys_proto.h>
37 #include <asm/arch/clock.h>
39 #include <asm/arch/da8xx-fb.h>
41 #include "../common/karo.h"
43 DECLARE_GLOBAL_DATA_PTR;
45 #define TX48_LED_GPIO AM33XX_GPIO_NR(1, 26)
46 #define TX48_ETH_PHY_RST_GPIO AM33XX_GPIO_NR(3, 8)
47 #define TX48_LCD_RST_GPIO AM33XX_GPIO_NR(1, 19)
48 #define TX48_LCD_PWR_GPIO AM33XX_GPIO_NR(1, 22)
49 #define TX48_LCD_BACKLIGHT_GPIO AM33XX_GPIO_NR(3, 14)
50 #define TX48_MMC_CD_GPIO AM33XX_GPIO_NR(3, 15)
52 #define GMII_SEL (CTRL_BASE + 0x650)
55 #define UART_SYSCFG_OFFSET 0x54
56 #define UART_SYSSTS_OFFSET 0x58
58 #define UART_RESET (0x1 << 1)
59 #define UART_CLK_RUNNING_MASK 0x1
60 #define UART_SMART_IDLE_EN (0x1 << 0x3)
63 #define TSICR_REG 0x54
64 #define TIOCP_CFG_REG 0x10
67 /* RGMII mode define */
68 #define RGMII_MODE_ENABLE 0xA
69 #define RMII_MODE_ENABLE 0x5
70 #define MII_MODE_ENABLE 0x0
72 #define NO_OF_MAC_ADDR 1
75 /* PAD Control Fields */
76 #define SLEWCTRL (0x1 << 6)
77 #define RXACTIVE (0x1 << 5)
78 #define PULLUP_EN (0x1 << 4) /* Pull UP Selection */
79 #define PULLUDEN (0x0 << 3) /* Pull up enabled */
80 #define PULLUDDIS (0x1 << 3) /* Pull up disabled */
81 #define MODE(val) (val)
85 * Field names corresponds to the pad signal name
177 int ecap0_in_pwm0_out;
196 int xdma_event_intr0;
197 int xdma_event_intr1;
301 #define PAD_CTRL_BASE 0x800
302 #define OFFSET(x) (unsigned int) (&((struct pad_signals *) \
306 * Configure the pin mux for the module
308 static inline void tx48_set_pin_mux(const struct pin_mux *pin_mux,
313 for (i = 0; i < num_pins; i++)
314 writel(pin_mux[i].val, CTRL_BASE + pin_mux[i].reg_offset);
317 #define PRM_RSTST_GLOBAL_COLD_RST (1 << 0)
318 #define PRM_RSTST_GLOBAL_WARM_SW_RST (1 << 1)
319 #define PRM_RSTST_WDT1_RST (1 << 4)
320 #define PRM_RSTST_EXTERNAL_WARM_RST (1 << 5)
321 #define PRM_RSTST_ICEPICK_RST (1 << 9)
323 static u32 prm_rstst __attribute__((section(".data")));
326 * Basic board specific setup
328 static const struct pin_mux tx48_pads[] = {
329 { OFFSET(i2c0_sda), MODE(7) | RXACTIVE | PULLUDEN | PULLUP_EN, },
330 { OFFSET(i2c0_scl), MODE(7) | RXACTIVE | PULLUDEN | PULLUP_EN, },
331 { OFFSET(emu1), MODE(7), }, /* ETH PHY Reset */
334 static const struct pin_mux tx48_i2c_pads[] = {
335 { OFFSET(i2c0_sda), MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN, },
336 { OFFSET(i2c0_scl), MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN, },
339 static const struct gpio tx48_gpios[] = {
340 { AM33XX_GPIO_NR(3, 5), GPIOF_INPUT, "I2C1_SDA", },
341 { AM33XX_GPIO_NR(3, 6), GPIOF_INPUT, "I2C1_SCL", },
342 { AM33XX_GPIO_NR(3, 8), GPIOF_OUTPUT_INIT_LOW, "ETH_PHY_RESET", },
345 static const struct pin_mux stk5_pads[] = {
347 { OFFSET(gpmc_a10), MODE(7) | PULLUDEN, },
349 { OFFSET(gpmc_a3), MODE(7) | PULLUDEN, },
350 /* LCD POWER_ENABLE */
351 { OFFSET(gpmc_a6), MODE(7) | PULLUDEN, },
352 /* LCD Backlight (PWM) */
353 { OFFSET(mcasp0_aclkx), MODE(7) | PULLUDEN, },
355 { OFFSET(mcasp0_fsx), MODE(7) | PULLUDEN | PULLUP_EN, },
358 static const struct gpio stk5_gpios[] = {
359 { TX48_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
360 { TX48_MMC_CD_GPIO, GPIOF_INPUT, "MMC0 CD", },
363 static const struct pin_mux stk5_lcd_pads[] = {
365 { OFFSET(lcd_data0), MODE(0) | PULLUDEN, },
366 { OFFSET(lcd_data1), MODE(0) | PULLUDEN, },
367 { OFFSET(lcd_data2), MODE(0) | PULLUDEN, },
368 { OFFSET(lcd_data3), MODE(0) | PULLUDEN, },
369 { OFFSET(lcd_data4), MODE(0) | PULLUDEN, },
370 { OFFSET(lcd_data5), MODE(0) | PULLUDEN, },
371 { OFFSET(lcd_data6), MODE(0) | PULLUDEN, },
372 { OFFSET(lcd_data7), MODE(0) | PULLUDEN, },
373 { OFFSET(lcd_data8), MODE(0) | PULLUDEN, },
374 { OFFSET(lcd_data9), MODE(0) | PULLUDEN, },
375 { OFFSET(lcd_data10), MODE(0) | PULLUDEN, },
376 { OFFSET(lcd_data11), MODE(0) | PULLUDEN, },
377 { OFFSET(lcd_data12), MODE(0) | PULLUDEN, },
378 { OFFSET(lcd_data13), MODE(0) | PULLUDEN, },
379 { OFFSET(lcd_data14), MODE(0) | PULLUDEN, },
380 { OFFSET(lcd_data15), MODE(0) | PULLUDEN, },
381 /* LCD control signals */
382 { OFFSET(lcd_hsync), MODE(0) | PULLUDEN, },
383 { OFFSET(lcd_vsync), MODE(0) | PULLUDEN, },
384 { OFFSET(lcd_pclk), MODE(0) | PULLUDEN, },
385 { OFFSET(lcd_ac_bias_en), MODE(0) | PULLUDEN, },
388 static const struct gpio stk5_lcd_gpios[] = {
389 { AM33XX_GPIO_NR(1, 19), GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
390 { AM33XX_GPIO_NR(1, 22), GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
391 { AM33XX_GPIO_NR(3, 14), GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
394 static const struct pin_mux stk5v5_pads[] = {
395 /* CAN transceiver control */
396 { OFFSET(gpmc_ad8), MODE(7) | PULLUDEN, },
399 static const struct gpio stk5v5_gpios[] = {
400 { AM33XX_GPIO_NR(0, 22), GPIOF_OUTPUT_INIT_HIGH, "CAN XCVR", },
404 static u16 tx48_cmap[256];
405 vidinfo_t panel_info = {
406 /* set to max. size supported by SoC */
410 .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
414 #define FB_SYNC_OE_LOW_ACT (1 << 31)
415 #define FB_SYNC_CLK_LAT_FALL (1 << 30)
417 static struct fb_videomode tx48_fb_modes[] = {
419 /* Standard VGA timing */
424 .pixclock = KHZ2PICOS(25175),
431 .sync = FB_SYNC_CLK_LAT_FALL,
434 /* Emerging ETV570 640 x 480 display. Syncs low active,
435 * DE high active, 115.2 mm x 86.4 mm display area
436 * VGA compatible timing
442 .pixclock = KHZ2PICOS(25175),
449 .sync = FB_SYNC_CLK_LAT_FALL,
452 /* Emerging ET0350G0DH6 320 x 240 display.
453 * 70.08 mm x 52.56 mm display area.
459 .pixclock = KHZ2PICOS(6500),
460 .left_margin = 68 - 34,
463 .upper_margin = 18 - 3,
466 .sync = FB_SYNC_CLK_LAT_FALL,
469 /* Emerging ET0430G0DH6 480 x 272 display.
470 * 95.04 mm x 53.856 mm display area.
476 .pixclock = KHZ2PICOS(9000),
485 /* Emerging ET0500G0DH6 800 x 480 display.
486 * 109.6 mm x 66.4 mm display area.
492 .pixclock = KHZ2PICOS(33260),
493 .left_margin = 216 - 128,
495 .right_margin = 1056 - 800 - 216,
496 .upper_margin = 35 - 2,
498 .lower_margin = 525 - 480 - 35,
499 .sync = FB_SYNC_CLK_LAT_FALL,
502 /* Emerging ETQ570G0DH6 320 x 240 display.
503 * 115.2 mm x 86.4 mm display area.
509 .pixclock = KHZ2PICOS(6400),
513 .upper_margin = 16, /* 15 according to datasheet */
514 .vsync_len = 3, /* TVP -> 1>x>5 */
515 .lower_margin = 4, /* 4.5 according to datasheet */
516 .sync = FB_SYNC_CLK_LAT_FALL,
519 /* Emerging ET0700G0DH6 800 x 480 display.
520 * 152.4 mm x 91.44 mm display area.
526 .pixclock = KHZ2PICOS(33260),
527 .left_margin = 216 - 128,
529 .right_margin = 1056 - 800 - 216,
530 .upper_margin = 35 - 2,
532 .lower_margin = 525 - 480 - 35,
533 .sync = FB_SYNC_CLK_LAT_FALL,
536 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
544 .sync = FB_SYNC_CLK_LAT_FALL,
548 void *lcd_base; /* Start of framebuffer memory */
549 void *lcd_console_address; /* Start of console buffer */
557 static int lcd_enabled = 1;
558 static int lcd_bl_polarity;
560 static int lcd_backlight_polarity(void)
562 return lcd_bl_polarity;
565 void lcd_initcolregs(void)
569 void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
573 void lcd_enable(void)
576 * global variable from common/lcd.c
577 * Set to 0 here to prevent messages from going to LCD
578 * rather than serial console
583 karo_load_splashimage(1);
585 debug("Switching LCD on\n");
586 gpio_set_value(TX48_LCD_PWR_GPIO, 1);
588 gpio_set_value(TX48_LCD_RST_GPIO, 1);
590 gpio_set_value(TX48_LCD_BACKLIGHT_GPIO,
591 lcd_backlight_polarity());
595 void lcd_disable(void)
598 printf("Disabling LCD\n");
604 static void tx48_lcd_panel_setup(struct da8xx_panel *p,
605 struct fb_videomode *fb)
607 p->pxl_clk = PICOS2KHZ(fb->pixclock) * 1000;
610 p->hbp = fb->left_margin;
611 p->hsw = fb->hsync_len;
612 p->hfp = fb->right_margin;
614 p->height = fb->yres;
615 p->vbp = fb->upper_margin;
616 p->vsw = fb->vsync_len;
617 p->vfp = fb->lower_margin;
619 p->invert_pxl_clk = !!(fb->sync & FB_SYNC_CLK_LAT_FALL);
622 void lcd_panel_disable(void)
625 debug("Switching LCD off\n");
626 gpio_set_value(TX48_LCD_BACKLIGHT_GPIO,
627 !lcd_backlight_polarity());
628 gpio_set_value(TX48_LCD_PWR_GPIO, 0);
629 gpio_set_value(TX48_LCD_RST_GPIO, 0);
633 void lcd_ctrl_init(void *lcdbase)
635 int color_depth = 24;
636 const char *video_mode = karo_get_vmode(getenv("video_mode"));
640 struct fb_videomode *p = &tx48_fb_modes[0];
641 struct fb_videomode fb_mode;
642 int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
645 debug("LCD disabled\n");
649 if (had_ctrlc() || (prm_rstst & PRM_RSTST_WDT1_RST)) {
650 debug("Disabling LCD\n");
652 setenv("splashimage", NULL);
658 if (video_mode == NULL) {
659 debug("Disabling LCD\n");
664 lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
666 if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
668 debug("Using video mode from FDT\n");
670 if (fb_mode.xres > panel_info.vl_col ||
671 fb_mode.yres > panel_info.vl_row) {
672 printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
673 fb_mode.xres, fb_mode.yres,
674 panel_info.vl_col, panel_info.vl_row);
680 debug("Trying compiled-in video modes\n");
681 while (p->name != NULL) {
682 if (strcmp(p->name, vm) == 0) {
683 debug("Using video mode: '%s'\n", p->name);
690 debug("Trying to decode video_mode: '%s'\n", vm);
691 while (*vm != '\0') {
692 if (*vm >= '0' && *vm <= '9') {
695 val = simple_strtoul(vm, &end, 0);
698 if (val > panel_info.vl_col)
699 val = panel_info.vl_col;
701 panel_info.vl_col = val;
703 } else if (!yres_set) {
704 if (val > panel_info.vl_row)
705 val = panel_info.vl_row;
707 panel_info.vl_row = val;
709 } else if (!bpp_set) {
718 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
719 end - vm, vm, color_depth);
722 } else if (!refresh_set) {
749 if (p->xres == 0 || p->yres == 0) {
750 printf("Invalid video mode: %s\n", getenv("video_mode"));
752 printf("Supported video modes are:");
753 for (p = &tx48_fb_modes[0]; p->name != NULL; p++) {
754 printf(" %s", p->name);
759 if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
760 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
761 p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
765 panel_info.vl_col = p->xres;
766 panel_info.vl_row = p->yres;
768 switch (color_depth) {
770 panel_info.vl_bpix = LCD_COLOR8;
773 panel_info.vl_bpix = LCD_COLOR16;
776 panel_info.vl_bpix = LCD_COLOR24;
779 p->pixclock = KHZ2PICOS(refresh *
780 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
781 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len)
783 debug("Pixel clock set to %lu.%03lu MHz\n",
784 PICOS2KHZ(p->pixclock) / 1000,
785 PICOS2KHZ(p->pixclock) % 1000);
790 debug("Creating new display-timing node from '%s'\n",
792 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
794 printf("Failed to create new display-timing node from '%s': %d\n",
798 gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
799 tx48_set_pin_mux(stk5_lcd_pads, ARRAY_SIZE(stk5_lcd_pads));
801 if (karo_load_splashimage(0) == 0) {
802 struct da8xx_panel da8xx_panel = { };
804 debug("Initializing FB driver\n");
805 tx48_lcd_panel_setup(&da8xx_panel, p);
806 da8xx_video_init(&da8xx_panel, color_depth);
808 debug("Initializing LCD controller\n");
811 debug("Skipping initialization of LCD controller\n");
815 #define lcd_enabled 0
816 #endif /* CONFIG_LCD */
818 static void stk5_board_init(void)
820 gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
821 tx48_set_pin_mux(stk5_pads, ARRAY_SIZE(stk5_pads));
824 static void stk5v3_board_init(void)
829 static void stk5v5_board_init(void)
833 gpio_request_array(stk5v5_gpios, ARRAY_SIZE(stk5v5_gpios));
834 tx48_set_pin_mux(stk5v5_pads, ARRAY_SIZE(stk5v5_pads));
837 /* called with default environment! */
842 /* mach type passed to kernel */
843 #ifdef CONFIG_OF_LIBFDT
844 gd->bd->bi_arch_number = -1;
846 /* address of boot parameters */
847 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
849 if (ctrlc() || (prm_rstst & PRM_RSTST_WDT1_RST)) {
850 if (prm_rstst & PRM_RSTST_WDT1_RST)
851 printf("WDOG RESET detected\n");
853 printf("<CTRL-C> detected; safeboot enabled\n");
856 gpio_request_array(tx48_gpios, ARRAY_SIZE(tx48_gpios));
857 tx48_set_pin_mux(tx48_pads, ARRAY_SIZE(tx48_pads));
859 for (i = 0; i < ARRAY_SIZE(tx48_gpios); i++) {
860 int gpio = tx48_gpios[i].gpio;
862 if (gpio_get_value(gpio) == 0)
863 gpio_direction_output(gpio, 1);
866 tx48_set_pin_mux(tx48_pads, ARRAY_SIZE(tx48_i2c_pads));
870 static void show_reset_cause(u32 prm_rstst)
872 const char *dlm = "";
874 printf("RESET cause: ");
875 if (prm_rstst & PRM_RSTST_GLOBAL_COLD_RST) {
876 printf("%sPOR", dlm);
879 if (prm_rstst & PRM_RSTST_GLOBAL_WARM_SW_RST) {
883 if (prm_rstst & PRM_RSTST_WDT1_RST) {
884 printf("%sWATCHDOG", dlm);
887 if (prm_rstst & PRM_RSTST_EXTERNAL_WARM_RST) {
888 printf("%sWARM", dlm);
891 if (prm_rstst & PRM_RSTST_ICEPICK_RST) {
892 printf("%sJTAG", dlm);
901 /* called with default environment! */
904 prm_rstst = readl(PRM_RSTST);
905 show_reset_cause(prm_rstst);
907 printf("Board: Ka-Ro TX48-7020\n");
913 static void tx48_set_cpu_clock(void)
915 unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
916 unsigned long act_cpu_clk;
918 if (cpu_clk == 0 || cpu_clk == mpu_clk_rate() / 1000000)
921 if (had_ctrlc() || (prm_rstst & PRM_RSTST_WDT1_RST)) {
922 printf("%s detected; skipping cpu clock change\n",
923 (prm_rstst & PRM_RSTST_WDT1_RST) ?
924 "WDOG RESET" : "<CTRL-C>");
928 mpu_pll_config_val(cpu_clk);
930 act_cpu_clk = mpu_clk_rate();
931 if (cpu_clk * 1000000 != act_cpu_clk) {
932 printf("Failed to set CPU clock to %lu MHz; using %lu.%03lu MHz instead\n",
933 cpu_clk, act_cpu_clk / 1000000,
934 act_cpu_clk / 1000 % 1000);
936 printf("CPU clock set to %lu.%03lu MHz\n",
937 act_cpu_clk / 1000000, act_cpu_clk / 1000 % 1000);
941 static void tx48_init_mac(void)
943 uint8_t mac_addr[ETH_ALEN];
944 uint32_t mac_hi, mac_lo;
946 /* try reading mac address from efuse */
947 mac_lo = __raw_readl(MAC_ID0_LO);
948 mac_hi = __raw_readl(MAC_ID0_HI);
950 mac_addr[0] = mac_hi & 0xFF;
951 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
952 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
953 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
954 mac_addr[4] = mac_lo & 0xFF;
955 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
957 if (!is_valid_ether_addr(mac_addr)) {
958 printf("No valid MAC address programmed\n");
961 printf("MAC addr from fuse: %pM\n", mac_addr);
962 eth_setenv_enetaddr("ethaddr", mac_addr);
965 /* called with environment from NAND or MMC */
966 int board_late_init(void)
969 const char *baseboard;
973 tx48_set_cpu_clock();
976 setenv_ulong("safeboot", 1);
977 else if (prm_rstst & PRM_RSTST_WDT1_RST)
978 setenv_ulong("wdreset", 1);
982 baseboard = getenv("baseboard");
986 if (strncmp(baseboard, "stk5", 4) == 0) {
987 printf("Baseboard: %s\n", baseboard);
988 if ((strlen(baseboard) == 4) ||
989 strcmp(baseboard, "stk5-v3") == 0) {
991 } else if (strcmp(baseboard, "stk5-v5") == 0) {
994 printf("WARNING: Unsupported STK5 board rev.: %s\n",
998 printf("WARNING: Unsupported baseboard: '%s'\n",
1009 #ifdef CONFIG_DRIVER_TI_CPSW
1010 static void tx48_phy_init(void)
1012 debug("%s: Resetting ethernet PHY\n", __func__);
1014 gpio_direction_output(TX48_ETH_PHY_RST_GPIO, 0);
1019 gpio_set_value(TX48_ETH_PHY_RST_GPIO, 1);
1021 /* Wait for PHY internal POR signal to deassert */
1025 static void cpsw_control(int enabled)
1027 /* nothing for now */
1028 /* TODO : VTP was here before */
1031 static struct cpsw_slave_data cpsw_slaves[] = {
1033 .slave_reg_ofs = 0x208,
1034 .sliver_reg_ofs = 0xd80,
1036 .phy_if = PHY_INTERFACE_MODE_RMII,
1042 /* Nothing to be done here */
1045 static struct cpsw_platform_data cpsw_data = {
1046 .mdio_base = CPSW_MDIO_BASE,
1047 .cpsw_base = CPSW_BASE,
1050 .cpdma_reg_ofs = 0x800,
1051 .slaves = ARRAY_SIZE(cpsw_slaves),
1052 .slave_data = cpsw_slaves,
1053 .ale_reg_ofs = 0xd00,
1054 .ale_entries = 1024,
1055 .host_port_reg_ofs = 0x108,
1056 .hw_stats_reg_ofs = 0x900,
1057 .mac_control = (1 << 5) /* MIIEN */,
1058 .control = cpsw_control,
1061 .version = CPSW_CTRL_VERSION_2,
1064 int board_eth_init(bd_t *bis)
1066 __raw_writel(RMII_MODE_ENABLE, MAC_MII_SEL);
1067 __raw_writel(0x5D, GMII_SEL);
1069 return cpsw_register(&cpsw_data);
1071 #endif /* CONFIG_DRIVER_TI_CPSW */
1073 #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
1074 int cpu_mmc_init(bd_t *bis)
1076 return omap_mmc_init(1, 0, 0, TX48_MMC_CD_GPIO, -1);
1080 void tx48_disable_watchdog(void)
1082 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
1084 while (readl(&wdtimer->wdtwwps) & (1 << 4))
1086 writel(0xaaaa, &wdtimer->wdtwspr);
1087 while (readl(&wdtimer->wdtwwps) & (1 << 4))
1089 writel(0x5555, &wdtimer->wdtwspr);
1093 LED_STATE_INIT = -1,
1098 void show_activity(int arg)
1100 static int led_state = LED_STATE_INIT;
1103 if (led_state == LED_STATE_INIT) {
1104 last = get_timer(0);
1105 gpio_set_value(TX48_LED_GPIO, 1);
1106 led_state = LED_STATE_ON;
1108 if (get_timer(last) > CONFIG_SYS_HZ) {
1109 last = get_timer(0);
1110 if (led_state == LED_STATE_ON) {
1111 gpio_set_value(TX48_LED_GPIO, 0);
1113 gpio_set_value(TX48_LED_GPIO, 1);
1115 led_state = 1 - led_state;
1120 #ifdef CONFIG_OF_BOARD_SETUP
1121 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1122 #include <jffs2/jffs2.h>
1123 #include <mtd_node.h>
1124 static struct node_info nodes[] = {
1125 { "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
1126 { "ti,am3352-gpmc", MTD_DEV_TYPE_NAND, },
1130 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1131 #endif /* CONFIG_FDT_FIXUP_PARTITIONS */
1133 static const char *tx48_touchpanels[] = {
1139 void ft_board_setup(void *blob, bd_t *bd)
1141 const char *baseboard = getenv("baseboard");
1142 int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1143 const char *video_mode = karo_get_vmode(getenv("video_mode"));
1146 ret = fdt_increase_size(blob, 4096);
1148 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1150 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1151 fdt_fixup_ethernet(blob);
1153 karo_fdt_fixup_touchpanel(blob, tx48_touchpanels,
1154 ARRAY_SIZE(tx48_touchpanels));
1155 karo_fdt_fixup_usb_otg(blob, "usb0", "phys", "vcc-supply");
1156 karo_fdt_fixup_flexcan(blob, stk5_v5);
1158 karo_fdt_update_fb_mode(blob, video_mode);
1160 tx48_disable_watchdog();
1162 if (get_cpu_rev() == 0) {
1163 karo_fdt_del_prop(blob, "lltc,ltc3589-2", 0x34, "interrupts");
1164 karo_fdt_del_prop(blob, "lltc,ltc3589-2", 0x34,
1165 "interrupt-parent");
1168 #endif /* CONFIG_OF_BOARD_SETUP */