2 * Copyright (C) 2011-2013 Lothar Waßmann <LW@KARO-electronics.de>
3 * based on: board/freescale/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
22 #include <fdt_support.h>
26 #include <fsl_esdhc.h>
33 #include <asm/arch/iomux-mx51.h>
34 #include <asm/arch/clock.h>
35 #include <asm/arch/imx-regs.h>
36 #include <asm/arch/crm_regs.h>
37 #include <asm/arch/sys_proto.h>
39 #include "../common/karo.h"
41 #define TX51_FEC_RST_GPIO IMX_GPIO_NR(2, 14)
42 #define TX51_FEC_PWR_GPIO IMX_GPIO_NR(1, 3)
43 #define TX51_FEC_INT_GPIO IMX_GPIO_NR(3, 18)
44 #define TX51_LED_GPIO IMX_GPIO_NR(4, 10)
46 #define TX51_LCD_PWR_GPIO IMX_GPIO_NR(4, 14)
47 #define TX51_LCD_RST_GPIO IMX_GPIO_NR(4, 13)
48 #define TX51_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 2)
50 #define TX51_RESET_OUT_GPIO IMX_GPIO_NR(2, 15)
52 DECLARE_GLOBAL_DATA_PTR;
54 #define IOMUX_SION IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
56 #define FEC_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
58 #define FEC_PAD_CTRL2 MUX_PAD_CTRL(PAD_CTL_DVS | PAD_CTL_SRE_FAST)
59 #define GPIO_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_DVS | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP)
61 static iomux_v3_cfg_t tx51_pads[] = {
62 /* NAND flash pads are set up in lowlevel_init.S */
65 MX51_PAD_EIM_A21__GPIO2_15 | GPIO_PAD_CTRL,
68 #if CONFIG_MXC_UART_BASE == UART1_BASE
69 MX51_PAD_UART1_RXD__UART1_RXD,
70 MX51_PAD_UART1_TXD__UART1_TXD,
71 MX51_PAD_UART1_RTS__UART1_RTS,
72 MX51_PAD_UART1_CTS__UART1_CTS,
74 #if CONFIG_MXC_UART_BASE == UART2_BASE
75 MX51_PAD_UART2_RXD__UART2_RXD,
76 MX51_PAD_UART2_TXD__UART2_TXD,
77 MX51_PAD_EIM_D26__UART2_RTS,
78 MX51_PAD_EIM_D25__UART2_CTS,
80 #if CONFIG_MXC_UART_BASE == UART3_BASE
81 MX51_PAD_UART3_RXD__UART3_RXD,
82 MX51_PAD_UART3_TXD__UART3_TXD,
83 MX51_PAD_EIM_D18__UART3_RTS,
84 MX51_PAD_EIM_D17__UART3_CTS,
87 MX51_PAD_I2C1_DAT__GPIO4_17 | IOMUX_SION,
88 MX51_PAD_I2C1_CLK__GPIO4_16 | IOMUX_SION,
90 /* FEC PHY GPIO functions */
91 MX51_PAD_GPIO1_3__GPIO1_3 | GPIO_PAD_CTRL, /* PHY POWER */
92 MX51_PAD_EIM_A20__GPIO2_14 | GPIO_PAD_CTRL, /* PHY RESET */
93 MX51_PAD_NANDF_CS2__GPIO3_18 | GPIO_PAD_CTRL, /* PHY INT */
96 MX51_PAD_NANDF_CS3__FEC_MDC | FEC_PAD_CTRL,
97 MX51_PAD_EIM_EB2__FEC_MDIO | FEC_PAD_CTRL,
98 MX51_PAD_NANDF_D11__FEC_RX_DV | FEC_PAD_CTRL2,
99 MX51_PAD_EIM_CS4__FEC_RX_ER | FEC_PAD_CTRL2,
100 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK | FEC_PAD_CTRL2,
101 MX51_PAD_NANDF_CS7__FEC_TX_EN | FEC_PAD_CTRL,
102 MX51_PAD_NANDF_D8__FEC_TDATA0 | FEC_PAD_CTRL,
103 MX51_PAD_NANDF_CS4__FEC_TDATA1 | FEC_PAD_CTRL,
104 MX51_PAD_NANDF_CS5__FEC_TDATA2 | FEC_PAD_CTRL,
105 MX51_PAD_NANDF_CS6__FEC_TDATA3 | FEC_PAD_CTRL,
107 /* strap pins for PHY configuration */
108 MX51_PAD_NANDF_RB3__GPIO3_11 | GPIO_PAD_CTRL, /* RX_CLK/REGOFF */
109 MX51_PAD_NANDF_D9__GPIO3_31 | GPIO_PAD_CTRL, /* RXD0/Mode0 */
110 MX51_PAD_EIM_EB3__GPIO2_23 | GPIO_PAD_CTRL, /* RXD1/Mode1 */
111 MX51_PAD_EIM_CS2__GPIO2_27 | GPIO_PAD_CTRL, /* RXD2/Mode2 */
112 MX51_PAD_EIM_CS3__GPIO2_28 | GPIO_PAD_CTRL, /* RXD3/nINTSEL */
113 MX51_PAD_NANDF_RB2__GPIO3_10 | GPIO_PAD_CTRL, /* COL/RMII/CRSDV */
114 MX51_PAD_EIM_CS5__GPIO2_30 | GPIO_PAD_CTRL, /* CRS/PHYAD4 */
116 /* unusable pins on TX51 */
117 MX51_PAD_GPIO1_0__GPIO1_0,
118 MX51_PAD_GPIO1_1__GPIO1_1,
121 static const struct gpio tx51_gpios[] = {
123 { TX51_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_LOW, "RESET_OUT", },
125 /* FEC PHY control GPIOs */
126 { TX51_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC POWER", }, /* PHY POWER */
127 { TX51_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC RESET", }, /* PHY RESET */
128 { TX51_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", }, /* PHY INT (TX_ER) */
130 /* FEC PHY strap pins */
131 { IMX_GPIO_NR(3, 11), GPIOF_OUTPUT_INIT_LOW, "FEC PHY REGOFF", }, /* RX_CLK/REGOFF */
132 { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "FEC PHY MODE0", }, /* RXD0/Mode0 */
133 { IMX_GPIO_NR(2, 23), GPIOF_OUTPUT_INIT_LOW, "FEC PHY MODE1", }, /* RXD1/Mode1 */
134 { IMX_GPIO_NR(2, 27), GPIOF_OUTPUT_INIT_LOW, "FEC PHY MODE2", }, /* RXD2/Mode2 */
135 { IMX_GPIO_NR(2, 28), GPIOF_OUTPUT_INIT_LOW, "FEC PHY nINTSEL", }, /* RXD3/nINTSEL */
136 { IMX_GPIO_NR(3, 10), GPIOF_OUTPUT_INIT_LOW, "FEC PHY RMII", }, /* COL/RMII/CRSDV */
137 { IMX_GPIO_NR(2, 30), GPIOF_OUTPUT_INIT_LOW, "FEC PHY PHYAD4", }, /* CRS/PHYAD4 */
139 /* module internal I2C bus */
140 { IMX_GPIO_NR(4, 17), GPIOF_INPUT, "I2C1 SDA", },
141 { IMX_GPIO_NR(4, 16), GPIOF_INPUT, "I2C1 SCL", },
143 /* Unconnected pins */
144 { IMX_GPIO_NR(1, 0), GPIOF_OUTPUT_INIT_LOW, "N/C", },
145 { IMX_GPIO_NR(1, 1), GPIOF_OUTPUT_INIT_LOW, "N/C", },
151 /* placed in section '.data' to prevent overwriting relocation info
154 static u32 wrsr __attribute__((section(".data")));
156 #define WRSR_POR (1 << 4)
157 #define WRSR_TOUT (1 << 1)
158 #define WRSR_SFTW (1 << 0)
160 static void print_reset_cause(void)
162 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
163 void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
167 printf("Reset cause: ");
169 srsr = readl(&src_regs->srsr);
170 wrsr = readw(wdt_base + 4);
172 if (wrsr & WRSR_POR) {
173 printf("%sPOR", dlm);
176 if (srsr & 0x00004) {
177 printf("%sCSU", dlm);
180 if (srsr & 0x00008) {
181 printf("%sIPP USER", dlm);
184 if (srsr & 0x00010) {
185 if (wrsr & WRSR_SFTW) {
186 printf("%sSOFT", dlm);
189 if (wrsr & WRSR_TOUT) {
190 printf("%sWDOG", dlm);
194 if (srsr & 0x00020) {
195 printf("%sJTAG HIGH-Z", dlm);
198 if (srsr & 0x00040) {
199 printf("%sJTAG SW", dlm);
202 if (srsr & 0x10000) {
203 printf("%sWARM BOOT", dlm);
212 static void tx51_print_cpuinfo(void)
216 cpurev = get_cpu_rev();
218 printf("CPU: Freescale i.MX51 rev%d.%d at %d MHz\n",
219 (cpurev & 0x000F0) >> 4,
220 (cpurev & 0x0000F) >> 0,
221 mxc_get_clock(MXC_ARM_CLK) / 1000000);
226 int board_early_init_f(void)
228 struct mxc_ccm_reg *ccm_regs = (void *)CCM_BASE_ADDR;
230 gpio_request_array(tx51_gpios, ARRAY_SIZE(tx51_gpios));
231 imx_iomux_v3_setup_multiple_pads(tx51_pads, ARRAY_SIZE(tx51_pads));
233 writel(0x77777777, AIPS1_BASE_ADDR + 0x00);
234 writel(0x77777777, AIPS1_BASE_ADDR + 0x04);
236 writel(0x00000000, AIPS1_BASE_ADDR + 0x40);
237 writel(0x00000000, AIPS1_BASE_ADDR + 0x44);
238 writel(0x00000000, AIPS1_BASE_ADDR + 0x48);
239 writel(0x00000000, AIPS1_BASE_ADDR + 0x4c);
240 writel(0x00000000, AIPS1_BASE_ADDR + 0x50);
242 writel(0x77777777, AIPS2_BASE_ADDR + 0x00);
243 writel(0x77777777, AIPS2_BASE_ADDR + 0x04);
245 writel(0x00000000, AIPS2_BASE_ADDR + 0x40);
246 writel(0x00000000, AIPS2_BASE_ADDR + 0x44);
247 writel(0x00000000, AIPS2_BASE_ADDR + 0x48);
248 writel(0x00000000, AIPS2_BASE_ADDR + 0x4c);
249 writel(0x00000000, AIPS2_BASE_ADDR + 0x50);
251 writel(0xffcffffc, &ccm_regs->CCGR0);
252 writel(0x003fffff, &ccm_regs->CCGR1);
253 writel(0x030c003c, &ccm_regs->CCGR2);
254 writel(0x000000ff, &ccm_regs->CCGR3);
255 writel(0x00000000, &ccm_regs->CCGR4);
256 writel(0x003fc003, &ccm_regs->CCGR5);
257 writel(0x00000000, &ccm_regs->CCGR6);
258 writel(0x00000000, &ccm_regs->cmeor);
259 #ifdef CONFIG_CMD_BOOTCE
260 /* WinCE fails to enable these clocks */
261 writel(readl(&ccm_regs->CCGR2) | 0x0c000000, &ccm_regs->CCGR2); /* usboh3_ipg_ahb */
262 writel(readl(&ccm_regs->CCGR4) | 0x30000000, &ccm_regs->CCGR4); /* srtc */
263 writel(readl(&ccm_regs->CCGR6) | 0x00000300, &ccm_regs->CCGR6); /* emi_garb */
270 /* Address of boot parameters */
271 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
279 /* dram_init must store complete ramsize in gd->ram_size */
280 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
283 ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK,
284 CONFIG_SYS_SDRAM_CLK, MXC_DDR_CLK);
286 printf("%s: Failed to set DDR clock to %u MHz: %d\n", __func__,
287 CONFIG_SYS_SDRAM_CLK, ret);
289 debug("%s: DDR clock set to %u.%03u MHz (desig.: %u.000 MHz)\n",
290 __func__, mxc_get_clock(MXC_DDR_CLK) / 1000000,
291 mxc_get_clock(MXC_DDR_CLK) / 1000 % 1000,
292 CONFIG_SYS_SDRAM_CLK);
296 void dram_init_banksize(void)
298 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
299 gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
301 #if CONFIG_NR_DRAM_BANKS > 1
302 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
303 gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
308 #ifdef CONFIG_CMD_MMC
309 static const iomux_v3_cfg_t mmc0_pads[] = {
310 MX51_PAD_SD1_CMD__SD1_CMD,
311 MX51_PAD_SD1_CLK__SD1_CLK,
312 MX51_PAD_SD1_DATA0__SD1_DATA0,
313 MX51_PAD_SD1_DATA1__SD1_DATA1,
314 MX51_PAD_SD1_DATA2__SD1_DATA2,
315 MX51_PAD_SD1_DATA3__SD1_DATA3,
317 MX51_PAD_DISPB2_SER_RS__GPIO3_8 | GPIO_PAD_CTRL,
320 static const iomux_v3_cfg_t mmc1_pads[] = {
321 MX51_PAD_SD2_CMD__SD2_CMD,
322 MX51_PAD_SD2_CLK__SD2_CLK,
323 MX51_PAD_SD2_DATA0__SD2_DATA0,
324 MX51_PAD_SD2_DATA1__SD2_DATA1,
325 MX51_PAD_SD2_DATA2__SD2_DATA2,
326 MX51_PAD_SD2_DATA3__SD2_DATA3,
328 MX51_PAD_DISPB2_SER_DIO__GPIO3_6 | GPIO_PAD_CTRL,
331 static struct tx51_esdhc_cfg {
332 const iomux_v3_cfg_t *pads;
334 struct fsl_esdhc_cfg cfg;
336 } tx51_esdhc_cfg[] = {
339 .num_pads = ARRAY_SIZE(mmc0_pads),
341 .esdhc_base = (void __iomem *)MMC_SDHC1_BASE_ADDR,
344 .cd_gpio = IMX_GPIO_NR(3, 8),
348 .num_pads = ARRAY_SIZE(mmc1_pads),
350 .esdhc_base = (void __iomem *)MMC_SDHC2_BASE_ADDR,
353 .cd_gpio = IMX_GPIO_NR(3, 6),
357 #define to_tx51_esdhc_cfg(p) container_of(p, struct tx51_esdhc_cfg, cfg)
359 int board_mmc_getcd(struct mmc *mmc)
361 struct tx51_esdhc_cfg *cfg = to_tx51_esdhc_cfg(mmc->priv);
363 if (cfg->cd_gpio < 0)
366 debug("SD card %d is %spresent\n",
367 cfg - tx51_esdhc_cfg,
368 gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
369 return !gpio_get_value(cfg->cd_gpio);
372 int board_mmc_init(bd_t *bis)
376 for (i = 0; i < ARRAY_SIZE(tx51_esdhc_cfg); i++) {
378 struct tx51_esdhc_cfg *cfg = &tx51_esdhc_cfg[i];
381 if (i >= CONFIG_SYS_FSL_ESDHC_NUM)
384 imx_iomux_v3_setup_multiple_pads(cfg->pads,
386 cfg->cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
388 fsl_esdhc_initialize(bis, &cfg->cfg);
390 ret = gpio_request_one(cfg->cd_gpio,
391 GPIOF_INPUT, "MMC CD");
393 printf("Error %d requesting GPIO%d_%d\n",
394 ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
398 mmc = find_mmc_device(i);
401 if (board_mmc_getcd(mmc) > 0)
406 #endif /* CONFIG_CMD_MMC */
408 #ifdef CONFIG_FEC_MXC
414 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
417 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
418 struct fuse_bank *bank = &iim->bank[1];
419 struct fuse_bank1_regs *fuse = (struct fuse_bank1_regs *)bank->fuse_regs;
424 for (i = 0; i < ETH_ALEN; i++)
425 mac[ETH_ALEN - i - 1] = readl(&fuse->mac_addr[i]);
428 static iomux_v3_cfg_t tx51_fec_pads[] = {
429 /* reconfigure strap pins for FEC function */
430 MX51_PAD_NANDF_RB3__FEC_RX_CLK | FEC_PAD_CTRL2,
431 MX51_PAD_NANDF_D9__FEC_RDATA0 | FEC_PAD_CTRL2,
432 MX51_PAD_EIM_EB3__FEC_RDATA1 | FEC_PAD_CTRL2,
433 MX51_PAD_EIM_CS2__FEC_RDATA2 | FEC_PAD_CTRL2,
434 MX51_PAD_EIM_CS3__FEC_RDATA3 | FEC_PAD_CTRL2,
435 MX51_PAD_NANDF_RB2__FEC_COL | FEC_PAD_CTRL2,
436 MX51_PAD_EIM_CS5__FEC_CRS | FEC_PAD_CTRL,
439 /* take bit 4 of PHY address from configured PHY address or
440 * set it to 0 if PHYADDR is -1 (probe for PHY)
442 #define PHYAD4 ((CONFIG_FEC_MXC_PHYADDR >> 4) & !(CONFIG_FEC_MXC_PHYADDR >> 5))
444 static struct gpio tx51_fec_gpios[] = {
445 { TX51_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY POWER", },
446 { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY Mode0", }, /* RXD0/Mode0 */
447 { IMX_GPIO_NR(2, 23), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY Mode1", }, /* RXD1/Mode1 */
448 { IMX_GPIO_NR(2, 27), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY Mode2", }, /* RXD2/Mode2 */
449 { IMX_GPIO_NR(2, 28), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY nINTSEL", }, /* RXD3/nINTSEL */
451 { IMX_GPIO_NR(2, 30), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PHYAD4", }, /* CRS/PHYAD4 */
453 { IMX_GPIO_NR(2, 30), GPIOF_OUTPUT_INIT_LOW, "FEC PHY PHYAD4", }, /* CRS/PHYAD4 */
457 int board_eth_init(bd_t *bis)
461 /* Power up the external phy and assert strap options */
462 gpio_request_array(tx51_fec_gpios, ARRAY_SIZE(tx51_fec_gpios));
464 /* delay at least 21ms for the PHY internal POR signal to deassert */
467 /* Deassert RESET to the external phy */
468 gpio_set_value(TX51_FEC_RST_GPIO, 1);
470 /* Without this delay the PHY won't work, though nothing in
471 * the datasheets suggests that it should be necessary!
474 imx_iomux_v3_setup_multiple_pads(tx51_fec_pads,
475 ARRAY_SIZE(tx51_fec_pads));
477 ret = cpu_eth_init(bis);
479 printf("cpu_eth_init() failed: %d\n", ret);
482 #endif /* CONFIG_FEC_MXC */
490 void show_activity(int arg)
492 static int led_state = LED_STATE_INIT;
495 if (led_state == LED_STATE_INIT) {
497 gpio_set_value(TX51_LED_GPIO, 1);
498 led_state = LED_STATE_ON;
500 if (get_timer(last) > CONFIG_SYS_HZ) {
502 if (led_state == LED_STATE_ON) {
503 gpio_set_value(TX51_LED_GPIO, 0);
505 gpio_set_value(TX51_LED_GPIO, 1);
507 led_state = 1 - led_state;
512 static const iomux_v3_cfg_t stk5_pads[] = {
513 /* SW controlled LED on STK5 baseboard */
514 MX51_PAD_CSI2_D13__GPIO4_10 | GPIO_PAD_CTRL,
517 MX51_PAD_GPIO1_4__GPIO1_4 | GPIO_PAD_CTRL,
519 MX51_PAD_GPIO1_6__GPIO1_6 | GPIO_PAD_CTRL,
520 /* USB PHY clock enable */
521 MX51_PAD_GPIO1_7__GPIO1_7 | GPIO_PAD_CTRL,
522 /* USBH1 VBUS enable */
523 MX51_PAD_GPIO1_8__GPIO1_8 | GPIO_PAD_CTRL,
525 MX51_PAD_GPIO1_9__GPIO1_9 | GPIO_PAD_CTRL,
528 static const struct gpio stk5_gpios[] = {
529 { TX51_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
531 { IMX_GPIO_NR(1, 4), GPIOF_OUTPUT_INIT_LOW, "ULPI PHY clk enable", },
532 { IMX_GPIO_NR(1, 6), GPIOF_INPUT, "USBOTG OC", },
533 { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "ULPI PHY reset", },
534 { IMX_GPIO_NR(1, 8), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
535 { IMX_GPIO_NR(1, 9), GPIOF_INPUT, "USBH1 OC", },
539 vidinfo_t panel_info = {
540 /* set to max. size supported by SoC */
544 .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
547 static struct fb_videomode tx51_fb_modes[] = {
549 /* Standard VGA timing */
554 .pixclock = KHZ2PICOS(25175),
561 .sync = FB_SYNC_CLK_LAT_FALL,
564 /* Emerging ETV570 640 x 480 display. Syncs low active,
565 * DE high active, 115.2 mm x 86.4 mm display area
566 * VGA compatible timing
572 .pixclock = KHZ2PICOS(25175),
579 .sync = FB_SYNC_CLK_LAT_FALL,
582 /* Emerging ET0350G0DH6 320 x 240 display.
583 * 70.08 mm x 52.56 mm display area.
589 .pixclock = KHZ2PICOS(6500),
590 .left_margin = 68 - 34,
593 .upper_margin = 18 - 3,
596 .sync = FB_SYNC_CLK_LAT_FALL,
599 /* Emerging ET0430G0DH6 480 x 272 display.
600 * 95.04 mm x 53.856 mm display area.
606 .pixclock = KHZ2PICOS(9000),
613 .sync = FB_SYNC_CLK_LAT_FALL,
616 /* Emerging ET0500G0DH6 800 x 480 display.
617 * 109.6 mm x 66.4 mm display area.
623 .pixclock = KHZ2PICOS(33260),
624 .left_margin = 216 - 128,
626 .right_margin = 1056 - 800 - 216,
627 .upper_margin = 35 - 2,
629 .lower_margin = 525 - 480 - 35,
630 .sync = FB_SYNC_CLK_LAT_FALL,
633 /* Emerging ETQ570G0DH6 320 x 240 display.
634 * 115.2 mm x 86.4 mm display area.
640 .pixclock = KHZ2PICOS(6400),
644 .upper_margin = 16, /* 15 according to datasheet */
645 .vsync_len = 3, /* TVP -> 1>x>5 */
646 .lower_margin = 4, /* 4.5 according to datasheet */
647 .sync = FB_SYNC_CLK_LAT_FALL,
650 /* Emerging ET0700G0DH6 800 x 480 display.
651 * 152.4 mm x 91.44 mm display area.
657 .pixclock = KHZ2PICOS(33260),
658 .left_margin = 216 - 128,
660 .right_margin = 1056 - 800 - 216,
661 .upper_margin = 35 - 2,
663 .lower_margin = 525 - 480 - 35,
664 .sync = FB_SYNC_CLK_LAT_FALL,
667 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
675 .sync = FB_SYNC_CLK_LAT_FALL,
679 static int lcd_enabled = 1;
681 void lcd_enable(void)
684 * global variable from common/lcd.c
685 * Set to 0 here to prevent messages from going to LCD
686 * rather than serial console
691 karo_load_splashimage(1);
693 debug("Switching LCD on\n");
694 gpio_set_value(TX51_LCD_PWR_GPIO, 1);
696 gpio_set_value(TX51_LCD_RST_GPIO, 1);
698 gpio_set_value(TX51_LCD_BACKLIGHT_GPIO, 0);
702 void lcd_disable(void)
705 printf("Disabling LCD\n");
710 void lcd_panel_disable(void)
713 debug("Switching LCD off\n");
714 gpio_set_value(TX51_LCD_BACKLIGHT_GPIO, 1);
715 gpio_set_value(TX51_LCD_RST_GPIO, 0);
716 gpio_set_value(TX51_LCD_PWR_GPIO, 0);
720 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
722 MX51_PAD_CSI2_VSYNC__GPIO4_13,
723 /* LCD POWER_ENABLE */
724 MX51_PAD_CSI2_HSYNC__GPIO4_14,
725 /* LCD Backlight (PWM) */
726 MX51_PAD_GPIO1_2__GPIO1_2,
729 MX51_PAD_DISP1_DAT0__DISP1_DAT0,
730 MX51_PAD_DISP1_DAT1__DISP1_DAT1,
731 MX51_PAD_DISP1_DAT2__DISP1_DAT2,
732 MX51_PAD_DISP1_DAT3__DISP1_DAT3,
733 MX51_PAD_DISP1_DAT4__DISP1_DAT4,
734 MX51_PAD_DISP1_DAT5__DISP1_DAT5,
735 MX51_PAD_DISP1_DAT6__DISP1_DAT6,
736 MX51_PAD_DISP1_DAT7__DISP1_DAT7,
737 MX51_PAD_DISP1_DAT8__DISP1_DAT8,
738 MX51_PAD_DISP1_DAT9__DISP1_DAT9,
739 MX51_PAD_DISP1_DAT10__DISP1_DAT10,
740 MX51_PAD_DISP1_DAT11__DISP1_DAT11,
741 MX51_PAD_DISP1_DAT12__DISP1_DAT12,
742 MX51_PAD_DISP1_DAT13__DISP1_DAT13,
743 MX51_PAD_DISP1_DAT14__DISP1_DAT14,
744 MX51_PAD_DISP1_DAT15__DISP1_DAT15,
745 MX51_PAD_DISP1_DAT16__DISP1_DAT16,
746 MX51_PAD_DISP1_DAT17__DISP1_DAT17,
747 MX51_PAD_DISP1_DAT18__DISP1_DAT18,
748 MX51_PAD_DISP1_DAT19__DISP1_DAT19,
749 MX51_PAD_DISP1_DAT20__DISP1_DAT20,
750 MX51_PAD_DISP1_DAT21__DISP1_DAT21,
751 MX51_PAD_DISP1_DAT22__DISP1_DAT22,
752 MX51_PAD_DISP1_DAT23__DISP1_DAT23,
753 MX51_PAD_DI1_PIN2__DI1_PIN2, /* HSYNC */
754 MX51_PAD_DI1_PIN3__DI1_PIN3, /* VSYNC */
757 static const struct gpio stk5_lcd_gpios[] = {
758 { TX51_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
759 { TX51_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
760 { TX51_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
763 void lcd_ctrl_init(void *lcdbase)
765 int color_depth = 24;
769 struct fb_videomode *p = &tx51_fb_modes[0];
770 struct fb_videomode fb_mode;
771 int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
773 ipu_di_clk_parent_t di_clk_parent = DI_PCLK_PLL3;
774 unsigned long di_clk_rate = 65000000;
777 debug("LCD disabled\n");
781 if (tstc() || (wrsr & WRSR_TOUT)) {
782 debug("Disabling LCD\n");
784 setenv("splashimage", NULL);
790 vm = getenv("video_mode");
792 debug("Disabling LCD\n");
796 if (karo_fdt_get_fb_mode(working_fdt, vm, &fb_mode) == 0) {
798 debug("Using video mode from FDT\n");
800 if (fb_mode.xres > panel_info.vl_col ||
801 fb_mode.yres > panel_info.vl_row) {
802 printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
803 fb_mode.xres, fb_mode.yres,
804 panel_info.vl_col, panel_info.vl_row);
810 debug("Trying compiled-in video modes\n");
811 while (p->name != NULL) {
812 if (strcmp(p->name, vm) == 0) {
813 debug("Using video mode: '%s'\n", p->name);
820 debug("Trying to decode video_mode: '%s'\n", vm);
821 while (*vm != '\0') {
822 if (*vm >= '0' && *vm <= '9') {
825 val = simple_strtoul(vm, &end, 0);
828 if (val > panel_info.vl_col)
829 val = panel_info.vl_col;
831 panel_info.vl_col = val;
833 } else if (!yres_set) {
834 if (val > panel_info.vl_row)
835 val = panel_info.vl_row;
837 panel_info.vl_row = val;
839 } else if (!bpp_set) {
849 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
850 end - vm, vm, color_depth);
853 } else if (!refresh_set) {
879 pix_fmt = IPU_PIX_FMT_RGB24;
880 tmp = strchr(vm, ':');
888 if (p->xres == 0 || p->yres == 0) {
889 printf("Invalid video mode: %s\n", getenv("video_mode"));
891 printf("Supported video modes are:");
892 for (p = &tx51_fb_modes[0]; p->name != NULL; p++) {
893 printf(" %s", p->name);
898 if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
899 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
900 p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
904 panel_info.vl_col = p->xres;
905 panel_info.vl_row = p->yres;
907 switch (color_depth) {
909 panel_info.vl_bpix = LCD_COLOR8;
912 panel_info.vl_bpix = LCD_COLOR16;
915 panel_info.vl_bpix = LCD_COLOR24;
918 p->pixclock = KHZ2PICOS(refresh *
919 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
920 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len)
922 debug("Pixel clock set to %lu.%03lu MHz\n",
923 PICOS2KHZ(p->pixclock) / 1000,
924 PICOS2KHZ(p->pixclock) % 1000);
928 char *modename = getenv("video_mode");
930 printf("Creating new display-timing node from '%s'\n",
932 ret = karo_fdt_create_fb_mode(working_fdt, modename, p);
934 printf("Failed to create new display-timing node from '%s': %d\n",
938 gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
939 imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
940 ARRAY_SIZE(stk5_lcd_pads));
942 debug("Initializing FB driver\n");
944 pix_fmt = IPU_PIX_FMT_RGB24;
946 if (karo_load_splashimage(0) == 0) {
948 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)MXC_CCM_BASE;
949 u32 ccgr4 = readl(&ccm_regs->CCGR4);
951 /* MIPI HSC clock is required for initialization */
952 writel(ccgr4 | (3 << 12), &ccm_regs->CCGR4);
954 gd->arch.ipu_hw_rev = IPUV3_HW_REV_IPUV3DEX;
956 debug("Initializing LCD controller\n");
957 ret = ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1);
958 writel(ccgr4 & ~(3 << 12), &ccm_regs->CCGR4);
960 printf("Failed to initialize FB driver: %d\n", ret);
964 debug("Skipping initialization of LCD controller\n");
968 #define lcd_enabled 0
969 #endif /* CONFIG_LCD */
971 static void stk5_board_init(void)
973 gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
974 imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
977 static void stk5v3_board_init(void)
982 static void tx51_set_cpu_clock(void)
984 unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
987 if (tstc() || (wrsr & WRSR_TOUT))
990 if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
993 ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK, cpu_clk, MXC_ARM_CLK);
995 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
998 printf("CPU clock set to %u.%03u MHz\n",
999 mxc_get_clock(MXC_ARM_CLK) / 1000000,
1000 mxc_get_clock(MXC_ARM_CLK) / 1000 % 1000);
1003 static void tx51_init_mac(void)
1007 imx_get_mac_from_fuse(0, mac);
1008 if (!is_valid_ether_addr(mac)) {
1009 printf("No valid MAC address programmed\n");
1013 eth_setenv_enetaddr("ethaddr", mac);
1014 printf("MAC addr from fuse: %pM\n", mac);
1017 int board_late_init(void)
1020 const char *baseboard;
1022 tx51_set_cpu_clock();
1023 karo_fdt_move_fdt();
1025 baseboard = getenv("baseboard");
1029 if (strncmp(baseboard, "stk5", 4) == 0) {
1030 printf("Baseboard: %s\n", baseboard);
1031 if ((strlen(baseboard) == 4) ||
1032 strcmp(baseboard, "stk5-v3") == 0) {
1033 stk5v3_board_init();
1034 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1035 printf("ERROR: Baseboard '%s' incompatible with TX51 module!\n",
1037 stk5v3_board_init();
1039 printf("WARNING: Unsupported STK5 board rev.: %s\n",
1043 printf("WARNING: Unsupported baseboard: '%s'\n",
1050 gpio_set_value(TX51_RESET_OUT_GPIO, 1);
1054 int checkboard(void)
1056 tx51_print_cpuinfo();
1057 #if CONFIG_NR_DRAM_BANKS > 1
1058 printf("Board: Ka-Ro TX51-8xx1 | TX51-8xx2\n");
1060 printf("Board: Ka-Ro TX51-8xx0\n");
1065 #if defined(CONFIG_OF_BOARD_SETUP)
1066 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1067 #include <jffs2/jffs2.h>
1068 #include <mtd_node.h>
1069 struct node_info nodes[] = {
1070 { "fsl,imx51-nand", MTD_DEV_TYPE_NAND, },
1074 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1077 static const char *tx51_touchpanels[] = {
1082 void ft_board_setup(void *blob, bd_t *bd)
1084 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1085 fdt_fixup_ethernet(blob);
1087 karo_fdt_fixup_touchpanel(blob, tx51_touchpanels,
1088 ARRAY_SIZE(tx51_touchpanels));
1089 karo_fdt_fixup_usb_otg(blob, "fsl,imx-otg", "fsl,usbphy");
1090 karo_fdt_update_fb_mode(blob, getenv("video_mode"));