2 * Copyright (C) 2011-2013 Lothar Waßmann <LW@KARO-electronics.de>
3 * based on: board/freescale/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
22 #include <fdt_support.h>
27 #include <fsl_esdhc.h>
34 #include <asm/arch/iomux-mx53.h>
35 #include <asm/arch/clock.h>
36 #include <asm/arch/imx-regs.h>
37 #include <asm/arch/crm_regs.h>
38 #include <asm/arch/sys_proto.h>
40 #include "../common/karo.h"
42 #define TX53_FEC_RST_GPIO IMX_GPIO_NR(7, 6)
43 #define TX53_FEC_PWR_GPIO IMX_GPIO_NR(3, 20)
44 #define TX53_FEC_INT_GPIO IMX_GPIO_NR(2, 4)
45 #define TX53_LED_GPIO IMX_GPIO_NR(2, 20)
47 #define TX53_LCD_PWR_GPIO IMX_GPIO_NR(2, 31)
48 #define TX53_LCD_RST_GPIO IMX_GPIO_NR(3, 29)
49 #define TX53_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 1)
51 #define TX53_RESET_OUT_GPIO IMX_GPIO_NR(7, 12)
53 DECLARE_GLOBAL_DATA_PTR;
55 #define MX53_GPIO_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_PUE | \
56 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP)
58 #define TX53_SDHC_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
59 PAD_CTL_SRE_FAST | PAD_CTL_PUS_47K_UP)
61 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
63 static iomux_v3_cfg_t tx53_pads[] = {
64 /* NAND flash pads are set up in lowlevel_init.S */
67 #if CONFIG_MXC_UART_BASE == UART1_BASE
68 MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
69 MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
70 MX53_PAD_PATA_IORDY__UART1_RTS,
71 MX53_PAD_PATA_RESET_B__UART1_CTS,
73 #if CONFIG_MXC_UART_BASE == UART2_BASE
74 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
75 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
76 MX53_PAD_PATA_DIOR__UART2_RTS,
77 MX53_PAD_PATA_INTRQ__UART2_CTS,
79 #if CONFIG_MXC_UART_BASE == UART3_BASE
80 MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
81 MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
82 MX53_PAD_PATA_DA_2__UART3_RTS,
83 MX53_PAD_PATA_DA_1__UART3_CTS,
86 MX53_PAD_EIM_D28__I2C1_SDA | MX53_GPIO_PAD_CTRL,
87 MX53_PAD_EIM_D21__I2C1_SCL | MX53_GPIO_PAD_CTRL,
89 /* FEC PHY GPIO functions */
90 MX53_PAD_EIM_D20__GPIO3_20, /* PHY POWER */
91 MX53_PAD_PATA_DA_0__GPIO7_6, /* PHY RESET */
92 MX53_PAD_PATA_DATA4__GPIO2_4, /* PHY INT */
95 MX53_PAD_FEC_MDC__FEC_MDC,
96 MX53_PAD_FEC_MDIO__FEC_MDIO,
97 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
98 MX53_PAD_FEC_RX_ER__FEC_RX_ER,
99 MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
100 MX53_PAD_FEC_RXD1__FEC_RDATA_1,
101 MX53_PAD_FEC_RXD0__FEC_RDATA_0,
102 MX53_PAD_FEC_TX_EN__FEC_TX_EN,
103 MX53_PAD_FEC_TXD1__FEC_TDATA_1,
104 MX53_PAD_FEC_TXD0__FEC_TDATA_0,
107 static const struct gpio tx53_gpios[] = {
108 { TX53_RESET_OUT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "#RESET_OUT", },
109 { TX53_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
110 { TX53_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
111 { TX53_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
117 /* placed in section '.data' to prevent overwriting relocation info
120 static u32 wrsr __attribute__((section(".data")));
122 #define WRSR_POR (1 << 4)
123 #define WRSR_TOUT (1 << 1)
124 #define WRSR_SFTW (1 << 0)
126 static void print_reset_cause(void)
128 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
129 void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
133 printf("Reset cause: ");
135 srsr = readl(&src_regs->srsr);
136 wrsr = readw(wdt_base + 4);
138 if (wrsr & WRSR_POR) {
139 printf("%sPOR", dlm);
142 if (srsr & 0x00004) {
143 printf("%sCSU", dlm);
146 if (srsr & 0x00008) {
147 printf("%sIPP USER", dlm);
150 if (srsr & 0x00010) {
151 if (wrsr & WRSR_SFTW) {
152 printf("%sSOFT", dlm);
155 if (wrsr & WRSR_TOUT) {
156 printf("%sWDOG", dlm);
160 if (srsr & 0x00020) {
161 printf("%sJTAG HIGH-Z", dlm);
164 if (srsr & 0x00040) {
165 printf("%sJTAG SW", dlm);
168 if (srsr & 0x10000) {
169 printf("%sWARM BOOT", dlm);
178 #define pr_lpgr_val(v, n, b, c) do { \
179 u32 __v = ((v) >> (b)) & ((1 << (c)) - 1); \
181 printf(" %s=%0*x", #n, DIV_ROUND_UP(c, 4), __v); \
184 static inline void print_lpgr(u32 lpgr)
189 printf("LPGR=%08x:", lpgr);
190 pr_lpgr_val(lpgr, SW_ISO, 31, 1);
191 pr_lpgr_val(lpgr, SECONDARY_BOOT, 30, 1);
192 pr_lpgr_val(lpgr, BLOCK_REWRITE, 29, 1);
193 pr_lpgr_val(lpgr, WDOG_BOOT, 28, 1);
194 pr_lpgr_val(lpgr, SBMR_SHADOW, 0, 26);
198 static void tx53_print_cpuinfo(void)
201 struct srtc_regs *srtc_regs = (void *)SRTC_BASE_ADDR;
202 u32 lpgr = readl(&srtc_regs->lpgr);
204 cpurev = get_cpu_rev();
206 printf("CPU: Freescale i.MX53 rev%d.%d at %d MHz\n",
207 (cpurev & 0x000F0) >> 4,
208 (cpurev & 0x0000F) >> 0,
209 mxc_get_clock(MXC_ARM_CLK) / 1000000);
215 if (lpgr & (1 << 30))
216 printf("WARNING: U-Boot started from secondary bootstrap image\n");
219 struct mxc_ccm_reg *ccm_regs = (void *)CCM_BASE_ADDR;
220 u32 ccgr4 = readl(&ccm_regs->CCGR4);
222 writel(ccgr4 | MXC_CCM_CCGR4_SRTC(3), &ccm_regs->CCGR4);
223 writel(0, &srtc_regs->lpgr);
224 writel(ccgr4, &ccm_regs->CCGR4);
232 LTC3589_CLIRQ = 0x21,
233 LTC3589_B1DTV1 = 0x23,
234 LTC3589_B1DTV2 = 0x24,
235 LTC3589_VRRCR = 0x25,
236 LTC3589_B2DTV1 = 0x26,
237 LTC3589_B2DTV2 = 0x27,
238 LTC3589_B3DTV1 = 0x29,
239 LTC3589_B3DTV2 = 0x2a,
240 LTC3589_L2DTV1 = 0x32,
241 LTC3589_L2DTV2 = 0x33,
244 #define LTC3589_BnDTV1_PGOOD_MASK (1 << 5)
245 #define LTC3589_BnDTV1_SLEW(n) (((n) & 3) << 6)
247 #define LTC3589_CLK_RATE_LOW (1 << 5)
249 #define LTC3589_SCR2_PGOOD_SHUTDWN (1 << 7)
251 #define VDD_LDO2_VAL mV_to_regval(vout_to_vref(1325 * 10, 2))
252 #define VDD_CORE_VAL mV_to_regval(vout_to_vref(1100 * 10, 3))
253 #define VDD_SOC_VAL mV_to_regval(vout_to_vref(1325 * 10, 4))
254 #define VDD_BUCK3_VAL mV_to_regval(vout_to_vref(2500 * 10, 5))
256 #ifndef CONFIG_SYS_TX53_HWREV_2
257 /* LDO2 vref divider */
260 /* BUCK1 vref divider */
263 /* BUCK2 vref divider */
266 /* BUCK3 vref divider */
270 /* no dividers on vref */
281 /* calculate voltages in 10mV */
282 #define R1(idx) R1_##idx
283 #define R2(idx) R2_##idx
285 #define vout_to_vref(vout, idx) ((vout) * R2(idx) / (R1(idx) + R2(idx)))
286 #define vref_to_vout(vref, idx) DIV_ROUND_UP((vref) * (R1(idx) + R2(idx)), R2(idx))
288 #define mV_to_regval(mV) DIV_ROUND(((((mV) < 3625) ? 3625 : (mV)) - 3625), 125)
289 #define regval_to_mV(v) (((v) * 125 + 3625))
291 static struct pmic_regs {
292 enum LTC3589_REGS addr;
295 { LTC3589_SCR1, 0x15, }, /* burst mode for all regulators except buck boost */
296 { LTC3589_SCR2, LTC3589_SCR2_PGOOD_SHUTDWN, }, /* enable shutdown on PGOOD Timeout */
298 { LTC3589_L2DTV1, VDD_LDO2_VAL | LTC3589_BnDTV1_SLEW(3) | LTC3589_BnDTV1_PGOOD_MASK, },
299 { LTC3589_L2DTV2, VDD_LDO2_VAL | LTC3589_CLK_RATE_LOW, },
301 { LTC3589_B1DTV1, VDD_CORE_VAL | LTC3589_BnDTV1_SLEW(3) | LTC3589_BnDTV1_PGOOD_MASK, },
302 { LTC3589_B1DTV2, VDD_CORE_VAL, },
304 { LTC3589_B2DTV1, VDD_SOC_VAL | LTC3589_BnDTV1_SLEW(3) | LTC3589_BnDTV1_PGOOD_MASK, },
305 { LTC3589_B2DTV2, VDD_SOC_VAL, },
307 { LTC3589_B3DTV1, VDD_BUCK3_VAL | LTC3589_BnDTV1_SLEW(3) | LTC3589_BnDTV1_PGOOD_MASK, },
308 { LTC3589_B3DTV2, VDD_BUCK3_VAL, },
310 /* Select ref 0 for all regulators and enable slew */
311 { LTC3589_VCCR, 0x55, },
313 { LTC3589_CLIRQ, 0, }, /* clear all interrupt flags */
316 static int setup_pmic_voltages(void)
322 ret = i2c_probe(CONFIG_SYS_I2C_SLAVE);
324 printf("Failed to initialize I2C\n");
328 ret = i2c_read(CONFIG_SYS_I2C_SLAVE, 0x11, 1, &value, 1);
330 printf("%s: i2c_read error: %d\n", __func__, ret);
334 for (i = 0; i < ARRAY_SIZE(ltc3589_regs); i++) {
335 ret = i2c_read(CONFIG_SYS_I2C_SLAVE, ltc3589_regs[i].addr, 1,
337 debug("Writing %02x to reg %02x (%02x)\n",
338 ltc3589_regs[i].val, ltc3589_regs[i].addr, value);
339 ret = i2c_write(CONFIG_SYS_I2C_SLAVE, ltc3589_regs[i].addr, 1,
340 <c3589_regs[i].val, 1);
342 printf("%s: failed to write PMIC register %02x: %d\n",
343 __func__, ltc3589_regs[i].addr, ret);
347 printf("VDDCORE set to %umV\n",
348 DIV_ROUND(vref_to_vout(regval_to_mV(VDD_CORE_VAL), 3), 10));
350 printf("VDDSOC set to %umV\n",
351 DIV_ROUND(vref_to_vout(regval_to_mV(VDD_SOC_VAL), 4), 10));
358 } tx53_core_voltages[] = {
359 { 800000000, 1100, },
360 { 1000000000, 1240, },
361 { 1200000000, 1350, },
364 int adjust_core_voltage(u32 freq)
369 printf("%s@%d\n", __func__, __LINE__);
371 for (i = 0; i < ARRAY_SIZE(tx53_core_voltages); i++) {
372 if (freq <= tx53_core_voltages[i].max_freq) {
374 const int max_tries = 10;
375 const int delay_us = 1;
376 u32 mV = tx53_core_voltages[i].mV;
377 u8 val = mV_to_regval(vout_to_vref(mV * 10, 3));
380 debug("regval[%umV]=%02x\n", mV, val);
382 ret = i2c_read(CONFIG_SYS_I2C_SLAVE, LTC3589_B1DTV1, 1,
385 printf("%s: failed to read PMIC register %02x: %d\n",
386 __func__, LTC3589_B1DTV1, ret);
389 debug("Changing reg %02x from %02x to %02x\n",
390 LTC3589_B1DTV1, v, (v & ~0x1f) |
391 mV_to_regval(vout_to_vref(mV * 10, 3)));
393 v |= mV_to_regval(vout_to_vref(mV * 10, 3));
394 ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3589_B1DTV1, 1,
397 printf("%s: failed to write PMIC register %02x: %d\n",
398 __func__, LTC3589_B1DTV1, ret);
401 ret = i2c_read(CONFIG_SYS_I2C_SLAVE, LTC3589_VCCR, 1,
404 printf("%s: failed to read PMIC register %02x: %d\n",
405 __func__, LTC3589_VCCR, ret);
409 ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3589_VCCR, 1,
412 printf("%s: failed to write PMIC register %02x: %d\n",
413 __func__, LTC3589_VCCR, ret);
416 for (retries = 0; retries < max_tries; retries++) {
417 ret = i2c_read(CONFIG_SYS_I2C_SLAVE,
418 LTC3589_VCCR, 1, &v, 1);
420 printf("%s: failed to read PMIC register %02x: %d\n",
421 __func__, LTC3589_VCCR, ret);
429 printf("change of VDDCORE did not complete after %uµs\n",
434 printf("VDDCORE set to %umV after %u loops\n",
435 DIV_ROUND(vref_to_vout(regval_to_mV(val & 0x1f), 3),
443 int board_early_init_f(void)
445 struct mxc_ccm_reg *ccm_regs = (void *)CCM_BASE_ADDR;
447 gpio_request_array(tx53_gpios, ARRAY_SIZE(tx53_gpios));
448 imx_iomux_v3_setup_multiple_pads(tx53_pads, ARRAY_SIZE(tx53_pads));
450 writel(0x77777777, AIPS1_BASE_ADDR + 0x00);
451 writel(0x77777777, AIPS1_BASE_ADDR + 0x04);
453 writel(0x00000000, AIPS1_BASE_ADDR + 0x40);
454 writel(0x00000000, AIPS1_BASE_ADDR + 0x44);
455 writel(0x00000000, AIPS1_BASE_ADDR + 0x48);
456 writel(0x00000000, AIPS1_BASE_ADDR + 0x4c);
457 writel(0x00000000, AIPS1_BASE_ADDR + 0x50);
459 writel(0x77777777, AIPS2_BASE_ADDR + 0x00);
460 writel(0x77777777, AIPS2_BASE_ADDR + 0x04);
462 writel(0x00000000, AIPS2_BASE_ADDR + 0x40);
463 writel(0x00000000, AIPS2_BASE_ADDR + 0x44);
464 writel(0x00000000, AIPS2_BASE_ADDR + 0x48);
465 writel(0x00000000, AIPS2_BASE_ADDR + 0x4c);
466 writel(0x00000000, AIPS2_BASE_ADDR + 0x50);
468 writel(0xffcf0fff, &ccm_regs->CCGR0);
469 writel(0x000fffcf, &ccm_regs->CCGR1);
470 writel(0x033c0000, &ccm_regs->CCGR2);
471 writel(0x000000ff, &ccm_regs->CCGR3);
472 writel(0x00000000, &ccm_regs->CCGR4);
473 writel(0x00fff033, &ccm_regs->CCGR5);
474 writel(0x0f00030f, &ccm_regs->CCGR6);
475 writel(0xfff00000, &ccm_regs->CCGR7);
476 writel(0x00000000, &ccm_regs->cmeor);
485 /* Address of boot parameters */
486 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
488 if (ctrlc() || (wrsr & WRSR_TOUT)) {
489 if (wrsr & WRSR_TOUT)
490 printf("WDOG RESET detected; Skipping PMIC setup\n");
492 printf("<CTRL-C> detected; safeboot enabled\n");
496 ret = setup_pmic_voltages();
498 printf("Failed to setup PMIC voltages\n");
509 * U-Boot doesn't support RAM banks with intervening holes,
510 * so let U-Boot only know about the first bank for its
511 * internal data structures. The size reported to Linux is
512 * determined from the individual bank sizes.
514 gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, SZ_1G);
516 ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK,
517 CONFIG_SYS_SDRAM_CLK, MXC_DDR_CLK);
519 printf("%s: Failed to set DDR clock to %u MHz: %d\n", __func__,
520 CONFIG_SYS_SDRAM_CLK, ret);
522 debug("%s: DDR clock set to %u.%03u MHz (desig.: %u.000 MHz)\n",
523 __func__, mxc_get_clock(MXC_DDR_CLK) / 1000000,
524 mxc_get_clock(MXC_DDR_CLK) / 1000 % 1000,
525 CONFIG_SYS_SDRAM_CLK);
529 void dram_init_banksize(void)
531 long total_size = gd->ram_size;
533 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
534 gd->bd->bi_dram[0].size = gd->ram_size;
536 #if CONFIG_NR_DRAM_BANKS > 1
537 gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, SZ_1G);
539 if (gd->bd->bi_dram[1].size) {
540 debug("Found %luMiB SDRAM in bank 2\n",
541 gd->bd->bi_dram[1].size / SZ_1M);
542 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
543 total_size += gd->bd->bi_dram[1].size;
546 if (total_size != CONFIG_SYS_SDRAM_SIZE)
547 printf("WARNING: SDRAM size mismatch: %uMiB configured; %luMiB detected\n",
548 CONFIG_SYS_SDRAM_SIZE / SZ_1M, total_size / SZ_1M);
551 #ifdef CONFIG_CMD_MMC
552 static const iomux_v3_cfg_t mmc0_pads[] = {
553 MX53_PAD_SD1_CMD__ESDHC1_CMD | TX53_SDHC_PAD_CTRL,
554 MX53_PAD_SD1_CLK__ESDHC1_CLK | TX53_SDHC_PAD_CTRL,
555 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 | TX53_SDHC_PAD_CTRL,
556 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 | TX53_SDHC_PAD_CTRL,
557 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 | TX53_SDHC_PAD_CTRL,
558 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 | TX53_SDHC_PAD_CTRL,
560 MX53_PAD_EIM_D24__GPIO3_24 | MX53_GPIO_PAD_CTRL,
563 static const iomux_v3_cfg_t mmc1_pads[] = {
564 MX53_PAD_SD2_CMD__ESDHC2_CMD | TX53_SDHC_PAD_CTRL,
565 MX53_PAD_SD2_CLK__ESDHC2_CLK | TX53_SDHC_PAD_CTRL,
566 MX53_PAD_SD2_DATA0__ESDHC2_DAT0 | TX53_SDHC_PAD_CTRL,
567 MX53_PAD_SD2_DATA1__ESDHC2_DAT1 | TX53_SDHC_PAD_CTRL,
568 MX53_PAD_SD2_DATA2__ESDHC2_DAT2 | TX53_SDHC_PAD_CTRL,
569 MX53_PAD_SD2_DATA3__ESDHC2_DAT3 | TX53_SDHC_PAD_CTRL,
571 MX53_PAD_EIM_D25__GPIO3_25 | MX53_GPIO_PAD_CTRL,
574 static struct tx53_esdhc_cfg {
575 const iomux_v3_cfg_t *pads;
577 struct fsl_esdhc_cfg cfg;
579 } tx53_esdhc_cfg[] = {
582 .num_pads = ARRAY_SIZE(mmc0_pads),
584 .esdhc_base = (void __iomem *)MMC_SDHC1_BASE_ADDR,
587 .cd_gpio = IMX_GPIO_NR(3, 24),
591 .num_pads = ARRAY_SIZE(mmc1_pads),
593 .esdhc_base = (void __iomem *)MMC_SDHC2_BASE_ADDR,
596 .cd_gpio = IMX_GPIO_NR(3, 25),
600 static inline struct tx53_esdhc_cfg *to_tx53_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
602 return container_of(cfg, struct tx53_esdhc_cfg, cfg);
605 int board_mmc_getcd(struct mmc *mmc)
607 struct tx53_esdhc_cfg *cfg = to_tx53_esdhc_cfg(mmc->priv);
609 if (cfg->cd_gpio < 0)
612 debug("SD card %d is %spresent\n",
613 cfg - tx53_esdhc_cfg,
614 gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
615 return !gpio_get_value(cfg->cd_gpio);
618 int board_mmc_init(bd_t *bis)
622 for (i = 0; i < ARRAY_SIZE(tx53_esdhc_cfg); i++) {
624 struct tx53_esdhc_cfg *cfg = &tx53_esdhc_cfg[i];
627 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
628 cfg->cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
630 ret = gpio_request_one(cfg->cd_gpio,
631 GPIOFLAG_INPUT, "MMC CD");
633 printf("Error %d requesting GPIO%d_%d\n",
634 ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
638 debug("%s: Initializing MMC slot %d\n", __func__, i);
639 fsl_esdhc_initialize(bis, &cfg->cfg);
641 mmc = find_mmc_device(i);
644 if (board_mmc_getcd(mmc) > 0)
649 #endif /* CONFIG_CMD_MMC */
651 #ifdef CONFIG_FEC_MXC
657 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
660 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
661 struct fuse_bank *bank = &iim->bank[1];
662 struct fuse_bank1_regs *fuse = (struct fuse_bank1_regs *)bank->fuse_regs;
667 for (i = 0; i < ETH_ALEN; i++)
668 mac[i] = readl(&fuse->mac_addr[i]);
671 #define FEC_PAD_CTL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
673 #define FEC_PAD_CTL2 (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
674 #define GPIO_PAD_CTL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
676 int board_eth_init(bd_t *bis)
680 /* delay at least 21ms for the PHY internal POR signal to deassert */
683 /* Deassert RESET to the external phy */
684 gpio_set_value(TX53_FEC_RST_GPIO, 1);
686 ret = cpu_eth_init(bis);
688 printf("cpu_eth_init() failed: %d\n", ret);
692 #endif /* CONFIG_FEC_MXC */
700 void show_activity(int arg)
702 static int led_state = LED_STATE_INIT;
705 if (led_state == LED_STATE_INIT) {
707 gpio_set_value(TX53_LED_GPIO, 1);
708 led_state = LED_STATE_ON;
710 if (get_timer(last) > CONFIG_SYS_HZ) {
712 if (led_state == LED_STATE_ON) {
713 gpio_set_value(TX53_LED_GPIO, 0);
715 gpio_set_value(TX53_LED_GPIO, 1);
717 led_state = 1 - led_state;
722 static const iomux_v3_cfg_t stk5_pads[] = {
723 /* SW controlled LED on STK5 baseboard */
724 MX53_PAD_EIM_A18__GPIO2_20,
726 /* I2C bus on DIMM pins 40/41 */
727 MX53_PAD_GPIO_6__I2C3_SDA | MX53_GPIO_PAD_CTRL,
728 MX53_PAD_GPIO_3__I2C3_SCL | MX53_GPIO_PAD_CTRL,
730 /* TSC200x PEN IRQ */
731 MX53_PAD_EIM_D26__GPIO3_26 | MX53_GPIO_PAD_CTRL,
733 /* EDT-FT5x06 Polytouch panel */
734 MX53_PAD_NANDF_CS2__GPIO6_15 | MX53_GPIO_PAD_CTRL, /* IRQ */
735 MX53_PAD_EIM_A16__GPIO2_22 | MX53_GPIO_PAD_CTRL, /* RESET */
736 MX53_PAD_EIM_A17__GPIO2_21 | MX53_GPIO_PAD_CTRL, /* WAKE */
739 MX53_PAD_EIM_D31__GPIO3_31 | MX53_GPIO_PAD_CTRL, /* VBUSEN */
740 MX53_PAD_EIM_D30__GPIO3_30 | MX53_GPIO_PAD_CTRL, /* OC */
742 MX53_PAD_GPIO_7__GPIO1_7, /* VBUSEN */
743 MX53_PAD_GPIO_8__GPIO1_8, /* OC */
745 /* DS1339 Interrupt */
746 MX53_PAD_DI0_PIN4__GPIO4_20 | MX53_GPIO_PAD_CTRL,
749 static const struct gpio stk5_gpios[] = {
750 { TX53_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
752 { IMX_GPIO_NR(1, 8), GPIOFLAG_INPUT, "USBOTG OC", },
753 { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
754 { IMX_GPIO_NR(3, 30), GPIOFLAG_INPUT, "USBH1 OC", },
755 { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
759 static u16 tx53_cmap[256];
760 vidinfo_t panel_info = {
761 /* set to max. size supported by SoC */
765 .vl_bpix = LCD_COLOR32, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
769 static struct fb_videomode tx53_fb_modes[] = {
770 #ifndef CONFIG_SYS_LVDS_IF
772 /* Standard VGA timing */
777 .pixclock = KHZ2PICOS(25175),
784 .sync = FB_SYNC_CLK_LAT_FALL,
787 /* Emerging ETV570 640 x 480 display. Syncs low active,
788 * DE high active, 115.2 mm x 86.4 mm display area
789 * VGA compatible timing
795 .pixclock = KHZ2PICOS(25175),
802 .sync = FB_SYNC_CLK_LAT_FALL,
805 /* Emerging ET0350G0DH6 320 x 240 display.
806 * 70.08 mm x 52.56 mm display area.
812 .pixclock = KHZ2PICOS(6500),
813 .left_margin = 68 - 34,
816 .upper_margin = 18 - 3,
819 .sync = FB_SYNC_CLK_LAT_FALL,
822 /* Emerging ET0430G0DH6 480 x 272 display.
823 * 95.04 mm x 53.856 mm display area.
829 .pixclock = KHZ2PICOS(9000),
836 .sync = FB_SYNC_CLK_LAT_FALL,
839 /* Emerging ET0500G0DH6 800 x 480 display.
840 * 109.6 mm x 66.4 mm display area.
846 .pixclock = KHZ2PICOS(33260),
847 .left_margin = 216 - 128,
849 .right_margin = 1056 - 800 - 216,
850 .upper_margin = 35 - 2,
852 .lower_margin = 525 - 480 - 35,
853 .sync = FB_SYNC_CLK_LAT_FALL,
856 /* Emerging ETQ570G0DH6 320 x 240 display.
857 * 115.2 mm x 86.4 mm display area.
863 .pixclock = KHZ2PICOS(6400),
867 .upper_margin = 16, /* 15 according to datasheet */
868 .vsync_len = 3, /* TVP -> 1>x>5 */
869 .lower_margin = 4, /* 4.5 according to datasheet */
870 .sync = FB_SYNC_CLK_LAT_FALL,
873 /* Emerging ET0700G0DH6 800 x 480 display.
874 * 152.4 mm x 91.44 mm display area.
880 .pixclock = KHZ2PICOS(33260),
881 .left_margin = 216 - 128,
883 .right_margin = 1056 - 800 - 216,
884 .upper_margin = 35 - 2,
886 .lower_margin = 525 - 480 - 35,
887 .sync = FB_SYNC_CLK_LAT_FALL,
891 /* HannStar HSD100PXN1
892 * 202.7m mm x 152.06 mm display area.
894 .name = "HSD100PXN1",
898 .pixclock = KHZ2PICOS(65000),
905 .sync = FB_SYNC_CLK_LAT_FALL,
909 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
917 .sync = FB_SYNC_CLK_LAT_FALL,
921 static int lcd_enabled = 1;
922 static int lcd_bl_polarity;
924 static int lcd_backlight_polarity(void)
926 return lcd_bl_polarity;
929 void lcd_enable(void)
932 * global variable from common/lcd.c
933 * Set to 0 here to prevent messages from going to LCD
934 * rather than serial console
939 karo_load_splashimage(1);
941 debug("Switching LCD on\n");
942 gpio_set_value(TX53_LCD_PWR_GPIO, 1);
944 gpio_set_value(TX53_LCD_RST_GPIO, 1);
946 gpio_set_value(TX53_LCD_BACKLIGHT_GPIO,
947 lcd_backlight_polarity());
951 void lcd_disable(void)
954 printf("Disabling LCD\n");
959 void lcd_panel_disable(void)
962 debug("Switching LCD off\n");
963 gpio_set_value(TX53_LCD_BACKLIGHT_GPIO,
964 !lcd_backlight_polarity());
965 gpio_set_value(TX53_LCD_RST_GPIO, 0);
966 gpio_set_value(TX53_LCD_PWR_GPIO, 0);
970 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
972 MX53_PAD_EIM_D29__GPIO3_29 | MX53_GPIO_PAD_CTRL,
973 /* LCD POWER_ENABLE */
974 MX53_PAD_EIM_EB3__GPIO2_31 | MX53_GPIO_PAD_CTRL,
975 /* LCD Backlight (PWM) */
976 MX53_PAD_GPIO_1__GPIO1_1 | MX53_GPIO_PAD_CTRL,
979 #ifndef CONFIG_SYS_LVDS_IF
981 MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
982 MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
983 MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
984 MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
985 MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
986 MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
987 MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
988 MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
989 MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
990 MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
991 MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
992 MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
993 MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
994 MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
995 MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
996 MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
997 MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
998 MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
999 MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
1000 MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
1001 MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
1002 MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
1003 MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
1004 MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
1005 MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
1006 MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
1007 MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
1008 MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
1011 MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3,
1012 MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2,
1013 MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK,
1014 MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1,
1015 MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0,
1016 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
1017 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
1018 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
1019 MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
1020 MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
1024 static const struct gpio stk5_lcd_gpios[] = {
1025 { TX53_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
1026 { TX53_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
1027 { TX53_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
1030 void lcd_ctrl_init(void *lcdbase)
1032 int color_depth = 24;
1033 const char *video_mode = karo_get_vmode(getenv("video_mode"));
1037 struct fb_videomode *p = &tx53_fb_modes[0];
1038 struct fb_videomode fb_mode;
1039 int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
1042 ipu_di_clk_parent_t di_clk_parent = is_lvds() ? DI_PCLK_LDB : DI_PCLK_PLL3;
1043 unsigned long di_clk_rate = 65000000;
1046 debug("LCD disabled\n");
1050 if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1051 debug("Disabling LCD\n");
1053 setenv("splashimage", NULL);
1057 karo_fdt_move_fdt();
1058 lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1060 if (video_mode == NULL) {
1061 debug("Disabling LCD\n");
1066 if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1068 debug("Using video mode from FDT\n");
1070 if (fb_mode.xres > panel_info.vl_col ||
1071 fb_mode.yres > panel_info.vl_row) {
1072 printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1073 fb_mode.xres, fb_mode.yres,
1074 panel_info.vl_col, panel_info.vl_row);
1079 if (p->name != NULL)
1080 debug("Trying compiled-in video modes\n");
1081 while (p->name != NULL) {
1082 if (strcmp(p->name, vm) == 0) {
1083 debug("Using video mode: '%s'\n", p->name);
1090 debug("Trying to decode video_mode: '%s'\n", vm);
1091 while (*vm != '\0') {
1092 if (*vm >= '0' && *vm <= '9') {
1095 val = simple_strtoul(vm, &end, 0);
1098 if (val > panel_info.vl_col)
1099 val = panel_info.vl_col;
1101 panel_info.vl_col = val;
1103 } else if (!yres_set) {
1104 if (val > panel_info.vl_row)
1105 val = panel_info.vl_row;
1107 panel_info.vl_row = val;
1109 } else if (!bpp_set) {
1114 pix_fmt = IPU_PIX_FMT_LVDS888;
1128 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1129 end - vm, vm, color_depth);
1132 } else if (!refresh_set) {
1159 if (p->xres == 0 || p->yres == 0) {
1160 printf("Invalid video mode: %s\n", getenv("video_mode"));
1162 printf("Supported video modes are:");
1163 for (p = &tx53_fb_modes[0]; p->name != NULL; p++) {
1164 printf(" %s", p->name);
1169 if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1170 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1171 p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1175 panel_info.vl_col = p->xres;
1176 panel_info.vl_row = p->yres;
1178 switch (color_depth) {
1180 panel_info.vl_bpix = LCD_COLOR8;
1183 panel_info.vl_bpix = LCD_COLOR16;
1186 panel_info.vl_bpix = LCD_COLOR32;
1189 p->pixclock = KHZ2PICOS(refresh *
1190 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1191 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1193 debug("Pixel clock set to %lu.%03lu MHz\n",
1194 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1196 if (p != &fb_mode) {
1199 debug("Creating new display-timing node from '%s'\n",
1201 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1203 printf("Failed to create new display-timing node from '%s': %d\n",
1207 gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1208 imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1209 ARRAY_SIZE(stk5_lcd_pads));
1211 lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
1212 switch (lcd_bus_width) {
1214 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
1218 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
1223 pix_fmt = IPU_PIX_FMT_RGB565;
1229 printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
1234 int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
1235 int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
1238 if (lvds_chan_mask == 0) {
1239 printf("No LVDS channel active\n");
1244 gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
1245 if (lcd_bus_width == 24)
1246 gpr2 |= (1 << 5) | (1 << 7);
1247 gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
1248 gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
1249 debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
1250 writel(gpr2, IOMUXC_BASE_ADDR + 8);
1252 if (karo_load_splashimage(0) == 0) {
1255 gd->arch.ipu_hw_rev = IPUV3_HW_REV_IPUV3M;
1257 debug("Initializing LCD controller\n");
1258 ret = ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1);
1260 printf("Failed to initialize FB driver: %d\n", ret);
1264 debug("Skipping initialization of LCD controller\n");
1268 #define lcd_enabled 0
1269 #endif /* CONFIG_LCD */
1271 static void stk5_board_init(void)
1273 gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1274 imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1277 static void stk5v3_board_init(void)
1282 static void stk5v5_board_init(void)
1286 gpio_request_one(IMX_GPIO_NR(4, 21), GPIOFLAG_OUTPUT_INIT_HIGH,
1287 "Flexcan Transceiver");
1288 imx_iomux_v3_setup_pad(MX53_PAD_DISP0_DAT0__GPIO4_21);
1291 static void tx53_set_cpu_clock(void)
1293 unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1295 if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1298 if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1299 printf("%s detected; skipping cpu clock change\n",
1300 (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1304 if (mxc_set_clock(CONFIG_SYS_MX5_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1305 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1306 printf("CPU clock set to %lu.%03lu MHz\n",
1307 cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1309 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1313 static void tx53_init_mac(void)
1317 imx_get_mac_from_fuse(0, mac);
1318 if (!is_valid_ether_addr(mac)) {
1319 printf("No valid MAC address programmed\n");
1323 printf("MAC addr from fuse: %pM\n", mac);
1324 eth_setenv_enetaddr("ethaddr", mac);
1327 int board_late_init(void)
1330 const char *baseboard;
1334 tx53_set_cpu_clock();
1337 setenv_ulong("safeboot", 1);
1338 else if (wrsr & WRSR_TOUT)
1339 setenv_ulong("wdreset", 1);
1341 karo_fdt_move_fdt();
1343 baseboard = getenv("baseboard");
1347 printf("Baseboard: %s\n", baseboard);
1349 if (strncmp(baseboard, "stk5", 4) == 0) {
1350 if ((strlen(baseboard) == 4) ||
1351 strcmp(baseboard, "stk5-v3") == 0) {
1352 stk5v3_board_init();
1353 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1354 const char *otg_mode = getenv("otg_mode");
1356 if (otg_mode && strcmp(otg_mode, "host") == 0) {
1357 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1358 otg_mode, baseboard);
1359 setenv("otg_mode", "none");
1361 stk5v5_board_init();
1363 printf("WARNING: Unsupported STK5 board rev.: %s\n",
1367 printf("WARNING: Unsupported baseboard: '%s'\n",
1375 gpio_set_value(TX53_RESET_OUT_GPIO, 1);
1380 int checkboard(void)
1382 tx53_print_cpuinfo();
1383 #if CONFIG_SYS_SDRAM_SIZE < SZ_1G
1384 printf("Board: Ka-Ro TX53-8%d3%c\n",
1385 is_lvds(), '0' + CONFIG_SYS_SDRAM_SIZE / SZ_1G);
1386 #elif CONFIG_SYS_SDRAM_SIZE < SZ_2G
1387 printf("Board: Ka-Ro TX53-1%d3%c\n",
1388 is_lvds() + 2, '0' + CONFIG_SYS_SDRAM_SIZE / SZ_1G);
1390 printf("Board: Ka-Ro TX53-123%c\n",
1391 '0' + CONFIG_SYS_SDRAM_SIZE / SZ_1G);
1396 #if defined(CONFIG_OF_BOARD_SETUP)
1397 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1398 #include <jffs2/jffs2.h>
1399 #include <mtd_node.h>
1400 static struct node_info nodes[] = {
1401 { "fsl,imx53-nand", MTD_DEV_TYPE_NAND, },
1404 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1407 #ifdef CONFIG_SYS_TX53_HWREV_2
1408 static void tx53_fixup_rtc(void *blob)
1410 karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupt-parent");
1411 karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupts");
1414 static inline void tx53_fixup_rtc(void *blob)
1417 #endif /* CONFIG_SYS_TX53_HWREV_2 */
1419 static const char *tx53_touchpanels[] = {
1425 int ft_board_setup(void *blob, bd_t *bd)
1427 const char *baseboard = getenv("baseboard");
1428 int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1429 const char *video_mode = karo_get_vmode(getenv("video_mode"));
1432 ret = fdt_increase_size(blob, 4096);
1434 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1438 karo_fdt_enable_node(blob, "stk5led", 0);
1440 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1441 fdt_fixup_ethernet(blob);
1443 karo_fdt_fixup_touchpanel(blob, tx53_touchpanels,
1444 ARRAY_SIZE(tx53_touchpanels));
1445 karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1446 karo_fdt_fixup_flexcan(blob, stk5_v5);
1447 tx53_fixup_rtc(blob);
1448 karo_fdt_update_fb_mode(blob, video_mode);
1452 #endif /* CONFIG_OF_BOARD_SETUP */