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1 /*
2  * Copyright (C) 2011-2013 Lothar Waßmann <LW@KARO-electronics.de>
3  * based on: board/freescale/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
4  *
5  * See file CREDITS for list of people who contributed to this
6  * project.
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License
10  * version 2 as published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  */
18
19 #include <common.h>
20 #include <errno.h>
21 #include <libfdt.h>
22 #include <fdt_support.h>
23 #include <i2c.h>
24 #include <lcd.h>
25 #include <netdev.h>
26 #include <mmc.h>
27 #include <fsl_esdhc.h>
28 #include <video_fb.h>
29 #include <ipu.h>
30 #include <mxcfb.h>
31 #include <linux/fb.h>
32 #include <asm/io.h>
33 #include <asm/gpio.h>
34 #include <asm/arch/iomux-mx53.h>
35 #include <asm/arch/clock.h>
36 #include <asm/arch/imx-regs.h>
37 #include <asm/arch/crm_regs.h>
38 #include <asm/arch/sys_proto.h>
39
40 #include "../common/karo.h"
41
42 #define TX53_FEC_RST_GPIO       IMX_GPIO_NR(7, 6)
43 #define TX53_FEC_PWR_GPIO       IMX_GPIO_NR(3, 20)
44 #define TX53_FEC_INT_GPIO       IMX_GPIO_NR(2, 4)
45 #define TX53_LED_GPIO           IMX_GPIO_NR(2, 20)
46
47 #define TX53_LCD_PWR_GPIO       IMX_GPIO_NR(2, 31)
48 #define TX53_LCD_RST_GPIO       IMX_GPIO_NR(3, 29)
49 #define TX53_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 1)
50
51 #define TX53_RESET_OUT_GPIO     IMX_GPIO_NR(7, 12)
52
53 DECLARE_GLOBAL_DATA_PTR;
54
55 #define MX53_GPIO_PAD_CTRL      MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_PUE | \
56                                 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP)
57
58 #define TX53_SDHC_PAD_CTRL      MUX_PAD_CTRL(PAD_CTL_HYS | PAD_CTL_DSE_HIGH |   \
59                                 PAD_CTL_SRE_FAST | PAD_CTL_PUS_47K_UP)
60
61 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
62
63 static iomux_v3_cfg_t tx53_pads[] = {
64         /* NAND flash pads are set up in lowlevel_init.S */
65
66         /* UART pads */
67 #if CONFIG_MXC_UART_BASE == UART1_BASE
68         MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
69         MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
70         MX53_PAD_PATA_IORDY__UART1_RTS,
71         MX53_PAD_PATA_RESET_B__UART1_CTS,
72 #endif
73 #if CONFIG_MXC_UART_BASE == UART2_BASE
74         MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
75         MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
76         MX53_PAD_PATA_DIOR__UART2_RTS,
77         MX53_PAD_PATA_INTRQ__UART2_CTS,
78 #endif
79 #if CONFIG_MXC_UART_BASE == UART3_BASE
80         MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
81         MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
82         MX53_PAD_PATA_DA_2__UART3_RTS,
83         MX53_PAD_PATA_DA_1__UART3_CTS,
84 #endif
85         /* internal I2C */
86         MX53_PAD_EIM_D28__I2C1_SDA | MX53_GPIO_PAD_CTRL,
87         MX53_PAD_EIM_D21__I2C1_SCL | MX53_GPIO_PAD_CTRL,
88
89         /* FEC PHY GPIO functions */
90         MX53_PAD_EIM_D20__GPIO3_20, /* PHY POWER */
91         MX53_PAD_PATA_DA_0__GPIO7_6, /* PHY RESET */
92         MX53_PAD_PATA_DATA4__GPIO2_4, /* PHY INT */
93
94         /* FEC functions */
95         MX53_PAD_FEC_MDC__FEC_MDC,
96         MX53_PAD_FEC_MDIO__FEC_MDIO,
97         MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
98         MX53_PAD_FEC_RX_ER__FEC_RX_ER,
99         MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
100         MX53_PAD_FEC_RXD1__FEC_RDATA_1,
101         MX53_PAD_FEC_RXD0__FEC_RDATA_0,
102         MX53_PAD_FEC_TX_EN__FEC_TX_EN,
103         MX53_PAD_FEC_TXD1__FEC_TDATA_1,
104         MX53_PAD_FEC_TXD0__FEC_TDATA_0,
105 };
106
107 static const struct gpio tx53_gpios[] = {
108         { TX53_RESET_OUT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "#RESET_OUT", },
109         { TX53_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
110         { TX53_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
111         { TX53_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
112 };
113
114 /*
115  * Functions
116  */
117 /* placed in section '.data' to prevent overwriting relocation info
118  * overlayed with bss
119  */
120 static u32 wrsr __attribute__((section(".data")));
121
122 #define WRSR_POR        (1 << 4)
123 #define WRSR_TOUT       (1 << 1)
124 #define WRSR_SFTW       (1 << 0)
125
126 static void print_reset_cause(void)
127 {
128         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
129         void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
130         u32 srsr;
131         char *dlm = "";
132
133         printf("Reset cause: ");
134
135         srsr = readl(&src_regs->srsr);
136         wrsr = readw(wdt_base + 4);
137
138         if (wrsr & WRSR_POR) {
139                 printf("%sPOR", dlm);
140                 dlm = " | ";
141         }
142         if (srsr & 0x00004) {
143                 printf("%sCSU", dlm);
144                 dlm = " | ";
145         }
146         if (srsr & 0x00008) {
147                 printf("%sIPP USER", dlm);
148                 dlm = " | ";
149         }
150         if (srsr & 0x00010) {
151                 if (wrsr & WRSR_SFTW) {
152                         printf("%sSOFT", dlm);
153                         dlm = " | ";
154                 }
155                 if (wrsr & WRSR_TOUT) {
156                         printf("%sWDOG", dlm);
157                         dlm = " | ";
158                 }
159         }
160         if (srsr & 0x00020) {
161                 printf("%sJTAG HIGH-Z", dlm);
162                 dlm = " | ";
163         }
164         if (srsr & 0x00040) {
165                 printf("%sJTAG SW", dlm);
166                 dlm = " | ";
167         }
168         if (srsr & 0x10000) {
169                 printf("%sWARM BOOT", dlm);
170                 dlm = " | ";
171         }
172         if (dlm[0] == '\0')
173                 printf("unknown");
174
175         printf("\n");
176 }
177
178 #define pr_lpgr_val(v, n, b, c) do {                                    \
179         u32 __v = ((v) >> (b)) & ((1 << (c)) - 1);                      \
180         if (__v)                                                        \
181                 printf(" %s=%0*x", #n, DIV_ROUND_UP(c, 4), __v);        \
182 } while (0)
183
184 static inline void print_lpgr(u32 lpgr)
185 {
186         if (!lpgr)
187                 return;
188
189         printf("LPGR=%08x:", lpgr);
190         pr_lpgr_val(lpgr, SW_ISO, 31, 1);
191         pr_lpgr_val(lpgr, SECONDARY_BOOT, 30, 1);
192         pr_lpgr_val(lpgr, BLOCK_REWRITE, 29, 1);
193         pr_lpgr_val(lpgr, WDOG_BOOT, 28, 1);
194         pr_lpgr_val(lpgr, SBMR_SHADOW, 0, 26);
195         printf("\n");
196 }
197
198 static void tx53_print_cpuinfo(void)
199 {
200         u32 cpurev;
201         struct srtc_regs *srtc_regs = (void *)SRTC_BASE_ADDR;
202         u32 lpgr = readl(&srtc_regs->lpgr);
203
204         cpurev = get_cpu_rev();
205
206         printf("CPU:   Freescale i.MX53 rev%d.%d at %d MHz\n",
207                 (cpurev & 0x000F0) >> 4,
208                 (cpurev & 0x0000F) >> 0,
209                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
210
211         print_reset_cause();
212
213         print_lpgr(lpgr);
214
215         if (lpgr & (1 << 30))
216                 printf("WARNING: U-Boot started from secondary bootstrap image\n");
217
218         if (lpgr) {
219                 struct mxc_ccm_reg *ccm_regs = (void *)CCM_BASE_ADDR;
220                 u32 ccgr4 = readl(&ccm_regs->CCGR4);
221
222                 writel(ccgr4 | MXC_CCM_CCGR4_SRTC(3), &ccm_regs->CCGR4);
223                 writel(0, &srtc_regs->lpgr);
224                 writel(ccgr4, &ccm_regs->CCGR4);
225         }
226 }
227
228 enum LTC3589_REGS {
229         LTC3589_SCR1 = 0x07,
230         LTC3589_SCR2 = 0x12,
231         LTC3589_VCCR = 0x20,
232         LTC3589_CLIRQ = 0x21,
233         LTC3589_B1DTV1 = 0x23,
234         LTC3589_B1DTV2 = 0x24,
235         LTC3589_VRRCR = 0x25,
236         LTC3589_B2DTV1 = 0x26,
237         LTC3589_B2DTV2 = 0x27,
238         LTC3589_B3DTV1 = 0x29,
239         LTC3589_B3DTV2 = 0x2a,
240         LTC3589_L2DTV1 = 0x32,
241         LTC3589_L2DTV2 = 0x33,
242 };
243
244 #define LTC3589_BnDTV1_PGOOD_MASK       (1 << 5)
245 #define LTC3589_BnDTV1_SLEW(n)          (((n) & 3) << 6)
246
247 #define LTC3589_CLK_RATE_LOW            (1 << 5)
248
249 #define LTC3589_SCR2_PGOOD_SHUTDWN      (1 << 7)
250
251 #define VDD_LDO2_VAL            mV_to_regval(vout_to_vref(1325 * 10, 2))
252 #define VDD_CORE_VAL            mV_to_regval(vout_to_vref(1100 * 10, 3))
253 #define VDD_SOC_VAL             mV_to_regval(vout_to_vref(1325 * 10, 4))
254 #define VDD_BUCK3_VAL           mV_to_regval(vout_to_vref(2500 * 10, 5))
255
256 #ifndef CONFIG_SYS_TX53_HWREV_2
257 /* LDO2 vref divider */
258 #define R1_2    180
259 #define R2_2    191
260 /* BUCK1 vref divider */
261 #define R1_3    150
262 #define R2_3    180
263 /* BUCK2 vref divider */
264 #define R1_4    180
265 #define R2_4    191
266 /* BUCK3 vref divider */
267 #define R1_5    270
268 #define R2_5    100
269 #else
270 /* no dividers on vref */
271 #define R1_2    0
272 #define R2_2    1
273 #define R1_3    0
274 #define R2_3    1
275 #define R1_4    0
276 #define R2_4    1
277 #define R1_5    0
278 #define R2_5    1
279 #endif
280
281 /* calculate voltages in 10mV */
282 #define R1(idx)                 R1_##idx
283 #define R2(idx)                 R2_##idx
284
285 #define vout_to_vref(vout, idx) ((vout) * R2(idx) / (R1(idx) + R2(idx)))
286 #define vref_to_vout(vref, idx) DIV_ROUND_UP((vref) * (R1(idx) + R2(idx)), R2(idx))
287
288 #define mV_to_regval(mV)        DIV_ROUND(((((mV) < 3625) ? 3625 : (mV)) - 3625), 125)
289 #define regval_to_mV(v)         (((v) * 125 + 3625))
290
291 static struct pmic_regs {
292         enum LTC3589_REGS addr;
293         u8 val;
294 } ltc3589_regs[] = {
295         { LTC3589_SCR1, 0x15, }, /* burst mode for all regulators except buck boost */
296         { LTC3589_SCR2, LTC3589_SCR2_PGOOD_SHUTDWN, }, /* enable shutdown on PGOOD Timeout */
297
298         { LTC3589_L2DTV1, VDD_LDO2_VAL | LTC3589_BnDTV1_SLEW(3) | LTC3589_BnDTV1_PGOOD_MASK, },
299         { LTC3589_L2DTV2, VDD_LDO2_VAL | LTC3589_CLK_RATE_LOW, },
300
301         { LTC3589_B1DTV1, VDD_CORE_VAL | LTC3589_BnDTV1_SLEW(3) | LTC3589_BnDTV1_PGOOD_MASK, },
302         { LTC3589_B1DTV2, VDD_CORE_VAL, },
303
304         { LTC3589_B2DTV1, VDD_SOC_VAL | LTC3589_BnDTV1_SLEW(3) | LTC3589_BnDTV1_PGOOD_MASK, },
305         { LTC3589_B2DTV2, VDD_SOC_VAL, },
306
307         { LTC3589_B3DTV1, VDD_BUCK3_VAL | LTC3589_BnDTV1_SLEW(3) | LTC3589_BnDTV1_PGOOD_MASK, },
308         { LTC3589_B3DTV2, VDD_BUCK3_VAL, },
309
310         /* Select ref 0 for all regulators and enable slew */
311         { LTC3589_VCCR, 0x55, },
312
313         { LTC3589_CLIRQ, 0, }, /* clear all interrupt flags */
314 };
315
316 static int setup_pmic_voltages(void)
317 {
318         int ret;
319         unsigned char value;
320         int i;
321
322         ret = i2c_probe(CONFIG_SYS_I2C_SLAVE);
323         if (ret != 0) {
324                 printf("Failed to initialize I2C\n");
325                 return ret;
326         }
327
328         ret = i2c_read(CONFIG_SYS_I2C_SLAVE, 0x11, 1, &value, 1);
329         if (ret) {
330                 printf("%s: i2c_read error: %d\n", __func__, ret);
331                 return ret;
332         }
333
334         for (i = 0; i < ARRAY_SIZE(ltc3589_regs); i++) {
335                 ret = i2c_read(CONFIG_SYS_I2C_SLAVE, ltc3589_regs[i].addr, 1,
336                                 &value, 1);
337                 debug("Writing %02x to reg %02x (%02x)\n",
338                         ltc3589_regs[i].val, ltc3589_regs[i].addr, value);
339                 ret = i2c_write(CONFIG_SYS_I2C_SLAVE, ltc3589_regs[i].addr, 1,
340                                 &ltc3589_regs[i].val, 1);
341                 if (ret) {
342                         printf("%s: failed to write PMIC register %02x: %d\n",
343                                 __func__, ltc3589_regs[i].addr, ret);
344                         return ret;
345                 }
346         }
347         printf("VDDCORE set to %umV\n",
348                 DIV_ROUND(vref_to_vout(regval_to_mV(VDD_CORE_VAL), 3), 10));
349
350         printf("VDDSOC  set to %umV\n",
351                 DIV_ROUND(vref_to_vout(regval_to_mV(VDD_SOC_VAL), 4), 10));
352         return 0;
353 }
354
355 static struct {
356         u32 max_freq;
357         u32 mV;
358 } tx53_core_voltages[] = {
359         { 800000000, 1100, },
360         { 1000000000, 1240, },
361         { 1200000000, 1350, },
362 };
363
364 int adjust_core_voltage(u32 freq)
365 {
366         int ret;
367         int i;
368
369         printf("%s@%d\n", __func__, __LINE__);
370
371         for (i = 0; i < ARRAY_SIZE(tx53_core_voltages); i++) {
372                 if (freq <= tx53_core_voltages[i].max_freq) {
373                         int retries = 0;
374                         const int max_tries = 10;
375                         const int delay_us = 1;
376                         u32 mV = tx53_core_voltages[i].mV;
377                         u8 val = mV_to_regval(vout_to_vref(mV * 10, 3));
378                         u8 v;
379
380                         debug("regval[%umV]=%02x\n", mV, val);
381
382                         ret = i2c_read(CONFIG_SYS_I2C_SLAVE, LTC3589_B1DTV1, 1,
383                                 &v, 1);
384                         if (ret) {
385                                 printf("%s: failed to read PMIC register %02x: %d\n",
386                                         __func__, LTC3589_B1DTV1, ret);
387                                 return ret;
388                         }
389                         debug("Changing reg %02x from %02x to %02x\n",
390                                 LTC3589_B1DTV1, v, (v & ~0x1f) |
391                                 mV_to_regval(vout_to_vref(mV * 10, 3)));
392                         v &= ~0x1f;
393                         v |= mV_to_regval(vout_to_vref(mV * 10, 3));
394                         ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3589_B1DTV1, 1,
395                                         &v, 1);
396                         if (ret) {
397                                 printf("%s: failed to write PMIC register %02x: %d\n",
398                                         __func__, LTC3589_B1DTV1, ret);
399                                 return ret;
400                         }
401                         ret = i2c_read(CONFIG_SYS_I2C_SLAVE, LTC3589_VCCR, 1,
402                                         &v, 1);
403                         if (ret) {
404                                 printf("%s: failed to read PMIC register %02x: %d\n",
405                                         __func__, LTC3589_VCCR, ret);
406                                 return ret;
407                         }
408                         v |= 0x1;
409                         ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3589_VCCR, 1,
410                                         &v, 1);
411                         if (ret) {
412                                 printf("%s: failed to write PMIC register %02x: %d\n",
413                                         __func__, LTC3589_VCCR, ret);
414                                 return ret;
415                         }
416                         for (retries = 0; retries < max_tries; retries++) {
417                                 ret = i2c_read(CONFIG_SYS_I2C_SLAVE,
418                                         LTC3589_VCCR, 1, &v, 1);
419                                 if (ret) {
420                                         printf("%s: failed to read PMIC register %02x: %d\n",
421                                                 __func__, LTC3589_VCCR, ret);
422                                         return ret;
423                                 }
424                                 if (!(v & 1))
425                                         break;
426                                 udelay(delay_us);
427                         }
428                         if (v & 1) {
429                                 printf("change of VDDCORE did not complete after %uµs\n",
430                                         retries * delay_us);
431                                 return -ETIMEDOUT;
432                         }
433
434                         printf("VDDCORE set to %umV after %u loops\n",
435                                 DIV_ROUND(vref_to_vout(regval_to_mV(val & 0x1f), 3),
436                                         10), retries);
437                         return 0;
438                 }
439         }
440         return -EINVAL;
441 }
442
443 int board_early_init_f(void)
444 {
445         struct mxc_ccm_reg *ccm_regs = (void *)CCM_BASE_ADDR;
446
447         gpio_request_array(tx53_gpios, ARRAY_SIZE(tx53_gpios));
448         imx_iomux_v3_setup_multiple_pads(tx53_pads, ARRAY_SIZE(tx53_pads));
449
450         writel(0x77777777, AIPS1_BASE_ADDR + 0x00);
451         writel(0x77777777, AIPS1_BASE_ADDR + 0x04);
452
453         writel(0x00000000, AIPS1_BASE_ADDR + 0x40);
454         writel(0x00000000, AIPS1_BASE_ADDR + 0x44);
455         writel(0x00000000, AIPS1_BASE_ADDR + 0x48);
456         writel(0x00000000, AIPS1_BASE_ADDR + 0x4c);
457         writel(0x00000000, AIPS1_BASE_ADDR + 0x50);
458
459         writel(0x77777777, AIPS2_BASE_ADDR + 0x00);
460         writel(0x77777777, AIPS2_BASE_ADDR + 0x04);
461
462         writel(0x00000000, AIPS2_BASE_ADDR + 0x40);
463         writel(0x00000000, AIPS2_BASE_ADDR + 0x44);
464         writel(0x00000000, AIPS2_BASE_ADDR + 0x48);
465         writel(0x00000000, AIPS2_BASE_ADDR + 0x4c);
466         writel(0x00000000, AIPS2_BASE_ADDR + 0x50);
467
468         writel(0xffcf0fff, &ccm_regs->CCGR0);
469         writel(0x000fffcf, &ccm_regs->CCGR1);
470         writel(0x033c0000, &ccm_regs->CCGR2);
471         writel(0x000000ff, &ccm_regs->CCGR3);
472         writel(0x00000000, &ccm_regs->CCGR4);
473         writel(0x00fff033, &ccm_regs->CCGR5);
474         writel(0x0f00030f, &ccm_regs->CCGR6);
475         writel(0xfff00000, &ccm_regs->CCGR7);
476         writel(0x00000000, &ccm_regs->cmeor);
477
478         return 0;
479 }
480
481 int board_init(void)
482 {
483         int ret;
484
485         /* Address of boot parameters */
486         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
487
488         if (ctrlc() || (wrsr & WRSR_TOUT)) {
489                 if (wrsr & WRSR_TOUT)
490                         printf("WDOG RESET detected; Skipping PMIC setup\n");
491                 else
492                         printf("<CTRL-C> detected; safeboot enabled\n");
493                 return 1;
494         }
495
496         ret = setup_pmic_voltages();
497         if (ret) {
498                 printf("Failed to setup PMIC voltages\n");
499                 hang();
500         }
501         return 0;
502 }
503
504 int dram_init(void)
505 {
506         int ret;
507
508         /*
509          * U-Boot doesn't support RAM banks with intervening holes,
510          * so let U-Boot only know about the first bank for its
511          * internal data structures. The size reported to Linux is
512          * determined from the individual bank sizes.
513          */
514         gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, SZ_1G);
515
516         ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK,
517                 CONFIG_SYS_SDRAM_CLK, MXC_DDR_CLK);
518         if (ret)
519                 printf("%s: Failed to set DDR clock to %u MHz: %d\n", __func__,
520                         CONFIG_SYS_SDRAM_CLK, ret);
521         else
522                 debug("%s: DDR clock set to %u.%03u MHz (desig.: %u.000 MHz)\n",
523                         __func__, mxc_get_clock(MXC_DDR_CLK) / 1000000,
524                         mxc_get_clock(MXC_DDR_CLK) / 1000 % 1000,
525                         CONFIG_SYS_SDRAM_CLK);
526         return ret;
527 }
528
529 void dram_init_banksize(void)
530 {
531         long total_size = gd->ram_size;
532
533         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
534         gd->bd->bi_dram[0].size = gd->ram_size;
535
536 #if CONFIG_NR_DRAM_BANKS > 1
537         gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, SZ_1G);
538
539         if (gd->bd->bi_dram[1].size) {
540                 debug("Found %luMiB SDRAM in bank 2\n",
541                         gd->bd->bi_dram[1].size / SZ_1M);
542                 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
543                 total_size += gd->bd->bi_dram[1].size;
544         }
545 #endif
546         if (total_size != CONFIG_SYS_SDRAM_SIZE)
547                 printf("WARNING: SDRAM size mismatch: %uMiB configured; %luMiB detected\n",
548                         CONFIG_SYS_SDRAM_SIZE / SZ_1M, total_size / SZ_1M);
549 }
550
551 #ifdef  CONFIG_CMD_MMC
552 static const iomux_v3_cfg_t mmc0_pads[] = {
553         MX53_PAD_SD1_CMD__ESDHC1_CMD | TX53_SDHC_PAD_CTRL,
554         MX53_PAD_SD1_CLK__ESDHC1_CLK | TX53_SDHC_PAD_CTRL,
555         MX53_PAD_SD1_DATA0__ESDHC1_DAT0 | TX53_SDHC_PAD_CTRL,
556         MX53_PAD_SD1_DATA1__ESDHC1_DAT1 | TX53_SDHC_PAD_CTRL,
557         MX53_PAD_SD1_DATA2__ESDHC1_DAT2 | TX53_SDHC_PAD_CTRL,
558         MX53_PAD_SD1_DATA3__ESDHC1_DAT3 | TX53_SDHC_PAD_CTRL,
559         /* SD1 CD */
560         MX53_PAD_EIM_D24__GPIO3_24 | MX53_GPIO_PAD_CTRL,
561 };
562
563 static const iomux_v3_cfg_t mmc1_pads[] = {
564         MX53_PAD_SD2_CMD__ESDHC2_CMD | TX53_SDHC_PAD_CTRL,
565         MX53_PAD_SD2_CLK__ESDHC2_CLK | TX53_SDHC_PAD_CTRL,
566         MX53_PAD_SD2_DATA0__ESDHC2_DAT0 | TX53_SDHC_PAD_CTRL,
567         MX53_PAD_SD2_DATA1__ESDHC2_DAT1 | TX53_SDHC_PAD_CTRL,
568         MX53_PAD_SD2_DATA2__ESDHC2_DAT2 | TX53_SDHC_PAD_CTRL,
569         MX53_PAD_SD2_DATA3__ESDHC2_DAT3 | TX53_SDHC_PAD_CTRL,
570         /* SD2 CD */
571         MX53_PAD_EIM_D25__GPIO3_25 | MX53_GPIO_PAD_CTRL,
572 };
573
574 static struct tx53_esdhc_cfg {
575         const iomux_v3_cfg_t *pads;
576         int num_pads;
577         struct fsl_esdhc_cfg cfg;
578         int cd_gpio;
579 } tx53_esdhc_cfg[] = {
580         {
581                 .pads = mmc0_pads,
582                 .num_pads = ARRAY_SIZE(mmc0_pads),
583                 .cfg = {
584                         .esdhc_base = (void __iomem *)MMC_SDHC1_BASE_ADDR,
585                         .max_bus_width = 4,
586                 },
587                 .cd_gpio = IMX_GPIO_NR(3, 24),
588         },
589         {
590                 .pads = mmc1_pads,
591                 .num_pads = ARRAY_SIZE(mmc1_pads),
592                 .cfg = {
593                         .esdhc_base = (void __iomem *)MMC_SDHC2_BASE_ADDR,
594                         .max_bus_width = 4,
595                 },
596                 .cd_gpio = IMX_GPIO_NR(3, 25),
597         },
598 };
599
600 static inline struct tx53_esdhc_cfg *to_tx53_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
601 {
602         return container_of(cfg, struct tx53_esdhc_cfg, cfg);
603 }
604
605 int board_mmc_getcd(struct mmc *mmc)
606 {
607         struct tx53_esdhc_cfg *cfg = to_tx53_esdhc_cfg(mmc->priv);
608
609         if (cfg->cd_gpio < 0)
610                 return cfg->cd_gpio;
611
612         debug("SD card %d is %spresent\n",
613                 cfg - tx53_esdhc_cfg,
614                 gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
615         return !gpio_get_value(cfg->cd_gpio);
616 }
617
618 int board_mmc_init(bd_t *bis)
619 {
620         int i;
621
622         for (i = 0; i < ARRAY_SIZE(tx53_esdhc_cfg); i++) {
623                 struct mmc *mmc;
624                 struct tx53_esdhc_cfg *cfg = &tx53_esdhc_cfg[i];
625                 int ret;
626
627                 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
628                 cfg->cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
629
630                 ret = gpio_request_one(cfg->cd_gpio,
631                                 GPIOFLAG_INPUT, "MMC CD");
632                 if (ret) {
633                         printf("Error %d requesting GPIO%d_%d\n",
634                                 ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
635                         continue;
636                 }
637
638                 debug("%s: Initializing MMC slot %d\n", __func__, i);
639                 fsl_esdhc_initialize(bis, &cfg->cfg);
640
641                 mmc = find_mmc_device(i);
642                 if (mmc == NULL)
643                         continue;
644                 if (board_mmc_getcd(mmc) > 0)
645                         mmc_init(mmc);
646         }
647         return 0;
648 }
649 #endif /* CONFIG_CMD_MMC */
650
651 #ifdef CONFIG_FEC_MXC
652
653 #ifndef ETH_ALEN
654 #define ETH_ALEN 6
655 #endif
656
657 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
658 {
659         int i;
660         struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
661         struct fuse_bank *bank = &iim->bank[1];
662         struct fuse_bank1_regs *fuse = (struct fuse_bank1_regs *)bank->fuse_regs;
663
664         if (dev_id > 0)
665                 return;
666
667         for (i = 0; i < ETH_ALEN; i++)
668                 mac[i] = readl(&fuse->mac_addr[i]);
669 }
670
671 #define FEC_PAD_CTL     (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
672                         PAD_CTL_SRE_FAST)
673 #define FEC_PAD_CTL2    (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
674 #define GPIO_PAD_CTL    (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
675
676 int board_eth_init(bd_t *bis)
677 {
678         int ret;
679
680         /* delay at least 21ms for the PHY internal POR signal to deassert */
681         udelay(22000);
682
683         /* Deassert RESET to the external phy */
684         gpio_set_value(TX53_FEC_RST_GPIO, 1);
685
686         ret = cpu_eth_init(bis);
687         if (ret)
688                 printf("cpu_eth_init() failed: %d\n", ret);
689
690         return ret;
691 }
692 #endif /* CONFIG_FEC_MXC */
693
694 enum {
695         LED_STATE_INIT = -1,
696         LED_STATE_OFF,
697         LED_STATE_ON,
698 };
699
700 void show_activity(int arg)
701 {
702         static int led_state = LED_STATE_INIT;
703         static ulong last;
704
705         if (led_state == LED_STATE_INIT) {
706                 last = get_timer(0);
707                 gpio_set_value(TX53_LED_GPIO, 1);
708                 led_state = LED_STATE_ON;
709         } else {
710                 if (get_timer(last) > CONFIG_SYS_HZ) {
711                         last = get_timer(0);
712                         if (led_state == LED_STATE_ON) {
713                                 gpio_set_value(TX53_LED_GPIO, 0);
714                         } else {
715                                 gpio_set_value(TX53_LED_GPIO, 1);
716                         }
717                         led_state = 1 - led_state;
718                 }
719         }
720 }
721
722 static const iomux_v3_cfg_t stk5_pads[] = {
723         /* SW controlled LED on STK5 baseboard */
724         MX53_PAD_EIM_A18__GPIO2_20,
725
726         /* I2C bus on DIMM pins 40/41 */
727         MX53_PAD_GPIO_6__I2C3_SDA | MX53_GPIO_PAD_CTRL,
728         MX53_PAD_GPIO_3__I2C3_SCL | MX53_GPIO_PAD_CTRL,
729
730         /* TSC200x PEN IRQ */
731         MX53_PAD_EIM_D26__GPIO3_26 | MX53_GPIO_PAD_CTRL,
732
733         /* EDT-FT5x06 Polytouch panel */
734         MX53_PAD_NANDF_CS2__GPIO6_15 | MX53_GPIO_PAD_CTRL, /* IRQ */
735         MX53_PAD_EIM_A16__GPIO2_22 | MX53_GPIO_PAD_CTRL, /* RESET */
736         MX53_PAD_EIM_A17__GPIO2_21 | MX53_GPIO_PAD_CTRL, /* WAKE */
737
738         /* USBH1 */
739         MX53_PAD_EIM_D31__GPIO3_31 | MX53_GPIO_PAD_CTRL, /* VBUSEN */
740         MX53_PAD_EIM_D30__GPIO3_30 | MX53_GPIO_PAD_CTRL, /* OC */
741         /* USBOTG */
742         MX53_PAD_GPIO_7__GPIO1_7, /* VBUSEN */
743         MX53_PAD_GPIO_8__GPIO1_8, /* OC */
744
745         /* DS1339 Interrupt */
746         MX53_PAD_DI0_PIN4__GPIO4_20 | MX53_GPIO_PAD_CTRL,
747 };
748
749 static const struct gpio stk5_gpios[] = {
750         { TX53_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
751
752         { IMX_GPIO_NR(1, 8), GPIOFLAG_INPUT, "USBOTG OC", },
753         { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
754         { IMX_GPIO_NR(3, 30), GPIOFLAG_INPUT, "USBH1 OC", },
755         { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
756 };
757
758 #ifdef CONFIG_LCD
759 static u16 tx53_cmap[256];
760 vidinfo_t panel_info = {
761         /* set to max. size supported by SoC */
762         .vl_col = 1600,
763         .vl_row = 1200,
764
765         .vl_bpix = LCD_COLOR32,    /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
766         .cmap = tx53_cmap,
767 };
768
769 static struct fb_videomode tx53_fb_modes[] = {
770 #ifndef CONFIG_SYS_LVDS_IF
771         {
772                 /* Standard VGA timing */
773                 .name           = "VGA",
774                 .refresh        = 60,
775                 .xres           = 640,
776                 .yres           = 480,
777                 .pixclock       = KHZ2PICOS(25175),
778                 .left_margin    = 48,
779                 .hsync_len      = 96,
780                 .right_margin   = 16,
781                 .upper_margin   = 31,
782                 .vsync_len      = 2,
783                 .lower_margin   = 12,
784                 .sync           = FB_SYNC_CLK_LAT_FALL,
785         },
786         {
787                 /* Emerging ETV570 640 x 480 display. Syncs low active,
788                  * DE high active, 115.2 mm x 86.4 mm display area
789                  * VGA compatible timing
790                  */
791                 .name           = "ETV570",
792                 .refresh        = 60,
793                 .xres           = 640,
794                 .yres           = 480,
795                 .pixclock       = KHZ2PICOS(25175),
796                 .left_margin    = 114,
797                 .hsync_len      = 30,
798                 .right_margin   = 16,
799                 .upper_margin   = 32,
800                 .vsync_len      = 3,
801                 .lower_margin   = 10,
802                 .sync           = FB_SYNC_CLK_LAT_FALL,
803         },
804         {
805                 /* Emerging ET0350G0DH6 320 x 240 display.
806                  * 70.08 mm x 52.56 mm display area.
807                  */
808                 .name           = "ET0350",
809                 .refresh        = 60,
810                 .xres           = 320,
811                 .yres           = 240,
812                 .pixclock       = KHZ2PICOS(6500),
813                 .left_margin    = 68 - 34,
814                 .hsync_len      = 34,
815                 .right_margin   = 20,
816                 .upper_margin   = 18 - 3,
817                 .vsync_len      = 3,
818                 .lower_margin   = 4,
819                 .sync           = FB_SYNC_CLK_LAT_FALL,
820         },
821         {
822                 /* Emerging ET0430G0DH6 480 x 272 display.
823                  * 95.04 mm x 53.856 mm display area.
824                  */
825                 .name           = "ET0430",
826                 .refresh        = 60,
827                 .xres           = 480,
828                 .yres           = 272,
829                 .pixclock       = KHZ2PICOS(9000),
830                 .left_margin    = 2,
831                 .hsync_len      = 41,
832                 .right_margin   = 2,
833                 .upper_margin   = 2,
834                 .vsync_len      = 10,
835                 .lower_margin   = 2,
836                 .sync           = FB_SYNC_CLK_LAT_FALL,
837         },
838         {
839                 /* Emerging ET0500G0DH6 800 x 480 display.
840                  * 109.6 mm x 66.4 mm display area.
841                  */
842                 .name           = "ET0500",
843                 .refresh        = 60,
844                 .xres           = 800,
845                 .yres           = 480,
846                 .pixclock       = KHZ2PICOS(33260),
847                 .left_margin    = 216 - 128,
848                 .hsync_len      = 128,
849                 .right_margin   = 1056 - 800 - 216,
850                 .upper_margin   = 35 - 2,
851                 .vsync_len      = 2,
852                 .lower_margin   = 525 - 480 - 35,
853                 .sync           = FB_SYNC_CLK_LAT_FALL,
854         },
855         {
856                 /* Emerging ETQ570G0DH6 320 x 240 display.
857                  * 115.2 mm x 86.4 mm display area.
858                  */
859                 .name           = "ETQ570",
860                 .refresh        = 60,
861                 .xres           = 320,
862                 .yres           = 240,
863                 .pixclock       = KHZ2PICOS(6400),
864                 .left_margin    = 38,
865                 .hsync_len      = 30,
866                 .right_margin   = 30,
867                 .upper_margin   = 16, /* 15 according to datasheet */
868                 .vsync_len      = 3, /* TVP -> 1>x>5 */
869                 .lower_margin   = 4, /* 4.5 according to datasheet */
870                 .sync           = FB_SYNC_CLK_LAT_FALL,
871         },
872         {
873                 /* Emerging ET0700G0DH6 800 x 480 display.
874                  * 152.4 mm x 91.44 mm display area.
875                  */
876                 .name           = "ET0700",
877                 .refresh        = 60,
878                 .xres           = 800,
879                 .yres           = 480,
880                 .pixclock       = KHZ2PICOS(33260),
881                 .left_margin    = 216 - 128,
882                 .hsync_len      = 128,
883                 .right_margin   = 1056 - 800 - 216,
884                 .upper_margin   = 35 - 2,
885                 .vsync_len      = 2,
886                 .lower_margin   = 525 - 480 - 35,
887                 .sync           = FB_SYNC_CLK_LAT_FALL,
888         },
889 #else
890         {
891                 /* HannStar HSD100PXN1
892                  * 202.7m mm x 152.06 mm display area.
893                  */
894                 .name           = "HSD100PXN1",
895                 .refresh        = 60,
896                 .xres           = 1024,
897                 .yres           = 768,
898                 .pixclock       = KHZ2PICOS(65000),
899                 .left_margin    = 0,
900                 .hsync_len      = 0,
901                 .right_margin   = 320,
902                 .upper_margin   = 0,
903                 .vsync_len      = 0,
904                 .lower_margin   = 38,
905                 .sync           = FB_SYNC_CLK_LAT_FALL,
906         },
907 #endif
908         {
909                 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
910                 .refresh        = 60,
911                 .left_margin    = 48,
912                 .hsync_len      = 96,
913                 .right_margin   = 16,
914                 .upper_margin   = 31,
915                 .vsync_len      = 2,
916                 .lower_margin   = 12,
917                 .sync           = FB_SYNC_CLK_LAT_FALL,
918         },
919 };
920
921 static int lcd_enabled = 1;
922 static int lcd_bl_polarity;
923
924 static int lcd_backlight_polarity(void)
925 {
926         return lcd_bl_polarity;
927 }
928
929 void lcd_enable(void)
930 {
931         /* HACK ALERT:
932          * global variable from common/lcd.c
933          * Set to 0 here to prevent messages from going to LCD
934          * rather than serial console
935          */
936         lcd_is_enabled = 0;
937
938         if (lcd_enabled) {
939                 karo_load_splashimage(1);
940
941                 debug("Switching LCD on\n");
942                 gpio_set_value(TX53_LCD_PWR_GPIO, 1);
943                 udelay(100);
944                 gpio_set_value(TX53_LCD_RST_GPIO, 1);
945                 udelay(300000);
946                 gpio_set_value(TX53_LCD_BACKLIGHT_GPIO,
947                         lcd_backlight_polarity());
948         }
949 }
950
951 void lcd_disable(void)
952 {
953         if (lcd_enabled) {
954                 printf("Disabling LCD\n");
955                 ipuv3_fb_shutdown();
956         }
957 }
958
959 void lcd_panel_disable(void)
960 {
961         if (lcd_enabled) {
962                 debug("Switching LCD off\n");
963                 gpio_set_value(TX53_LCD_BACKLIGHT_GPIO,
964                         !lcd_backlight_polarity());
965                 gpio_set_value(TX53_LCD_RST_GPIO, 0);
966                 gpio_set_value(TX53_LCD_PWR_GPIO, 0);
967         }
968 }
969
970 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
971         /* LCD RESET */
972         MX53_PAD_EIM_D29__GPIO3_29 | MX53_GPIO_PAD_CTRL,
973         /* LCD POWER_ENABLE */
974         MX53_PAD_EIM_EB3__GPIO2_31 | MX53_GPIO_PAD_CTRL,
975         /* LCD Backlight (PWM) */
976         MX53_PAD_GPIO_1__GPIO1_1 | MX53_GPIO_PAD_CTRL,
977
978         /* Display */
979 #ifndef CONFIG_SYS_LVDS_IF
980         /* LCD option */
981         MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
982         MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
983         MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
984         MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
985         MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
986         MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
987         MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
988         MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
989         MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
990         MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
991         MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
992         MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
993         MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
994         MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
995         MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
996         MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
997         MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
998         MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
999         MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
1000         MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
1001         MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
1002         MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
1003         MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
1004         MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
1005         MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
1006         MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
1007         MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
1008         MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
1009 #else
1010         /* LVDS option */
1011         MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3,
1012         MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2,
1013         MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK,
1014         MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1,
1015         MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0,
1016         MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
1017         MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
1018         MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
1019         MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
1020         MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
1021 #endif
1022 };
1023
1024 static const struct gpio stk5_lcd_gpios[] = {
1025         { TX53_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
1026         { TX53_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
1027         { TX53_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
1028 };
1029
1030 void lcd_ctrl_init(void *lcdbase)
1031 {
1032         int color_depth = 24;
1033         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1034         const char *vm;
1035         unsigned long val;
1036         int refresh = 60;
1037         struct fb_videomode *p = &tx53_fb_modes[0];
1038         struct fb_videomode fb_mode;
1039         int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
1040         int pix_fmt;
1041         int lcd_bus_width;
1042         ipu_di_clk_parent_t di_clk_parent = is_lvds() ? DI_PCLK_LDB : DI_PCLK_PLL3;
1043         unsigned long di_clk_rate = 65000000;
1044
1045         if (!lcd_enabled) {
1046                 debug("LCD disabled\n");
1047                 return;
1048         }
1049
1050         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1051                 debug("Disabling LCD\n");
1052                 lcd_enabled = 0;
1053                 setenv("splashimage", NULL);
1054                 return;
1055         }
1056
1057         karo_fdt_move_fdt();
1058         lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1059
1060         if (video_mode == NULL) {
1061                 debug("Disabling LCD\n");
1062                 lcd_enabled = 0;
1063                 return;
1064         }
1065         vm = video_mode;
1066         if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1067                 p = &fb_mode;
1068                 debug("Using video mode from FDT\n");
1069                 vm += strlen(vm);
1070                 if (fb_mode.xres > panel_info.vl_col ||
1071                         fb_mode.yres > panel_info.vl_row) {
1072                         printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1073                                 fb_mode.xres, fb_mode.yres,
1074                                 panel_info.vl_col, panel_info.vl_row);
1075                         lcd_enabled = 0;
1076                         return;
1077                 }
1078         }
1079         if (p->name != NULL)
1080                 debug("Trying compiled-in video modes\n");
1081         while (p->name != NULL) {
1082                 if (strcmp(p->name, vm) == 0) {
1083                         debug("Using video mode: '%s'\n", p->name);
1084                         vm += strlen(vm);
1085                         break;
1086                 }
1087                 p++;
1088         }
1089         if (*vm != '\0')
1090                 debug("Trying to decode video_mode: '%s'\n", vm);
1091         while (*vm != '\0') {
1092                 if (*vm >= '0' && *vm <= '9') {
1093                         char *end;
1094
1095                         val = simple_strtoul(vm, &end, 0);
1096                         if (end > vm) {
1097                                 if (!xres_set) {
1098                                         if (val > panel_info.vl_col)
1099                                                 val = panel_info.vl_col;
1100                                         p->xres = val;
1101                                         panel_info.vl_col = val;
1102                                         xres_set = 1;
1103                                 } else if (!yres_set) {
1104                                         if (val > panel_info.vl_row)
1105                                                 val = panel_info.vl_row;
1106                                         p->yres = val;
1107                                         panel_info.vl_row = val;
1108                                         yres_set = 1;
1109                                 } else if (!bpp_set) {
1110                                         switch (val) {
1111                                         case 32:
1112                                         case 24:
1113                                                 if (is_lvds())
1114                                                         pix_fmt = IPU_PIX_FMT_LVDS888;
1115                                                 /* fallthru */
1116                                         case 16:
1117                                         case 8:
1118                                                 color_depth = val;
1119                                                 break;
1120
1121                                         case 18:
1122                                                 if (is_lvds()) {
1123                                                         color_depth = val;
1124                                                         break;
1125                                                 }
1126                                                 /* fallthru */
1127                                         default:
1128                                                 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1129                                                         end - vm, vm, color_depth);
1130                                         }
1131                                         bpp_set = 1;
1132                                 } else if (!refresh_set) {
1133                                         refresh = val;
1134                                         refresh_set = 1;
1135                                 }
1136                         }
1137                         vm = end;
1138                 }
1139                 switch (*vm) {
1140                 case '@':
1141                         bpp_set = 1;
1142                         /* fallthru */
1143                 case '-':
1144                         yres_set = 1;
1145                         /* fallthru */
1146                 case 'x':
1147                         xres_set = 1;
1148                         /* fallthru */
1149                 case 'M':
1150                 case 'R':
1151                         vm++;
1152                         break;
1153
1154                 default:
1155                         if (*vm != '\0')
1156                                 vm++;
1157                 }
1158         }
1159         if (p->xres == 0 || p->yres == 0) {
1160                 printf("Invalid video mode: %s\n", getenv("video_mode"));
1161                 lcd_enabled = 0;
1162                 printf("Supported video modes are:");
1163                 for (p = &tx53_fb_modes[0]; p->name != NULL; p++) {
1164                         printf(" %s", p->name);
1165                 }
1166                 printf("\n");
1167                 return;
1168         }
1169         if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1170                 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1171                         p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1172                 lcd_enabled = 0;
1173                 return;
1174         }
1175         panel_info.vl_col = p->xres;
1176         panel_info.vl_row = p->yres;
1177
1178         switch (color_depth) {
1179         case 8:
1180                 panel_info.vl_bpix = LCD_COLOR8;
1181                 break;
1182         case 16:
1183                 panel_info.vl_bpix = LCD_COLOR16;
1184                 break;
1185         default:
1186                 panel_info.vl_bpix = LCD_COLOR32;
1187         }
1188
1189         p->pixclock = KHZ2PICOS(refresh *
1190                 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1191                 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1192                                 1000);
1193         debug("Pixel clock set to %lu.%03lu MHz\n",
1194                 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1195
1196         if (p != &fb_mode) {
1197                 int ret;
1198
1199                 debug("Creating new display-timing node from '%s'\n",
1200                         video_mode);
1201                 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1202                 if (ret)
1203                         printf("Failed to create new display-timing node from '%s': %d\n",
1204                                 video_mode, ret);
1205         }
1206
1207         gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1208         imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1209                                         ARRAY_SIZE(stk5_lcd_pads));
1210
1211         lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
1212         switch (lcd_bus_width) {
1213         case 24:
1214                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
1215                 break;
1216
1217         case 18:
1218                 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
1219                 break;
1220
1221         case 16:
1222                 if (!is_lvds()) {
1223                         pix_fmt = IPU_PIX_FMT_RGB565;
1224                         break;
1225                 }
1226                 /* fallthru */
1227         default:
1228                 lcd_enabled = 0;
1229                 printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
1230                         lcd_bus_width);
1231                 return;
1232         }
1233         if (is_lvds()) {
1234                 int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
1235                 int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
1236                 uint32_t gpr2;
1237
1238                 if (lvds_chan_mask == 0) {
1239                         printf("No LVDS channel active\n");
1240                         lcd_enabled = 0;
1241                         return;
1242                 }
1243
1244                 gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
1245                 if (lcd_bus_width == 24)
1246                         gpr2 |= (1 << 5) | (1 << 7);
1247                 gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
1248                 gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
1249                 debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
1250                 writel(gpr2, IOMUXC_BASE_ADDR + 8);
1251         }
1252         if (karo_load_splashimage(0) == 0) {
1253                 int ret;
1254
1255                 gd->arch.ipu_hw_rev = IPUV3_HW_REV_IPUV3M;
1256
1257                 debug("Initializing LCD controller\n");
1258                 ret = ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1);
1259                 if (ret) {
1260                         printf("Failed to initialize FB driver: %d\n", ret);
1261                         lcd_enabled = 0;
1262                 }
1263         } else {
1264                 debug("Skipping initialization of LCD controller\n");
1265         }
1266 }
1267 #else
1268 #define lcd_enabled 0
1269 #endif /* CONFIG_LCD */
1270
1271 static void stk5_board_init(void)
1272 {
1273         gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1274         imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1275 }
1276
1277 static void stk5v3_board_init(void)
1278 {
1279         stk5_board_init();
1280 }
1281
1282 static void stk5v5_board_init(void)
1283 {
1284         stk5_board_init();
1285
1286         gpio_request_one(IMX_GPIO_NR(4, 21), GPIOFLAG_OUTPUT_INIT_HIGH,
1287                         "Flexcan Transceiver");
1288         imx_iomux_v3_setup_pad(MX53_PAD_DISP0_DAT0__GPIO4_21);
1289 }
1290
1291 static void tx53_set_cpu_clock(void)
1292 {
1293         unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1294
1295         if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1296                 return;
1297
1298         if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1299                 printf("%s detected; skipping cpu clock change\n",
1300                         (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1301                 return;
1302         }
1303
1304         if (mxc_set_clock(CONFIG_SYS_MX5_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1305                 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1306                 printf("CPU clock set to %lu.%03lu MHz\n",
1307                         cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1308         } else {
1309                 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1310         }
1311 }
1312
1313 static void tx53_init_mac(void)
1314 {
1315         u8 mac[ETH_ALEN];
1316
1317         imx_get_mac_from_fuse(0, mac);
1318         if (!is_valid_ether_addr(mac)) {
1319                 printf("No valid MAC address programmed\n");
1320                 return;
1321         }
1322
1323         printf("MAC addr from fuse: %pM\n", mac);
1324         eth_setenv_enetaddr("ethaddr", mac);
1325 }
1326
1327 int board_late_init(void)
1328 {
1329         int ret = 0;
1330         const char *baseboard;
1331
1332         env_cleanup();
1333
1334         tx53_set_cpu_clock();
1335
1336         if (had_ctrlc())
1337                 setenv_ulong("safeboot", 1);
1338         else if (wrsr & WRSR_TOUT)
1339                 setenv_ulong("wdreset", 1);
1340         else
1341                 karo_fdt_move_fdt();
1342
1343         baseboard = getenv("baseboard");
1344         if (!baseboard)
1345                 goto exit;
1346
1347         printf("Baseboard: %s\n", baseboard);
1348
1349         if (strncmp(baseboard, "stk5", 4) == 0) {
1350                 if ((strlen(baseboard) == 4) ||
1351                         strcmp(baseboard, "stk5-v3") == 0) {
1352                         stk5v3_board_init();
1353                 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1354                         const char *otg_mode = getenv("otg_mode");
1355
1356                         if (otg_mode && strcmp(otg_mode, "host") == 0) {
1357                                 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1358                                         otg_mode, baseboard);
1359                                 setenv("otg_mode", "none");
1360                         }
1361                         stk5v5_board_init();
1362                 } else {
1363                         printf("WARNING: Unsupported STK5 board rev.: %s\n",
1364                                 baseboard + 4);
1365                 }
1366         } else {
1367                 printf("WARNING: Unsupported baseboard: '%s'\n",
1368                         baseboard);
1369                 ret = -EINVAL;
1370         }
1371
1372 exit:
1373         tx53_init_mac();
1374
1375         gpio_set_value(TX53_RESET_OUT_GPIO, 1);
1376         clear_ctrlc();
1377         return ret;
1378 }
1379
1380 int checkboard(void)
1381 {
1382         tx53_print_cpuinfo();
1383 #if CONFIG_SYS_SDRAM_SIZE < SZ_1G
1384         printf("Board: Ka-Ro TX53-8%d3%c\n",
1385                 is_lvds(), '0' + CONFIG_SYS_SDRAM_SIZE / SZ_1G);
1386 #elif CONFIG_SYS_SDRAM_SIZE < SZ_2G
1387         printf("Board: Ka-Ro TX53-1%d3%c\n",
1388                 is_lvds() + 2, '0' + CONFIG_SYS_SDRAM_SIZE / SZ_1G);
1389 #else
1390         printf("Board: Ka-Ro TX53-123%c\n",
1391                 '0' + CONFIG_SYS_SDRAM_SIZE / SZ_1G);
1392 #endif
1393         return 0;
1394 }
1395
1396 #if defined(CONFIG_OF_BOARD_SETUP)
1397 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1398 #include <jffs2/jffs2.h>
1399 #include <mtd_node.h>
1400 static struct node_info nodes[] = {
1401         { "fsl,imx53-nand", MTD_DEV_TYPE_NAND, },
1402 };
1403 #else
1404 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1405 #endif
1406
1407 #ifdef CONFIG_SYS_TX53_HWREV_2
1408 static void tx53_fixup_rtc(void *blob)
1409 {
1410         karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupt-parent");
1411         karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupts");
1412 }
1413 #else
1414 static inline void tx53_fixup_rtc(void *blob)
1415 {
1416 }
1417 #endif /* CONFIG_SYS_TX53_HWREV_2 */
1418
1419 static const char *tx53_touchpanels[] = {
1420         "ti,tsc2007",
1421         "edt,edt-ft5x06",
1422         "eeti,egalax_ts",
1423 };
1424
1425 int ft_board_setup(void *blob, bd_t *bd)
1426 {
1427         const char *baseboard = getenv("baseboard");
1428         int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1429         const char *video_mode = karo_get_vmode(getenv("video_mode"));
1430         int ret;
1431
1432         ret = fdt_increase_size(blob, 4096);
1433         if (ret) {
1434                 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1435                 return ret;
1436         }
1437         if (stk5_v5)
1438                 karo_fdt_enable_node(blob, "stk5led", 0);
1439
1440         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1441         fdt_fixup_ethernet(blob);
1442
1443         karo_fdt_fixup_touchpanel(blob, tx53_touchpanels,
1444                                 ARRAY_SIZE(tx53_touchpanels));
1445         karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1446         karo_fdt_fixup_flexcan(blob, stk5_v5);
1447         tx53_fixup_rtc(blob);
1448         karo_fdt_update_fb_mode(blob, video_mode);
1449
1450         return 0;
1451 }
1452 #endif /* CONFIG_OF_BOARD_SETUP */