2 * Copyright (C) 2011 Lothar Waßmann <LW@KARO-electronics.de>
3 * based on: board/freesclae/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <fdt_support.h>
31 #include <fsl_esdhc.h>
33 #include <ipu_pixfmt.h>
38 #include <asm/arch/iomux-mx53.h>
39 #include <asm/arch/clock.h>
40 #include <asm/arch/imx-regs.h>
41 #include <asm/arch/crm_regs.h>
42 #include <asm/arch/sys_proto.h>
44 #include "../common/karo.h"
46 #define IMX_GPIO_NR(b, o) ((((b) - 1) << 5) | (o))
48 #define TX53_FEC_RST_GPIO IMX_GPIO_NR(7, 6)
49 #define TX53_FEC_PWR_GPIO IMX_GPIO_NR(3, 20)
50 #define TX53_FEC_INT_GPIO IMX_GPIO_NR(2, 4)
51 #define TX53_LED_GPIO IMX_GPIO_NR(2, 20)
53 #define TX53_LCD_PWR_GPIO IMX_GPIO_NR(2, 31)
54 #define TX53_LCD_RST_GPIO IMX_GPIO_NR(3, 29)
55 #define TX53_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 1)
57 #define TX53_RESET_OUT_GPIO IMX_GPIO_NR(7, 12)
59 DECLARE_GLOBAL_DATA_PTR;
61 #define MX53_GPIO_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
62 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP)
64 #define TX53_SDHC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
65 PAD_CTL_SRE_FAST | PAD_CTL_PUS_100K_DOWN)
67 static iomux_v3_cfg_t tx53_pads[] = {
68 /* NAND flash pads are set up in lowlevel_init.S */
71 MX53_PAD_GPIO_17__GPIO7_12,
74 #if CONFIG_MXC_UART_BASE == UART1_BASE
75 MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
76 MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
77 MX53_PAD_PATA_IORDY__UART1_RTS,
78 MX53_PAD_PATA_RESET_B__UART1_CTS,
80 #if CONFIG_MXC_UART_BASE == UART2_BASE
81 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
82 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
83 MX53_PAD_PATA_DIOR__UART2_RTS,
84 MX53_PAD_PATA_INTRQ__UART2_CTS,
86 #if CONFIG_MXC_UART_BASE == UART3_BASE
87 MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
88 MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
89 MX53_PAD_PATA_DA_2__UART3_RTS,
90 MX53_PAD_PATA_DA_1__UART3_CTS,
93 NEW_PAD_CTRL(MX53_PAD_EIM_D28__I2C1_SDA, MX53_GPIO_PAD_CTRL),
94 NEW_PAD_CTRL(MX53_PAD_EIM_D21__I2C1_SCL, MX53_GPIO_PAD_CTRL),
96 /* FEC PHY GPIO functions */
97 MX53_PAD_EIM_D20__GPIO3_20, /* PHY POWER */
98 MX53_PAD_PATA_DA_0__GPIO7_6, /* PHY RESET */
99 MX53_PAD_PATA_DATA4__GPIO2_4, /* PHY INT */
102 MX53_PAD_FEC_MDC__FEC_MDC,
103 MX53_PAD_FEC_MDIO__FEC_MDIO,
104 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
105 MX53_PAD_FEC_RX_ER__FEC_RX_ER,
106 MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
107 MX53_PAD_FEC_RXD1__FEC_RDATA_1,
108 MX53_PAD_FEC_RXD0__FEC_RDATA_0,
109 MX53_PAD_FEC_TX_EN__FEC_TX_EN,
110 MX53_PAD_FEC_TXD1__FEC_TDATA_1,
111 MX53_PAD_FEC_TXD0__FEC_TDATA_0,
114 static const struct gpio tx53_gpios[] = {
115 { TX53_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", },
116 { TX53_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
117 { TX53_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", },
118 { TX53_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },
124 /* placed in section '.data' to prevent overwriting relocation info
127 static u32 wrsr __attribute__((section(".data")));
129 #define WRSR_POR (1 << 4)
130 #define WRSR_TOUT (1 << 1)
131 #define WRSR_SFTW (1 << 0)
133 static void print_reset_cause(void)
135 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
136 void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
140 printf("Reset cause: ");
142 srsr = readl(&src_regs->srsr);
143 wrsr = readw(wdt_base + 4);
145 if (wrsr & WRSR_POR) {
146 printf("%sPOR", dlm);
149 if (srsr & 0x00004) {
150 printf("%sCSU", dlm);
153 if (srsr & 0x00008) {
154 printf("%sIPP USER", dlm);
157 if (srsr & 0x00010) {
158 if (wrsr & WRSR_SFTW) {
159 printf("%sSOFT", dlm);
162 if (wrsr & WRSR_TOUT) {
163 printf("%sWDOG", dlm);
167 if (srsr & 0x00020) {
168 printf("%sJTAG HIGH-Z", dlm);
171 if (srsr & 0x00040) {
172 printf("%sJTAG SW", dlm);
175 if (srsr & 0x10000) {
176 printf("%sWARM BOOT", dlm);
185 static void print_cpuinfo(void)
189 cpurev = get_cpu_rev();
191 printf("CPU: Freescale i.MX53 rev%d.%d at %d MHz\n",
192 (cpurev & 0x000F0) >> 4,
193 (cpurev & 0x0000F) >> 0,
194 mxc_get_clock(MXC_ARM_CLK) / 1000000);
199 int board_early_init_f(void)
201 gpio_request_array(tx53_gpios, ARRAY_SIZE(tx53_gpios));
202 mxc_iomux_v3_setup_multiple_pads(tx53_pads, ARRAY_SIZE(tx53_pads));
204 writel(0x77777777, AIPS1_BASE_ADDR + 0x00);
205 writel(0x77777777, AIPS1_BASE_ADDR + 0x04);
207 writel(0x00000000, AIPS1_BASE_ADDR + 0x40);
208 writel(0x00000000, AIPS1_BASE_ADDR + 0x44);
209 writel(0x00000000, AIPS1_BASE_ADDR + 0x48);
210 writel(0x00000000, AIPS1_BASE_ADDR + 0x4c);
211 writel(0x00000000, AIPS1_BASE_ADDR + 0x50);
213 writel(0x77777777, AIPS2_BASE_ADDR + 0x00);
214 writel(0x77777777, AIPS2_BASE_ADDR + 0x04);
216 writel(0x00000000, AIPS2_BASE_ADDR + 0x40);
217 writel(0x00000000, AIPS2_BASE_ADDR + 0x44);
218 writel(0x00000000, AIPS2_BASE_ADDR + 0x48);
219 writel(0x00000000, AIPS2_BASE_ADDR + 0x4c);
220 writel(0x00000000, AIPS2_BASE_ADDR + 0x50);
227 /* Address of boot parameters */
228 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
236 /* dram_init must store complete ramsize in gd->ram_size */
237 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
240 ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK,
241 CONFIG_SYS_SDRAM_CLK, MXC_DDR_CLK);
243 printf("%s: Failed to set DDR clock to %u MHz: %d\n", __func__,
244 CONFIG_SYS_SDRAM_CLK, ret);
246 debug("%s: DDR clock set to %u.%03u MHz (desig.: %u.000 MHz)\n",
247 __func__, mxc_get_clock(MXC_DDR_CLK) / 1000000,
248 mxc_get_clock(MXC_DDR_CLK) / 1000 % 1000,
249 CONFIG_SYS_SDRAM_CLK);
253 void dram_init_banksize(void)
255 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
256 gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
258 #if CONFIG_NR_DRAM_BANKS > 1
259 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
260 gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
265 #ifdef CONFIG_CMD_MMC
266 int board_mmc_getcd(struct mmc *mmc)
268 struct fsl_esdhc_cfg *cfg = mmc->priv;
270 if (cfg->cd_gpio < 0)
273 return !gpio_get_value(cfg->cd_gpio);
276 static struct fsl_esdhc_cfg esdhc_cfg[] = {
278 .esdhc_base = (void __iomem *)MMC_SDHC1_BASE_ADDR,
280 .cd_gpio = IMX_GPIO_NR(3, 24),
284 .esdhc_base = (void __iomem *)MMC_SDHC2_BASE_ADDR,
286 .cd_gpio = IMX_GPIO_NR(3, 25),
291 static const iomux_v3_cfg_t mmc0_pads[] = {
292 NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, TX53_SDHC_PAD_CTRL),
293 NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, TX53_SDHC_PAD_CTRL),
294 NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, TX53_SDHC_PAD_CTRL),
295 NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, TX53_SDHC_PAD_CTRL),
296 NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, TX53_SDHC_PAD_CTRL),
297 NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, TX53_SDHC_PAD_CTRL),
299 NEW_PAD_CTRL(MX53_PAD_EIM_D24__GPIO3_24, MX53_GPIO_PAD_CTRL),
302 static const iomux_v3_cfg_t mmc1_pads[] = {
303 NEW_PAD_CTRL(MX53_PAD_SD2_CMD__ESDHC2_CMD, TX53_SDHC_PAD_CTRL),
304 NEW_PAD_CTRL(MX53_PAD_SD2_CLK__ESDHC2_CLK, TX53_SDHC_PAD_CTRL),
305 NEW_PAD_CTRL(MX53_PAD_SD2_DATA0__ESDHC2_DAT0, TX53_SDHC_PAD_CTRL),
306 NEW_PAD_CTRL(MX53_PAD_SD2_DATA1__ESDHC2_DAT1, TX53_SDHC_PAD_CTRL),
307 NEW_PAD_CTRL(MX53_PAD_SD2_DATA2__ESDHC2_DAT2, TX53_SDHC_PAD_CTRL),
308 NEW_PAD_CTRL(MX53_PAD_SD2_DATA3__ESDHC2_DAT3, TX53_SDHC_PAD_CTRL),
310 NEW_PAD_CTRL(MX53_PAD_EIM_D25__GPIO3_25, MX53_GPIO_PAD_CTRL),
314 const iomux_v3_cfg_t *pads;
316 } mmc_pad_config[] = {
317 { mmc0_pads, ARRAY_SIZE(mmc0_pads), },
318 { mmc1_pads, ARRAY_SIZE(mmc1_pads), },
321 int board_mmc_init(bd_t *bis)
325 for (i = 0; i < ARRAY_SIZE(esdhc_cfg); i++) {
328 if (i >= CONFIG_SYS_FSL_ESDHC_NUM)
331 mxc_iomux_v3_setup_multiple_pads(mmc_pad_config[i].pads,
332 mmc_pad_config[i].count);
333 fsl_esdhc_initialize(bis, &esdhc_cfg[i]);
335 mmc = find_mmc_device(i);
338 if (board_mmc_getcd(mmc) > 0)
343 #endif /* CONFIG_CMD_MMC */
345 #ifdef CONFIG_FEC_MXC
351 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
354 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
355 struct fuse_bank *bank = &iim->bank[1];
356 struct fuse_bank1_regs *fuse = (struct fuse_bank1_regs *)bank->fuse_regs;
361 for (i = 0; i < ETH_ALEN; i++)
362 mac[i] = readl(&fuse->mac_addr[i]);
365 #define FEC_PAD_CTL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
367 #define FEC_PAD_CTL2 (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
368 #define GPIO_PAD_CTL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
370 int board_eth_init(bd_t *bis)
373 unsigned char mac[ETH_ALEN];
374 char mac_str[ETH_ALEN * 3] = "";
376 /* delay at least 21ms for the PHY internal POR signal to deassert */
379 /* Deassert RESET to the external phy */
380 gpio_set_value(TX53_FEC_RST_GPIO, 1);
382 ret = cpu_eth_init(bis);
384 printf("cpu_eth_init() failed: %d\n", ret);
388 imx_get_mac_from_fuse(0, mac);
389 snprintf(mac_str, sizeof(mac_str), "%02x:%02x:%02x:%02x:%02x:%02x",
390 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
391 setenv("ethaddr", mac_str);
395 #endif /* CONFIG_FEC_MXC */
403 void show_activity(int arg)
405 static int led_state = LED_STATE_INIT;
408 if (led_state == LED_STATE_INIT) {
410 gpio_set_value(TX53_LED_GPIO, 1);
411 led_state = LED_STATE_ON;
413 if (get_timer(last) > CONFIG_SYS_HZ) {
415 if (led_state == LED_STATE_ON) {
416 gpio_set_value(TX53_LED_GPIO, 0);
418 gpio_set_value(TX53_LED_GPIO, 1);
420 led_state = 1 - led_state;
425 static const iomux_v3_cfg_t stk5_pads[] = {
426 /* SW controlled LED on STK5 baseboard */
427 MX53_PAD_EIM_A18__GPIO2_20,
429 /* I2C bus on DIMM pins 40/41 */
430 NEW_PAD_CTRL(MX53_PAD_GPIO_6__I2C3_SDA, MX53_GPIO_PAD_CTRL),
431 NEW_PAD_CTRL(MX53_PAD_GPIO_3__I2C3_SCL, MX53_GPIO_PAD_CTRL),
433 /* TSC200x PEN IRQ */
434 NEW_PAD_CTRL(MX53_PAD_EIM_D26__GPIO3_26, MX53_GPIO_PAD_CTRL),
436 /* EDT-FT5x06 Polytouch panel */
437 NEW_PAD_CTRL(MX53_PAD_NANDF_CS2__GPIO6_15, MX53_GPIO_PAD_CTRL), /* IRQ */
438 NEW_PAD_CTRL(MX53_PAD_EIM_A16__GPIO2_22, MX53_GPIO_PAD_CTRL), /* RESET */
439 NEW_PAD_CTRL(MX53_PAD_EIM_A17__GPIO2_21, MX53_GPIO_PAD_CTRL), /* WAKE */
442 NEW_PAD_CTRL(MX53_PAD_EIM_D31__GPIO3_31, MX53_GPIO_PAD_CTRL), /* VBUSEN */
443 NEW_PAD_CTRL(MX53_PAD_EIM_D30__GPIO3_30, MX53_GPIO_PAD_CTRL), /* OC */
445 MX53_PAD_GPIO_7__GPIO1_7, /* VBUSEN */
446 MX53_PAD_GPIO_8__GPIO1_8, /* OC */
448 /* DS1339 Interrupt */
449 NEW_PAD_CTRL(MX53_PAD_DI0_PIN4__GPIO4_20, MX53_GPIO_PAD_CTRL),
452 static const struct gpio stk5_gpios[] = {
453 { TX53_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
455 { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", },
456 { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
457 { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", },
458 { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
462 vidinfo_t panel_info = {
463 /* set to max. size supported by SoC */
467 .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
470 static struct fb_videomode tx53_fb_mode = {
471 /* Standard VGA timing */
476 .pixclock = KHZ2PICOS(25175),
483 .sync = FB_SYNC_CLK_LAT_FALL,
484 .vmode = FB_VMODE_NONINTERLACED,
487 void *lcd_base; /* Start of framebuffer memory */
488 void *lcd_console_address; /* Start of console buffer */
497 void lcd_initcolregs(void)
501 void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
505 static int lcd_enabled = 1;
507 void lcd_enable(void)
510 * global variable from common/lcd.c
511 * Set to 0 here to prevent messages from going to LCD
512 * rather than serial console
516 karo_load_splashimage(1);
518 debug("Switching LCD on\n");
519 gpio_set_value(TX53_LCD_PWR_GPIO, 1);
521 gpio_set_value(TX53_LCD_RST_GPIO, 1);
523 gpio_set_value(TX53_LCD_BACKLIGHT_GPIO, 0);
527 void mxcfb_disable(void);
529 void lcd_disable(void)
534 void lcd_panel_disable(void)
537 debug("Switching LCD off\n");
538 gpio_set_value(TX53_LCD_BACKLIGHT_GPIO, 1);
539 gpio_set_value(TX53_LCD_RST_GPIO, 0);
540 gpio_set_value(TX53_LCD_PWR_GPIO, 0);
544 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
546 NEW_PAD_CTRL(MX53_PAD_EIM_D29__GPIO3_29, MX53_GPIO_PAD_CTRL),
547 /* LCD POWER_ENABLE */
548 NEW_PAD_CTRL(MX53_PAD_EIM_EB3__GPIO2_31, MX53_GPIO_PAD_CTRL),
549 /* LCD Backlight (PWM) */
550 NEW_PAD_CTRL(MX53_PAD_GPIO_1__GPIO1_1, MX53_GPIO_PAD_CTRL),
553 MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
554 MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
555 MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
556 MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
557 MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
558 MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
559 MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
560 MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
561 MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
562 MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
563 MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
564 MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
565 MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
566 MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
567 MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
568 MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
569 MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
570 MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
571 MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
572 MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
573 MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
574 MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
575 MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
576 MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
577 MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
578 MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
579 MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
580 MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
583 MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3,
584 MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2,
585 MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK,
586 MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1,
587 MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0,
588 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
589 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
590 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
591 MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
592 MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
595 static const struct gpio stk5_lcd_gpios[] = {
596 { TX53_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
597 { TX53_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
598 { TX53_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
601 void lcd_ctrl_init(void *lcdbase)
603 int color_depth = 24;
607 struct fb_videomode *p = &tx53_fb_mode;
608 int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
612 debug("LCD disabled\n");
616 if (tstc() || (wrsr & WRSR_TOUT)) {
617 debug("Disabling LCD\n");
622 vm = getenv("video_mode");
624 debug("Disabling LCD\n");
628 while (*vm != '\0') {
629 if (*vm >= '0' && *vm <= '9') {
632 val = simple_strtoul(vm, &end, 0);
635 if (val > panel_info.vl_col)
636 val = panel_info.vl_col;
638 panel_info.vl_col = val;
640 } else if (!yres_set) {
641 if (val > panel_info.vl_row)
642 val = panel_info.vl_row;
644 panel_info.vl_row = val;
646 } else if (!bpp_set) {
649 if (pix_fmt == IPU_PIX_FMT_LVDS666)
650 pix_fmt = IPU_PIX_FMT_LVDS888;
658 if (pix_fmt == IPU_PIX_FMT_LVDS666) {
664 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
665 end - vm, vm, color_depth);
668 } else if (!refresh_set) {
694 if (strncmp(vm, "LVDS", 4) == 0)
695 pix_fmt = IPU_PIX_FMT_LVDS666;
697 pix_fmt = IPU_PIX_FMT_RGB24;
698 tmp = strchr(vm, ':');
706 switch (color_depth) {
708 panel_info.vl_bpix = 3;
712 panel_info.vl_bpix = 4;
717 panel_info.vl_bpix = 5;
719 lcd_line_length = NBITS(panel_info.vl_bpix) / 8 * panel_info.vl_col;
721 p->pixclock = KHZ2PICOS(refresh *
722 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
723 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len)
725 debug("Pixel clock set to %lu.%03lu MHz\n",
726 PICOS2KHZ(p->pixclock) / 1000,
727 PICOS2KHZ(p->pixclock) % 1000);
729 gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
730 mxc_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
731 ARRAY_SIZE(stk5_lcd_pads));
733 debug("Initializing FB driver\n");
735 pix_fmt = IPU_PIX_FMT_RGB24;
736 else if (pix_fmt == IPU_PIX_FMT_LVDS666) {
737 writel(0x01, IOMUXC_BASE_ADDR + 8);
738 } else if (pix_fmt == IPU_PIX_FMT_LVDS888) {
739 writel(0x21, IOMUXC_BASE_ADDR + 8);
741 if (pix_fmt != IPU_PIX_FMT_RGB24) {
742 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)MXC_CCM_BASE;
743 /* enable LDB & DI0 clock */
744 writel(readl(&ccm_regs->CCGR6) | (3 << 28) | (3 << 10),
748 mx5_fb_init(p, 0, pix_fmt, 1 << panel_info.vl_bpix);
750 if (karo_load_splashimage(0) == 0) {
751 debug("Initializing LCD controller\n");
754 debug("Skipping initialization of LCD controller\n");
758 #define lcd_enabled 0
759 #endif /* CONFIG_LCD */
761 static void stk5_board_init(void)
763 gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
764 mxc_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
767 static void stk5v3_board_init(void)
772 static void stk5v5_board_init(void)
776 gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH,
777 "Flexcan Transceiver");
778 mxc_iomux_v3_setup_pad(MX53_PAD_DISP0_DAT0__GPIO4_21);
781 static void tx53_set_cpu_clock(void)
783 unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
786 if (tstc() || (wrsr & WRSR_TOUT))
789 if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
792 ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK, cpu_clk, MXC_ARM_CLK);
794 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
797 printf("CPU clock set to %u.%03u MHz\n",
798 mxc_get_clock(MXC_ARM_CLK) / 1000000,
799 mxc_get_clock(MXC_ARM_CLK) / 1000 % 1000);
802 int board_late_init(void)
805 const char *baseboard;
807 tx53_set_cpu_clock();
810 baseboard = getenv("baseboard");
814 if (strncmp(baseboard, "stk5", 4) == 0) {
815 printf("Baseboard: %s\n", baseboard);
816 if ((strlen(baseboard) == 4) ||
817 strcmp(baseboard, "stk5-v3") == 0) {
819 } else if (strcmp(baseboard, "stk5-v5") == 0) {
822 printf("WARNING: Unsupported STK5 board rev.: %s\n",
826 printf("WARNING: Unsupported baseboard: '%s'\n",
832 gpio_set_value(TX53_RESET_OUT_GPIO, 1);
840 printf("Board: Ka-Ro TX53-xx3%s\n",
846 #if defined(CONFIG_OF_BOARD_SETUP)
847 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
848 #include <jffs2/jffs2.h>
849 #include <mtd_node.h>
850 struct node_info nodes[] = {
851 { "fsl,imx53-nand", MTD_DEV_TYPE_NAND, },
855 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
858 static void tx53_fixup_flexcan(void *blob)
860 const char *baseboard = getenv("baseboard");
862 if (baseboard && strcmp(baseboard, "stk5-v5") == 0)
865 karo_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x53fc8000, "transceiver-switch");
866 karo_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x53fcc000, "transceiver-switch");
869 #ifdef CONFIG_SYS_TX53_HWREV_2
870 void tx53_fixup_rtc(void *blob)
872 karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupt-parent");
873 karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupts");
876 static inline void tx53_fixup_rtc(void *blob)
881 void ft_board_setup(void *blob, bd_t *bd)
883 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
884 fdt_fixup_ethernet(blob);
886 karo_fdt_fixup_touchpanel(blob);
887 karo_fdt_fixup_usb_otg(blob);
888 tx53_fixup_flexcan(blob);
889 tx53_fixup_rtc(blob);