2 * Copyright (C) 2011-2013 Lothar Waßmann <LW@KARO-electronics.de>
3 * based on: board/freescale/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
22 #include <fdt_support.h>
26 #include <fsl_esdhc.h>
33 #include <asm/arch/iomux-mx53.h>
34 #include <asm/arch/clock.h>
35 #include <asm/arch/imx-regs.h>
36 #include <asm/arch/crm_regs.h>
37 #include <asm/arch/sys_proto.h>
39 #include "../common/karo.h"
41 #define TX53_FEC_RST_GPIO IMX_GPIO_NR(7, 6)
42 #define TX53_FEC_PWR_GPIO IMX_GPIO_NR(3, 20)
43 #define TX53_FEC_INT_GPIO IMX_GPIO_NR(2, 4)
44 #define TX53_LED_GPIO IMX_GPIO_NR(2, 20)
46 #define TX53_LCD_PWR_GPIO IMX_GPIO_NR(2, 31)
47 #define TX53_LCD_RST_GPIO IMX_GPIO_NR(3, 29)
48 #define TX53_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 1)
50 #define TX53_RESET_OUT_GPIO IMX_GPIO_NR(7, 12)
52 DECLARE_GLOBAL_DATA_PTR;
54 #define MX53_GPIO_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_PUE | \
55 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP)
57 #define TX53_SDHC_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
58 PAD_CTL_SRE_FAST | PAD_CTL_PUS_47K_UP)
60 static iomux_v3_cfg_t tx53_pads[] = {
61 /* NAND flash pads are set up in lowlevel_init.S */
64 #if CONFIG_MXC_UART_BASE == UART1_BASE
65 MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
66 MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
67 MX53_PAD_PATA_IORDY__UART1_RTS,
68 MX53_PAD_PATA_RESET_B__UART1_CTS,
70 #if CONFIG_MXC_UART_BASE == UART2_BASE
71 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
72 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
73 MX53_PAD_PATA_DIOR__UART2_RTS,
74 MX53_PAD_PATA_INTRQ__UART2_CTS,
76 #if CONFIG_MXC_UART_BASE == UART3_BASE
77 MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
78 MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
79 MX53_PAD_PATA_DA_2__UART3_RTS,
80 MX53_PAD_PATA_DA_1__UART3_CTS,
83 MX53_PAD_EIM_D28__I2C1_SDA | MX53_GPIO_PAD_CTRL,
84 MX53_PAD_EIM_D21__I2C1_SCL | MX53_GPIO_PAD_CTRL,
86 /* FEC PHY GPIO functions */
87 MX53_PAD_EIM_D20__GPIO3_20, /* PHY POWER */
88 MX53_PAD_PATA_DA_0__GPIO7_6, /* PHY RESET */
89 MX53_PAD_PATA_DATA4__GPIO2_4, /* PHY INT */
92 MX53_PAD_FEC_MDC__FEC_MDC,
93 MX53_PAD_FEC_MDIO__FEC_MDIO,
94 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
95 MX53_PAD_FEC_RX_ER__FEC_RX_ER,
96 MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
97 MX53_PAD_FEC_RXD1__FEC_RDATA_1,
98 MX53_PAD_FEC_RXD0__FEC_RDATA_0,
99 MX53_PAD_FEC_TX_EN__FEC_TX_EN,
100 MX53_PAD_FEC_TXD1__FEC_TDATA_1,
101 MX53_PAD_FEC_TXD0__FEC_TDATA_0,
104 static const struct gpio tx53_gpios[] = {
105 { TX53_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", },
106 { TX53_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
107 { TX53_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", },
108 { TX53_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", },
114 /* placed in section '.data' to prevent overwriting relocation info
117 static u32 wrsr __attribute__((section(".data")));
119 #define WRSR_POR (1 << 4)
120 #define WRSR_TOUT (1 << 1)
121 #define WRSR_SFTW (1 << 0)
123 static void print_reset_cause(void)
125 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
126 void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
130 printf("Reset cause: ");
132 srsr = readl(&src_regs->srsr);
133 wrsr = readw(wdt_base + 4);
135 if (wrsr & WRSR_POR) {
136 printf("%sPOR", dlm);
139 if (srsr & 0x00004) {
140 printf("%sCSU", dlm);
143 if (srsr & 0x00008) {
144 printf("%sIPP USER", dlm);
147 if (srsr & 0x00010) {
148 if (wrsr & WRSR_SFTW) {
149 printf("%sSOFT", dlm);
152 if (wrsr & WRSR_TOUT) {
153 printf("%sWDOG", dlm);
157 if (srsr & 0x00020) {
158 printf("%sJTAG HIGH-Z", dlm);
161 if (srsr & 0x00040) {
162 printf("%sJTAG SW", dlm);
165 if (srsr & 0x10000) {
166 printf("%sWARM BOOT", dlm);
175 static void tx53_print_cpuinfo(void)
179 cpurev = get_cpu_rev();
181 printf("CPU: Freescale i.MX53 rev%d.%d at %d MHz\n",
182 (cpurev & 0x000F0) >> 4,
183 (cpurev & 0x0000F) >> 0,
184 mxc_get_clock(MXC_ARM_CLK) / 1000000);
189 int board_early_init_f(void)
191 struct mxc_ccm_reg *ccm_regs = (void *)CCM_BASE_ADDR;
193 gpio_request_array(tx53_gpios, ARRAY_SIZE(tx53_gpios));
194 imx_iomux_v3_setup_multiple_pads(tx53_pads, ARRAY_SIZE(tx53_pads));
196 writel(0x77777777, AIPS1_BASE_ADDR + 0x00);
197 writel(0x77777777, AIPS1_BASE_ADDR + 0x04);
199 writel(0x00000000, AIPS1_BASE_ADDR + 0x40);
200 writel(0x00000000, AIPS1_BASE_ADDR + 0x44);
201 writel(0x00000000, AIPS1_BASE_ADDR + 0x48);
202 writel(0x00000000, AIPS1_BASE_ADDR + 0x4c);
203 writel(0x00000000, AIPS1_BASE_ADDR + 0x50);
205 writel(0x77777777, AIPS2_BASE_ADDR + 0x00);
206 writel(0x77777777, AIPS2_BASE_ADDR + 0x04);
208 writel(0x00000000, AIPS2_BASE_ADDR + 0x40);
209 writel(0x00000000, AIPS2_BASE_ADDR + 0x44);
210 writel(0x00000000, AIPS2_BASE_ADDR + 0x48);
211 writel(0x00000000, AIPS2_BASE_ADDR + 0x4c);
212 writel(0x00000000, AIPS2_BASE_ADDR + 0x50);
214 writel(0xffcf0fff, &ccm_regs->CCGR0);
215 writel(0x000fffc3, &ccm_regs->CCGR1);
216 writel(0x033c0000, &ccm_regs->CCGR2);
217 writel(0x000000ff, &ccm_regs->CCGR3);
218 writel(0x00000000, &ccm_regs->CCGR4);
219 writel(0x00fff033, &ccm_regs->CCGR5);
220 writel(0x0f00030f, &ccm_regs->CCGR6);
221 writel(0xfff00000, &ccm_regs->CCGR7);
222 writel(0x00000000, &ccm_regs->cmeor);
229 /* Address of boot parameters */
230 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
238 /* dram_init must store complete ramsize in gd->ram_size */
239 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
242 ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK,
243 CONFIG_SYS_SDRAM_CLK, MXC_DDR_CLK);
245 printf("%s: Failed to set DDR clock to %u MHz: %d\n", __func__,
246 CONFIG_SYS_SDRAM_CLK, ret);
248 debug("%s: DDR clock set to %u.%03u MHz (desig.: %u.000 MHz)\n",
249 __func__, mxc_get_clock(MXC_DDR_CLK) / 1000000,
250 mxc_get_clock(MXC_DDR_CLK) / 1000 % 1000,
251 CONFIG_SYS_SDRAM_CLK);
255 void dram_init_banksize(void)
257 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
258 gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
260 #if CONFIG_NR_DRAM_BANKS > 1
261 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
262 gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
267 #ifdef CONFIG_CMD_MMC
268 static const iomux_v3_cfg_t mmc0_pads[] = {
269 MX53_PAD_SD1_CMD__ESDHC1_CMD | TX53_SDHC_PAD_CTRL,
270 MX53_PAD_SD1_CLK__ESDHC1_CLK | TX53_SDHC_PAD_CTRL,
271 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 | TX53_SDHC_PAD_CTRL,
272 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 | TX53_SDHC_PAD_CTRL,
273 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 | TX53_SDHC_PAD_CTRL,
274 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 | TX53_SDHC_PAD_CTRL,
276 MX53_PAD_EIM_D24__GPIO3_24 | MX53_GPIO_PAD_CTRL,
279 static const iomux_v3_cfg_t mmc1_pads[] = {
280 MX53_PAD_SD2_CMD__ESDHC2_CMD | TX53_SDHC_PAD_CTRL,
281 MX53_PAD_SD2_CLK__ESDHC2_CLK | TX53_SDHC_PAD_CTRL,
282 MX53_PAD_SD2_DATA0__ESDHC2_DAT0 | TX53_SDHC_PAD_CTRL,
283 MX53_PAD_SD2_DATA1__ESDHC2_DAT1 | TX53_SDHC_PAD_CTRL,
284 MX53_PAD_SD2_DATA2__ESDHC2_DAT2 | TX53_SDHC_PAD_CTRL,
285 MX53_PAD_SD2_DATA3__ESDHC2_DAT3 | TX53_SDHC_PAD_CTRL,
287 MX53_PAD_EIM_D25__GPIO3_25 | MX53_GPIO_PAD_CTRL,
290 static struct tx53_esdhc_cfg {
291 const iomux_v3_cfg_t *pads;
293 struct fsl_esdhc_cfg cfg;
295 } tx53_esdhc_cfg[] = {
298 .num_pads = ARRAY_SIZE(mmc0_pads),
300 .esdhc_base = (void __iomem *)MMC_SDHC1_BASE_ADDR,
303 .cd_gpio = IMX_GPIO_NR(3, 24),
307 .num_pads = ARRAY_SIZE(mmc1_pads),
309 .esdhc_base = (void __iomem *)MMC_SDHC2_BASE_ADDR,
312 .cd_gpio = IMX_GPIO_NR(3, 25),
316 #define to_tx53_esdhc_cfg(p) container_of(p, struct tx53_esdhc_cfg, cfg)
318 int board_mmc_getcd(struct mmc *mmc)
320 struct tx53_esdhc_cfg *cfg = to_tx53_esdhc_cfg(mmc->priv);
322 if (cfg->cd_gpio < 0)
325 debug("SD card %d is %spresent\n",
326 cfg - tx53_esdhc_cfg,
327 gpio_get_value(cfg->cd_gpio) ? "NOT " : "");
328 return !gpio_get_value(cfg->cd_gpio);
331 int board_mmc_init(bd_t *bis)
335 for (i = 0; i < ARRAY_SIZE(tx53_esdhc_cfg); i++) {
337 struct tx53_esdhc_cfg *cfg = &tx53_esdhc_cfg[i];
340 if (i >= CONFIG_SYS_FSL_ESDHC_NUM)
343 imx_iomux_v3_setup_multiple_pads(cfg->pads,
345 cfg->cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
347 fsl_esdhc_initialize(bis, &cfg->cfg);
349 ret = gpio_request_one(cfg->cd_gpio,
350 GPIOF_INPUT, "MMC CD");
352 printf("Error %d requesting GPIO%d_%d\n",
353 ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
357 mmc = find_mmc_device(i);
360 if (board_mmc_getcd(mmc) > 0)
365 #endif /* CONFIG_CMD_MMC */
367 #ifdef CONFIG_FEC_MXC
373 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
376 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
377 struct fuse_bank *bank = &iim->bank[1];
378 struct fuse_bank1_regs *fuse = (struct fuse_bank1_regs *)bank->fuse_regs;
383 for (i = 0; i < ETH_ALEN; i++)
384 mac[i] = readl(&fuse->mac_addr[i]);
387 #define FEC_PAD_CTL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \
389 #define FEC_PAD_CTL2 (PAD_CTL_DVS | PAD_CTL_SRE_FAST)
390 #define GPIO_PAD_CTL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
392 int board_eth_init(bd_t *bis)
395 unsigned char mac[ETH_ALEN];
397 /* delay at least 21ms for the PHY internal POR signal to deassert */
400 /* Deassert RESET to the external phy */
401 gpio_set_value(TX53_FEC_RST_GPIO, 1);
403 ret = cpu_eth_init(bis);
405 printf("cpu_eth_init() failed: %d\n", ret);
409 imx_get_mac_from_fuse(0, mac);
410 eth_setenv_enetaddr("ethaddr", mac);
411 printf("MAC addr from fuse: %pM\n", mac);
415 #endif /* CONFIG_FEC_MXC */
423 void show_activity(int arg)
425 static int led_state = LED_STATE_INIT;
428 if (led_state == LED_STATE_INIT) {
430 gpio_set_value(TX53_LED_GPIO, 1);
431 led_state = LED_STATE_ON;
433 if (get_timer(last) > CONFIG_SYS_HZ) {
435 if (led_state == LED_STATE_ON) {
436 gpio_set_value(TX53_LED_GPIO, 0);
438 gpio_set_value(TX53_LED_GPIO, 1);
440 led_state = 1 - led_state;
445 static const iomux_v3_cfg_t stk5_pads[] = {
446 /* SW controlled LED on STK5 baseboard */
447 MX53_PAD_EIM_A18__GPIO2_20,
449 /* I2C bus on DIMM pins 40/41 */
450 MX53_PAD_GPIO_6__I2C3_SDA | MX53_GPIO_PAD_CTRL,
451 MX53_PAD_GPIO_3__I2C3_SCL | MX53_GPIO_PAD_CTRL,
453 /* TSC200x PEN IRQ */
454 MX53_PAD_EIM_D26__GPIO3_26 | MX53_GPIO_PAD_CTRL,
456 /* EDT-FT5x06 Polytouch panel */
457 MX53_PAD_NANDF_CS2__GPIO6_15 | MX53_GPIO_PAD_CTRL, /* IRQ */
458 MX53_PAD_EIM_A16__GPIO2_22 | MX53_GPIO_PAD_CTRL, /* RESET */
459 MX53_PAD_EIM_A17__GPIO2_21 | MX53_GPIO_PAD_CTRL, /* WAKE */
462 MX53_PAD_EIM_D31__GPIO3_31 | MX53_GPIO_PAD_CTRL, /* VBUSEN */
463 MX53_PAD_EIM_D30__GPIO3_30 | MX53_GPIO_PAD_CTRL, /* OC */
465 MX53_PAD_GPIO_7__GPIO1_7, /* VBUSEN */
466 MX53_PAD_GPIO_8__GPIO1_8, /* OC */
468 /* DS1339 Interrupt */
469 MX53_PAD_DI0_PIN4__GPIO4_20 | MX53_GPIO_PAD_CTRL,
472 static const struct gpio stk5_gpios[] = {
473 { TX53_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
475 { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", },
476 { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
477 { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", },
478 { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
482 vidinfo_t panel_info = {
483 /* set to max. size supported by SoC */
487 .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
490 static struct fb_videomode tx53_fb_modes[] = {
492 /* Standard VGA timing */
497 .pixclock = KHZ2PICOS(25175),
504 .sync = FB_SYNC_CLK_LAT_FALL,
507 /* Emerging ETV570 640 x 480 display. Syncs low active,
508 * DE high active, 115.2 mm x 86.4 mm display area
509 * VGA compatible timing
515 .pixclock = KHZ2PICOS(25175),
522 .sync = FB_SYNC_CLK_LAT_FALL,
525 /* Emerging ET0350G0DH6 320 x 240 display.
526 * 70.08 mm x 52.56 mm display area.
532 .pixclock = KHZ2PICOS(6500),
533 .left_margin = 68 - 34,
536 .upper_margin = 18 - 3,
539 .sync = FB_SYNC_CLK_LAT_FALL,
542 /* Emerging ET0430G0DH6 480 x 272 display.
543 * 95.04 mm x 53.856 mm display area.
549 .pixclock = KHZ2PICOS(9000),
556 .sync = FB_SYNC_CLK_LAT_FALL,
559 /* Emerging ET0500G0DH6 800 x 480 display.
560 * 109.6 mm x 66.4 mm display area.
566 .pixclock = KHZ2PICOS(33260),
567 .left_margin = 216 - 128,
569 .right_margin = 1056 - 800 - 216,
570 .upper_margin = 35 - 2,
572 .lower_margin = 525 - 480 - 35,
573 .sync = FB_SYNC_CLK_LAT_FALL,
576 /* Emerging ETQ570G0DH6 320 x 240 display.
577 * 115.2 mm x 86.4 mm display area.
583 .pixclock = KHZ2PICOS(6400),
587 .upper_margin = 16, /* 15 according to datasheet */
588 .vsync_len = 3, /* TVP -> 1>x>5 */
589 .lower_margin = 4, /* 4.5 according to datasheet */
590 .sync = FB_SYNC_CLK_LAT_FALL,
593 /* Emerging ET0700G0DH6 800 x 480 display.
594 * 152.4 mm x 91.44 mm display area.
600 .pixclock = KHZ2PICOS(33260),
601 .left_margin = 216 - 128,
603 .right_margin = 1056 - 800 - 216,
604 .upper_margin = 35 - 2,
606 .lower_margin = 525 - 480 - 35,
607 .sync = FB_SYNC_CLK_LAT_FALL,
610 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
618 .sync = FB_SYNC_CLK_LAT_FALL,
622 static int lcd_enabled = 1;
624 void lcd_enable(void)
627 * global variable from common/lcd.c
628 * Set to 0 here to prevent messages from going to LCD
629 * rather than serial console
634 karo_load_splashimage(1);
636 debug("Switching LCD on\n");
637 gpio_set_value(TX53_LCD_PWR_GPIO, 1);
639 gpio_set_value(TX53_LCD_RST_GPIO, 1);
641 gpio_set_value(TX53_LCD_BACKLIGHT_GPIO, 0);
645 void lcd_disable(void)
648 printf("Disabling LCD\n");
653 void lcd_panel_disable(void)
656 debug("Switching LCD off\n");
657 gpio_set_value(TX53_LCD_BACKLIGHT_GPIO, 1);
658 gpio_set_value(TX53_LCD_RST_GPIO, 0);
659 gpio_set_value(TX53_LCD_PWR_GPIO, 0);
663 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
665 MX53_PAD_EIM_D29__GPIO3_29 | MX53_GPIO_PAD_CTRL,
666 /* LCD POWER_ENABLE */
667 MX53_PAD_EIM_EB3__GPIO2_31 | MX53_GPIO_PAD_CTRL,
668 /* LCD Backlight (PWM) */
669 MX53_PAD_GPIO_1__GPIO1_1 | MX53_GPIO_PAD_CTRL,
672 MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
673 MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
674 MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
675 MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
676 MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
677 MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
678 MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
679 MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
680 MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
681 MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
682 MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
683 MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
684 MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
685 MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
686 MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
687 MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
688 MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
689 MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
690 MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
691 MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
692 MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
693 MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
694 MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
695 MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
696 MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
697 MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
698 MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
699 MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
702 MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3,
703 MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2,
704 MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK,
705 MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1,
706 MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0,
707 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
708 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
709 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
710 MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
711 MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
714 static const struct gpio stk5_lcd_gpios[] = {
715 { TX53_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", },
716 { TX53_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", },
717 { TX53_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
720 void lcd_ctrl_init(void *lcdbase)
722 int color_depth = 24;
726 struct fb_videomode *p = &tx53_fb_modes[0];
727 struct fb_videomode fb_mode;
728 int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
730 ipu_di_clk_parent_t di_clk_parent = DI_PCLK_PLL3;
731 unsigned long di_clk_rate = 65000000;
734 debug("LCD disabled\n");
738 if (tstc() || (wrsr & WRSR_TOUT)) {
739 debug("Disabling LCD\n");
741 setenv("splashimage", NULL);
747 vm = getenv("video_mode");
749 debug("Disabling LCD\n");
753 if (karo_fdt_get_fb_mode(working_fdt, vm, &fb_mode) == 0) {
755 debug("Using video mode from FDT\n");
757 if (fb_mode.xres > panel_info.vl_col ||
758 fb_mode.yres > panel_info.vl_row) {
759 printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
760 fb_mode.xres, fb_mode.yres,
761 panel_info.vl_col, panel_info.vl_row);
767 debug("Trying compiled-in video modes\n");
768 while (p->name != NULL) {
769 if (strcmp(p->name, vm) == 0) {
770 debug("Using video mode: '%s'\n", p->name);
777 debug("Trying to decode video_mode: '%s'\n", vm);
778 while (*vm != '\0') {
779 if (*vm >= '0' && *vm <= '9') {
782 val = simple_strtoul(vm, &end, 0);
785 if (val > panel_info.vl_col)
786 val = panel_info.vl_col;
788 panel_info.vl_col = val;
790 } else if (!yres_set) {
791 if (val > panel_info.vl_row)
792 val = panel_info.vl_row;
794 panel_info.vl_row = val;
796 } else if (!bpp_set) {
800 if (pix_fmt == IPU_PIX_FMT_LVDS666)
801 pix_fmt = IPU_PIX_FMT_LVDS888;
809 if (pix_fmt == IPU_PIX_FMT_LVDS666) {
815 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
816 end - vm, vm, color_depth);
819 } else if (!refresh_set) {
845 if (strncmp(vm, "LVDS", 4) == 0) {
846 pix_fmt = IPU_PIX_FMT_LVDS666;
847 di_clk_parent = DI_PCLK_LDB;
849 pix_fmt = IPU_PIX_FMT_RGB24;
851 tmp = strchr(vm, ':');
859 if (p->xres == 0 || p->yres == 0) {
860 printf("Invalid video mode: %s\n", getenv("video_mode"));
862 printf("Supported video modes are:");
863 for (p = &tx53_fb_modes[0]; p->name != NULL; p++) {
864 printf(" %s", p->name);
869 if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
870 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
871 p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
875 panel_info.vl_col = p->xres;
876 panel_info.vl_row = p->yres;
878 switch(color_depth) {
880 panel_info.vl_bpix = LCD_COLOR8;
883 panel_info.vl_bpix = LCD_COLOR16;
886 panel_info.vl_bpix = LCD_COLOR24;
889 p->pixclock = KHZ2PICOS(refresh *
890 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
891 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len)
893 debug("Pixel clock set to %lu.%03lu MHz\n",
894 PICOS2KHZ(p->pixclock) / 1000,
895 PICOS2KHZ(p->pixclock) % 1000);
899 char *modename = getenv("video_mode");
901 printf("Creating new display-timing node from '%s'\n",
903 ret = karo_fdt_create_fb_mode(working_fdt, modename, p);
905 printf("Failed to create new display-timing node from '%s': %d\n",
909 gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
910 imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
911 ARRAY_SIZE(stk5_lcd_pads));
913 debug("Initializing FB driver\n");
915 pix_fmt = IPU_PIX_FMT_RGB24;
916 else if (pix_fmt == IPU_PIX_FMT_LVDS666) {
917 writel(0x01, IOMUXC_BASE_ADDR + 8);
918 } else if (pix_fmt == IPU_PIX_FMT_LVDS888) {
919 writel(0x21, IOMUXC_BASE_ADDR + 8);
921 if (pix_fmt != IPU_PIX_FMT_RGB24) {
922 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
923 /* enable LDB & DI0 clock */
924 writel(readl(&ccm_regs->CCGR6) | (3 << 28) | (3 << 10),
928 if (karo_load_splashimage(0) == 0) {
931 gd->arch.ipu_hw_rev = IPUV3_HW_REV_IPUV3M;
933 debug("Initializing LCD controller\n");
934 ret = ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1);
936 printf("Failed to initialize FB driver: %d\n", ret);
940 debug("Skipping initialization of LCD controller\n");
944 #define lcd_enabled 0
945 #endif /* CONFIG_LCD */
947 static void stk5_board_init(void)
949 gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
950 imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
953 static void stk5v3_board_init(void)
958 static void stk5v5_board_init(void)
962 gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH,
963 "Flexcan Transceiver");
964 imx_iomux_v3_setup_pad(MX53_PAD_DISP0_DAT0__GPIO4_21);
967 static void tx53_set_cpu_clock(void)
969 unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
972 if (tstc() || (wrsr & WRSR_TOUT))
975 if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
978 ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK, cpu_clk, MXC_ARM_CLK);
980 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
983 printf("CPU clock set to %u.%03u MHz\n",
984 mxc_get_clock(MXC_ARM_CLK) / 1000000,
985 mxc_get_clock(MXC_ARM_CLK) / 1000 % 1000);
988 int board_late_init(void)
991 const char *baseboard;
993 tx53_set_cpu_clock();
996 baseboard = getenv("baseboard");
1000 if (strncmp(baseboard, "stk5", 4) == 0) {
1001 printf("Baseboard: %s\n", baseboard);
1002 if ((strlen(baseboard) == 4) ||
1003 strcmp(baseboard, "stk5-v3") == 0) {
1004 stk5v3_board_init();
1005 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1006 stk5v5_board_init();
1008 printf("WARNING: Unsupported STK5 board rev.: %s\n",
1012 printf("WARNING: Unsupported baseboard: '%s'\n",
1018 gpio_set_value(TX53_RESET_OUT_GPIO, 1);
1022 int checkboard(void)
1024 tx53_print_cpuinfo();
1026 printf("Board: Ka-Ro TX53-xx3%s\n",
1032 #if defined(CONFIG_OF_BOARD_SETUP)
1033 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1034 #include <jffs2/jffs2.h>
1035 #include <mtd_node.h>
1036 struct node_info nodes[] = {
1037 { "fsl,imx53-nand", MTD_DEV_TYPE_NAND, },
1041 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1044 #ifdef CONFIG_SYS_TX53_HWREV_2
1045 void tx53_fixup_rtc(void *blob)
1047 karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupt-parent");
1048 karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupts");
1051 static inline void tx53_fixup_rtc(void *blob)
1054 #endif /* CONFIG_SYS_TX53_HWREV_2 */
1056 void ft_board_setup(void *blob, bd_t *bd)
1058 const char *baseboard = getenv("baseboard");
1059 int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1061 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1062 fdt_fixup_ethernet(blob);
1064 karo_fdt_fixup_touchpanel(blob);
1065 karo_fdt_fixup_usb_otg(blob, "fsl,imx-otg", "fsl,usbphy");
1066 karo_fdt_fixup_flexcan(blob, stk5_v5);
1067 tx53_fixup_rtc(blob);
1068 karo_fdt_update_fb_mode(blob, getenv("video_mode"));
1070 #endif /* CONFIG_OF_BOARD_SETUP */