2 #include <configs/tx6.h>
3 #include <asm/arch/imx-regs.h>
4 #include <generated/asm-offsets.h>
7 #error asm-offsets not included
10 #define DEBUG_LED_BIT 20
11 #define LED_GPIO_BASE GPIO2_BASE_ADDR
12 #define LED_MUX_OFFSET 0x0ec
13 #define LED_MUX_MODE 0x15
15 #define SDRAM_CLK CONFIG_SYS_SDRAM_CLK
17 #ifdef PHYS_SDRAM_2_SIZE
18 #define SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
20 #define SDRAM_SIZE PHYS_SDRAM_1_SIZE
23 #define CPU_2_BE_32(l) \
24 ((((l) << 24) & 0xFF000000) | \
25 (((l) << 8) & 0x00FF0000) | \
26 (((l) >> 8) & 0x0000FF00) | \
27 (((l) >> 24) & 0x000000FF))
29 #define CHECK_DCD_ADDR(a) ( \
30 ((a) >= 0x020E0000 && (a) <= 0x020E3FFF) /* IOMUXC */ || \
31 ((a) >= 0x020C4000 && (a) <= 0x020C7FFF) /* CCM */ || \
32 ((a) >= 0x020C8000 && (a) <= 0x020C8FFF) /* ANALOG */ || \
33 ((a) >= 0x021B0000 && (a) <= 0x021B7FFF) /* MMDC */ || \
34 ((a) >= 0x00907000 && (a) <= 0x00937FF0) /* OCRAM */ || \
35 ((a) >= 0x08000000 && (a) <= 0x0FFEFFFF) /* EIM (CS0) */ || \
36 ((a) >= 0x10000000 && (a) <= 0xFFFFFFFF) /* SDRAM */)
38 .macro mxc_dcd_item addr, val
39 .ifne CHECK_DCD_ADDR(\addr)
40 .word CPU_2_BE_32(\addr), CPU_2_BE_32(\val)
42 .error "Address \addr not accessible from DCD"
46 #define MXC_DCD_ITEM(addr, val) mxc_dcd_item (addr), (val)
47 #if PHYS_SDRAM_1_WIDTH == 16
48 #define MXC_DCD_ITEM_16(addr, val) mxc_dcd_item (addr), (val)
49 #define MXC_DCD_CMD_CHK_16(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask)
51 #define MXC_DCD_ITEM_16(addr, val)
52 #define MXC_DCD_CMD_CHK_16(type, flags, addr, mask)
54 #if PHYS_SDRAM_1_WIDTH > 16
55 #define MXC_DCD_ITEM_32(addr, val) mxc_dcd_item (addr), (val)
56 #define MXC_DCD_CMD_CHK_32(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask)
58 #define MXC_DCD_ITEM_32(addr, val)
59 #define MXC_DCD_CMD_CHK_32(type, flags, addr, mask)
61 #if PHYS_SDRAM_1_WIDTH == 64
62 #define MXC_DCD_ITEM_64(addr, val) mxc_dcd_item (addr), (val)
63 #define MXC_DCD_CMD_CHK_64(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask)
65 #define MXC_DCD_ITEM_64(addr, val)
66 #define MXC_DCD_CMD_CHK_64(type, flags, addr, mask)
69 #define MXC_DCD_CMD_SZ_BYTE 1
70 #define MXC_DCD_CMD_SZ_SHORT 2
71 #define MXC_DCD_CMD_SZ_WORD 4
72 #define MXC_DCD_CMD_FLAG_WRITE 0x0
73 #define MXC_DCD_CMD_FLAG_CLR 0x1
74 #define MXC_DCD_CMD_FLAG_SET 0x3
75 #define MXC_DCD_CMD_FLAG_CHK_CLR ((0 << 0) | (0 << 1))
76 #define MXC_DCD_CMD_FLAG_CHK_SET ((0 << 0) | (1 << 1))
77 #define MXC_DCD_CMD_FLAG_CHK_ANY_CLR ((1 << 0) | (0 << 1))
78 #define MXC_DCD_CMD_FLAG_CHK_ANY_SET ((1 << 0) | (1 << 1))
80 #define MXC_DCD_START \
81 .word CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION) ; \
86 .ifgt . - dcd_start - 1768
87 .error "DCD too large!"
92 #define MXC_DCD_CMD_WRT(type, flags) \
93 1: .word CPU_2_BE_32((0xcc << 24) | ((1f - .) << 8) | ((flags) << 3) | (type))
95 #define MXC_DCD_CMD_CHK(type, flags, addr, mask) \
96 1: .word CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)), \
97 CPU_2_BE_32(addr), CPU_2_BE_32(mask)
99 #define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count) \
100 1: .word CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)), \
101 CPU_2_BE_32(addr), CPU_2_BE_32(mask), CPU_2_BE_32(count)
103 #define MXC_DCD_CMD_NOP() \
104 1: .word CPU_2_BE_32((0xc0 << 24) | (4 << 8))
107 #define CK_TO_NS(ck) (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK)
108 #define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000)
109 #define NS_TO_CK10(ns) DIV_ROUND_UP(NS_TO_CK(ns), 10)
111 .macro CK_VAL, name, clks, offs, max
115 .ifle \clks - \offs - \max
116 .set \name, \clks - \offs
118 .error "Value \clks out of range for parameter \name"
123 .macro NS_VAL, name, ns, offs, max
127 CK_VAL \name, NS_TO_CK(\ns), \offs, \max
131 .macro CK_MAX, name, ck1, ck2, offs, max
133 CK_VAL \name, \ck1, \offs, \max
135 CK_VAL \name, \ck2, \offs, \max
139 #define MDMISC_DDR_TYPE_DDR3 0
140 #define MDMISC_DDR_TYPE_LPDDR2 1
141 #define MDMISC_DDR_TYPE_DDR2 2
143 #define DIV_ROUND_UP(m,d) (((m) + (d) - 1) / (d))
145 #define MDOR_CLK_PERIOD_ns 15258 /* base clock for MDOR values */
148 #if SDRAM_SIZE > PHYS_SDRAM_1_SIZE
149 #define BANK_ADDR_BITS 2
151 #define BANK_ADDR_BITS 1
153 #define SDRAM_BURST_LENGTH 8
157 #define ADDR_MIRROR 0
158 #define DDR_TYPE MDMISC_DDR_TYPE_DDR3
160 /* 512/1024MiB SDRAM: NT5CB128M16FP-DII */
161 #if SDRAM_CLK > 666 && SDRAM_CLK <= 800
164 #elif SDRAM_CLK > 533 && SDRAM_CLK <= 666
165 #define CL_VAL 9 // or 10
167 #elif SDRAM_CLK > 400 && SDRAM_CLK <= 533
168 #define CL_VAL 7 // or 8
170 #elif SDRAM_CLK > 333 && SDRAM_CLK <= 400
173 #elif SDRAM_CLK >= 303 && SDRAM_CLK <= 333
177 #error SDRAM clock out of range: 303 .. 800
181 NS_VAL tRFC, 160, 1, 255 /* clks - 1 (0..255) */
182 CK_MAX tXS, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */
183 CK_MAX tXP, NS_TO_CK10(75), 3, 1, 7 /* clks - 1 (0..7) */ /* max(3tCK, 7.5ns) */
184 CK_MAX tXPDLL, NS_TO_CK(24), 2, 1, 15 /* clks - 1 (0..15) */
185 NS_VAL tFAW, 50, 1, 31 /* clks - 1 (0..31) */
186 CK_VAL tCL, CL_VAL, 3, 8 /* clks - 3 (0..8) CAS Latency */
189 CK_VAL tRCD, NS_TO_CK10(125), 1, 7 /* clks - 1 (0..7) */ /* 12.5 */
190 CK_VAL tRP, NS_TO_CK10(125), 1, 7 /* clks - 1 (0..7) */ /* 12.5 */
191 NS_VAL tRC, 50, 1, 31 /* clks - 1 (0..31) */
192 CK_VAL tRAS, NS_TO_CK10(375), 1, 31 /* clks - 1 (0..31) */ /* 37.5 */
193 CK_VAL tRPA, 1, 0, 1 /* clks (0..1) */
194 NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */
195 CK_VAL tMRD, 4, 1, 15 /* clks - 1 (0..15) */
196 CK_VAL tCWL, CWL_VAL, 2, 6 /* clks - 2 (0..6) */
199 CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */
200 CK_MAX tRTP, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
201 CK_MAX tWTR, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
202 CK_MAX tRRD, NS_TO_CK(10), 4, 1, 7 /* clks - 1 (0..7) */
205 CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */
206 #define tSDE_RST (DIV_ROUND_UP(200000, MDOR_CLK_PERIOD_ns) + 2)
207 #define tRST_CKE (DIV_ROUND_UP(500000, MDOR_CLK_PERIOD_ns) + 2)
210 CK_VAL tAOFPD, NS_TO_CK10(85), 1, 7 /* clks - 1 (0..7) */ /* 8.5ns */
211 CK_VAL tAONPD, NS_TO_CK10(85), 1, 7 /* clks - 1 (0..7) */ /* 8.5ns */
212 CK_VAL tANPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */
213 CK_VAL tAXPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */
214 CK_VAL tODTLon tCWL, 0, 7 /* clks - 1 (0..7) */ /* CWL+AL-2 */
215 CK_VAL tODTLoff tCWL, 0, 31 /* clks - 1 (0..31) */ /* CWL+AL-2 */
218 CK_MAX tCKE, NS_TO_CK(5), 3, 1, 7
219 CK_MAX tCKSRX, NS_TO_CK(10), 5, 0, 7
220 CK_MAX tCKSRE, NS_TO_CK(10), 5, 0, 7
227 #define MDPDC_VAL_0 ( \
232 (BOTH_CS_PD << 6) | \
237 #define MDPDC_VAL_1 (MDPDC_VAL_0 | \
242 #define ROW_ADDR_BITS 14
243 #define COL_ADDR_BITS 10
245 #define Rtt_Nom 1 /* ODT: 0: off 1: RZQ/4 2: RZQ/2 3: RZQ/6 4: RZQ/12 5: RZQ/8 */
246 #define Rtt_WR 0 /* Dynamic ODT: 0: off 1: RZQ/4 2: RZQ/2 */
247 #define DLL_DISABLE 0
250 .set mr0_val, (((1 - DLL_DISABLE) << 8) /* DLL Reset */ | \
251 (SLOW_PD << 12) /* PD exit: 0: fast 1: slow */ |\
252 ((tWR + 1 - 4) << 9) | \
253 ((((tCL + 3) - 4) & 0x7) << 4) | \
254 ((((tCL + 3) - 4) & 0x8) >> 1))
256 .set mr0_val, ((1 << 8) /* DLL Reset */ | \
257 (SLOW_PD << 12) /* PD exit: 0: fast 1: slow */ |\
258 (((tWR + 1) / 2) << 9) | \
259 ((((tCL + 3) - 4) & 0x7) << 4) | \
260 ((((tCL + 3) - 4) & 0x8) >> 1))
264 ((Rtt_Nom & 1) << 2) | \
265 (((Rtt_Nom >> 1) & 1) << 6) | \
266 (((Rtt_Nom >> 2) & 1) << 9) | \
267 (DLL_DISABLE << 0) | \
270 (Rtt_WR << 9) /* dynamic ODT */ | \
271 (0 << 7) /* SRT: Ext. temp. (mutually exclusive with ASR!) */ | \
272 (1 << 6) | /* ASR: Automatic Self Refresh */ \
273 (((tCWL + 2) - 5) << 3) | \
277 #define MDSCR_MRS_VAL(cs, mr, val) (((val) << 16) | \
278 (1 << 15) /* CON_REQ */ | \
279 (3 << 4) /* MRS command */ | \
284 #define MDCFG0_VAL ( \
292 #define MDCFG1_VAL ( \
302 #define MDCFG2_VAL ( \
308 #define BURST_LEN (SDRAM_BURST_LENGTH / 8) /* 0: 4 byte 1: 8 byte */
310 #define MDCTL_VAL (((ROW_ADDR_BITS - 11) << 24) | \
311 ((COL_ADDR_BITS - 9) << 20) | \
312 (BURST_LEN << 19) | \
313 ((PHYS_SDRAM_1_WIDTH / 32) << 16) | \
314 ((-1) << (32 - BANK_ADDR_BITS)))
316 #define MDMISC_VAL ((ADDR_MIRROR << 19) | \
323 #define MDOR_VAL ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0))
325 #define MDOTC_VAL ((tAOFPD << 27) | \
333 .word CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40)
349 .long CONFIG_U_BOOT_IMG_SIZE
353 #define DCD_VERSION 0x40
355 #define DDR_SEL_VAL 3 /* DDR3 */
356 #if PHYS_SDRAM_1_WIDTH == 16
357 #define DSE1_VAL 6 /* Drive Strength for DATA lines */
358 #define DSE2_VAL 6 /* Drive Strength for ADDR/CMD lines */
360 #define DSE1_VAL 6 /* Drive Strength for DATA lines */
361 #define DSE2_VAL 6 /* Drive Strength for ADDR/CMD lines */
364 #define DDR_PKE_VAL 0
366 #define DDR_SEL_SHIFT 18
367 #define DDR_MODE_SHIFT 17
375 #define DDR_SEL_MASK (DDR_SEL_VAL << DDR_SEL_SHIFT)
376 #define DDR_MODE_MASK (1 << DDR_MODE_SHIFT) /* differential input mode */
377 #define DSE1_MASK (DSE1_VAL << DSE_SHIFT)
378 #define DSE2_MASK (DSE2_VAL << DSE_SHIFT)
379 #define ODT_MASK (ODT_VAL << ODT_SHIFT)
380 #define DDR_PKE_MASK (DDR_PKE_VAL << PKE_SHIFT)
382 #define DQM_MASK (DDR_MODE_MASK | DSE2_MASK)
383 #define SDQS_MASK DSE2_MASK
384 #define SDODT_MASK (DSE2_MASK | (1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
385 #define SDCLK_MASK (DDR_MODE_MASK | DSE2_MASK)
386 #define SDCKE_MASK ((1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
387 #define DDR_ADDR_MASK (ODT_MASK | DDR_MODE_MASK)
388 #define DDR_CTRL_MASK (DDR_MODE_MASK | DSE2_MASK)
390 #define MMDC1_MDCTL 0x021b0000
391 #define MMDC1_MDPDC 0x021b0004
392 #define MMDC1_MDOTC 0x021b0008
393 #define MMDC1_MDCFG0 0x021b000c
394 #define MMDC1_MDCFG1 0x021b0010
395 #define MMDC1_MDCFG2 0x021b0014
396 #define MMDC1_MDMISC 0x021b0018
397 #define MMDC1_MDSCR 0x021b001c
398 #define MMDC1_MDREF 0x021b0020
399 #define MMDC1_MDRWD 0x021b002c
400 #define MMDC1_MDOR 0x021b0030
401 #define MMDC1_MDASP 0x021b0040
402 #define MMDC1_MAPSR 0x021b0404
403 #define MMDC1_MPZQHWCTRL 0x021b0800
404 #define MMDC1_MPWLGCR 0x021b0808
405 #define MMDC1_MPWLDECTRL0 0x021b080c
406 #define MMDC1_MPWLDECTRL1 0x021b0810
407 #define MMDC1_MPWLDLST 0x021b0814
408 #define MMDC1_MPODTCTRL 0x021b0818
409 #define MMDC1_MPRDDQBY0DL 0x021b081c
410 #define MMDC1_MPRDDQBY1DL 0x021b0820
411 #define MMDC1_MPRDDQBY2DL 0x021b0824
412 #define MMDC1_MPRDDQBY3DL 0x021b0828
413 #define MMDC1_MPDGCTRL0 0x021b083c
414 #define MMDC1_MPDGCTRL1 0x021b0840
415 #define MMDC1_MPDGDLST0 0x021b0844
416 #define MMDC1_MPRDDLCTL 0x021b0848
417 #define MMDC1_MPRDDLST 0x021b084c
418 #define MMDC1_MPWRDLCTL 0x021b0850
419 #define MMDC1_MPWRDLST 0x021b0854
420 #define MMDC1_MPRDDLHWCTL 0x021b0860
421 #define MMDC1_MPWRDLHWCTL 0x021b0864
422 #define MMDC1_MPPDCMPR2 0x021b0890
423 #define MMDC1_MPSWDRDR0 0x021b0898
424 #define MMDC1_MPSWDRDR1 0x021b089c
425 #define MMDC1_MPSWDRDR2 0x021b08a0
426 #define MMDC1_MPSWDRDR3 0x021b08a4
427 #define MMDC1_MPSWDRDR4 0x021b08a8
428 #define MMDC1_MPSWDRDR5 0x021b08ac
429 #define MMDC1_MPSWDRDR6 0x021b08b0
430 #define MMDC1_MPSWDRDR7 0x021b08b4
431 #define MMDC1_MPMUR0 0x021b08b8
433 #if PHYS_SDRAM_1_WIDTH == 64
434 #define MMDC2_MDPDC 0x021b4004
435 #define MMDC2_MPWLGCR 0x021b4808
436 #define MMDC2_MPWLDECTRL0 0x021b480c
437 #define MMDC2_MPWLDECTRL1 0x021b4810
438 #define MMDC2_MPWLDLST 0x021b4814
439 #define MMDC2_MPODTCTRL 0x021b4818
440 #define MMDC2_MPRDDQBY0DL 0x021b481c
441 #define MMDC2_MPRDDQBY1DL 0x021b4820
442 #define MMDC2_MPRDDQBY2DL 0x021b4824
443 #define MMDC2_MPRDDQBY3DL 0x021b4828
444 #define MMDC2_MPDGCTRL0 0x021b483c
445 #define MMDC2_MPDGCTRL1 0x021b4840
446 #define MMDC2_MPDGDLST0 0x021b4844
447 #define MMDC2_MPRDDLCTL 0x021b4848
448 #define MMDC2_MPRDDLST 0x021b484c
449 #define MMDC2_MPWRDLCTL 0x021b4850
450 #define MMDC2_MPWRDLST 0x021b4854
451 #define MMDC2_MPRDDLHWCTL 0x021b4860
452 #define MMDC2_MPWRDLHWCTL 0x021b4864
453 #define MMDC2_MPRDDLHWST0 0x021b4868
454 #define MMDC2_MPRDDLHWST1 0x021b486c
455 #define MMDC2_MPWRDLHWST0 0x021b4870
456 #define MMDC2_MPWRDLHWST1 0x021b4874
457 #define MMDC2_MPWLHWERR 0x021b4878
458 #define MMDC2_MPDGHWST0 0x021b487c
459 #define MMDC2_MPDGHWST1 0x021b4880
460 #define MMDC2_MPDGHWST2 0x021b4884
461 #define MMDC2_MPDGHWST3 0x021b4888
462 #define MMDC2_MPSWDAR0 0x021b4894
463 #define MMDC2_MPSWDRDR0 0x021b4898
464 #define MMDC2_MPSWDRDR1 0x021b489c
465 #define MMDC2_MPSWDRDR2 0x021b48a0
466 #define MMDC2_MPSWDRDR3 0x021b48a4
467 #define MMDC2_MPSWDRDR4 0x021b48a8
468 #define MMDC2_MPSWDRDR5 0x021b48ac
469 #define MMDC2_MPSWDRDR6 0x021b48b0
470 #define MMDC2_MPSWDRDR7 0x021b48b4
473 #ifdef CONFIG_SOC_MX6Q
474 #define IOMUXC_GPR1 0x020e0004
475 #define IOMUXC_SW_MUX_CTL_PAD_GPIO17 0x020e024c
476 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7 0x020e02a8
477 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6 0x020e02ac
478 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0 0x020e02c0
479 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1 0x020e02c4
480 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE 0x020e02d4
481 #define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE 0x020e02d8
482 #define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B 0x020e02dc
483 #define IOMUXC_SW_MUX_CTL_PAD_NAND_READY 0x020e02e0
484 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B 0x020e02e4
485 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B 0x020e02ec
486 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD 0x020e02f4
487 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK 0x020e02f8
488 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00 0x020e02fc
489 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01 0x020e0300
490 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 0x020e0304
491 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03 0x020e0308
492 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04 0x020e030c
493 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 0x020e0310
494 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 0x020e0314
495 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 0x020e0318
496 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P 0x020e050c
497 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 0x020e0510
498 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 0x020e0514
499 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P 0x020e0518
500 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P 0x020e051c
501 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 0x020e0520
502 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P 0x020e0524
503 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 0x020e0528
504 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00 0x020e052c
505 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01 0x020e0530
506 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02 0x020e0534
507 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03 0x020e0538
508 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04 0x020e053c
509 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05 0x020e0540
510 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06 0x020e0544
511 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07 0x020e0548
512 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08 0x020e054c
513 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09 0x020e0550
514 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10 0x020e0554
515 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11 0x020e0558
516 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12 0x020e055c
517 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13 0x020e0560
518 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14 0x020e0564
519 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15 0x020e0568
520 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS 0x020e056c
521 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS 0x020e0578
522 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET 0x020e057c
523 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0 0x020e0580
524 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1 0x020e0584
525 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P 0x020e0588
526 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 0x020e058c
527 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 0x020e0590
528 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P 0x020e0594
529 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 0x020e0598
530 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 0x020e059c
531 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 0x020e05a0
532 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P 0x020e05a8
533 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 0x020e05ac
534 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P 0x020e05b0
535 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 0x020e05b4
536 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P 0x020e05b8
537 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 0x020e05bc
538 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P 0x020e05c0
539 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 0x020e05c4
540 #define IOMUXC_SW_PAD_CTL_GRP_B7DS 0x020e0748
541 #define IOMUXC_SW_PAD_CTL_GRP_ADDDS 0x020e074c
542 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL 0x020e0750
543 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0 0x020e0754
544 #define IOMUXC_SW_PAD_CTL_GRP_DDRPKE 0x020e0758
545 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1 0x020e075c
546 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2 0x020e0760
547 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3 0x020e0764
548 #define IOMUXC_SW_PAD_CTL_GRP_DDRPK 0x020e0768
549 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4 0x020e076c
550 #define IOMUXC_SW_PAD_CTL_GRP_DDRHYS 0x020e0770
551 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE 0x020e0774
552 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5 0x020e0778
553 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6 0x020e077c
554 #define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7 0x020e0780
555 #define IOMUXC_SW_PAD_CTL_GRP_B0DS 0x020e0784
556 #define IOMUXC_SW_PAD_CTL_GRP_B1DS 0x020e0788
557 #define IOMUXC_SW_PAD_CTL_GRP_CTLDS 0x020e078c
558 #define IOMUXC_SW_PAD_CTL_GRP_B2DS 0x020e0794
559 #define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE 0x020e0798
560 #define IOMUXC_SW_PAD_CTL_GRP_B3DS 0x020e079c
561 #define IOMUXC_SW_PAD_CTL_GRP_B4DS 0x020e07a0
562 #define IOMUXC_SW_PAD_CTL_GRP_B5DS 0x020e07a4
563 #define IOMUXC_SW_PAD_CTL_GRP_B6DS 0x020e07a8
564 #define IOMUXC_UART1_UART_RTS_B_SELECT_INPUT 0x020e091c
565 #define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT 0x020e0920
568 #if defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)
569 #define IOMUXC_GPR1 0x020e0004
570 #define IOMUXC_SW_MUX_CTL_PAD_GPIO17 0x020e0218
571 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7 0x020e0330
572 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6 0x020e032c
573 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0 0x020e0314
574 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1 0x020e0318
575 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE 0x020e0270
576 #define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE 0x020e026c
577 #define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B 0x020e02a8
578 #define IOMUXC_SW_MUX_CTL_PAD_NAND_READY 0x020e02a4
579 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B 0x020e0274
580 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B 0x020e027c
581 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD 0x020e033c
582 #define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK 0x020e0338
583 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00 0x020e0284
584 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01 0x020e0288
585 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 0x020e028c
586 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03 0x020e0290
587 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04 0x020e0294
588 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 0x020e0298
589 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 0x020e029c
590 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 0x020e02a0
591 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P 0x020e04d0
592 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 0x020e0484
593 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 0x020e0480
594 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P 0x020e04cc
595 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P 0x020e04c8
596 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 0x020e047c
597 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P 0x020e04c4
598 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 0x020e0478
599 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00 0x020e0424
600 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01 0x020e0428
601 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02 0x020e0444
602 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03 0x020e0448
603 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04 0x020e044c
604 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05 0x020e0450
605 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06 0x020e0454
606 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07 0x020e0458
607 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08 0x020e045c
608 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09 0x020e0460
609 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10 0x020e042c
610 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11 0x020e0430
611 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12 0x020e0434
612 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13 0x020e0438
613 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14 0x020e043c
614 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15 0x020e0440
615 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS 0x020e0464
616 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS 0x020e0490
617 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET 0x020e0494
618 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0 0x020e0498
619 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1 0x020e049c
620 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P 0x020e04ac
621 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 0x020e04a0
622 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 0x020e04a4
623 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P 0x020e04b0
624 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 0x020e04a8
625 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 0x020e04b4
626 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 0x020e04b8
627 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P 0x020e04bc
628 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 0x020e0470
629 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P 0x020e04c0
630 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 0x020e0474
631 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P 0x020e04d4
632 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 0x020e0488
633 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P 0x020e04d8
634 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 0x020e048c
635 #define IOMUXC_SW_PAD_CTL_GRP_B7DS 0x020e0748
636 #define IOMUXC_SW_PAD_CTL_GRP_ADDDS 0x020e074c
637 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL 0x020e0750
638 #define IOMUXC_SW_PAD_CTL_GRP_DDRPKE 0x020e0754
639 #define IOMUXC_SW_PAD_CTL_GRP_DDRPK 0x020e0758
640 #define IOMUXC_SW_PAD_CTL_GRP_DDRHYS 0x020e075c
641 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE 0x020e0760
642 #define IOMUXC_SW_PAD_CTL_GRP_B0DS 0x020e0784
643 #define IOMUXC_SW_PAD_CTL_GRP_B1DS 0x020e0788
644 #define IOMUXC_SW_PAD_CTL_GRP_CTLDS 0x020e078c
645 #define IOMUXC_SW_PAD_CTL_GRP_B2DS 0x020e0794
646 #define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE 0x020e0798
647 #define IOMUXC_SW_PAD_CTL_GRP_B3DS 0x020e079c
648 #define IOMUXC_SW_PAD_CTL_GRP_B4DS 0x020e07a0
649 #define IOMUXC_SW_PAD_CTL_GRP_B5DS 0x020e07a4
650 #define IOMUXC_SW_PAD_CTL_GRP_B6DS 0x020e07a8
651 #define IOMUXC_UART1_UART_RTS_B_SELECT_INPUT 0x020e08f8
652 #define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT 0x020e08fc
657 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
658 /* RESET_OUT GPIO_7_12 */
659 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_GPIO17, 0x00000005)
661 MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CS2CDR, 0x006336c1) /* default: 0x007236c1 */
662 MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CHSCCDR, 0x00012093) /* default: 0x0002a150 */
663 MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CSCDR2, 0x00012090) /* default: 0x0002a150 */
665 MXC_DCD_ITEM(ANATOP_BASE_ADDR + ANATOP_PLL_ENET, 0x00002001) /* ENET PLL */
667 /* enable all relevant clocks... */
668 MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR0, 0xf0c03f3f) /* default: 0xf0c03f0f APBH-DMA */
669 MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR1, 0xf0fc0c00) /* default: 0xf0fc0000 */
670 MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, 0xfc3ff0cc) /* default: 0xfc3ff00c I2C1 */
671 MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR3, 0x3ff00000) /* default: 0x3ff00000 */
672 MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, 0xff00ff00) /* default: 0x0000ff00 GPMI BCH */
673 MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR5, 0xff033f0f) /* default: 0xf0033f0f UART1 */
674 MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR6, 0xffff03ff) /* default: 0xffff0003 USDHC4 (for APBH-DMA!) USDHC3 (for BCH!) */
675 MXC_DCD_ITEM(0x020c80a0, 0x80082029) /* set video PLL to 984MHz */
676 MXC_DCD_ITEM(0x020c80b0, 0x00065b9a)
677 MXC_DCD_ITEM(0x020c80c0, 0x000f4240)
680 MXC_DCD_ITEM(IOMUXC_GPR1, 0x48640005) /* default: 0x48400005 ENET_CLK output */
681 /* UART1 pad config */
682 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7, 0x00000001) /* UART1 TXD */
683 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6, 0x00000001) /* UART1 RXD */
684 #ifdef CONFIG_SOC_MX6Q
685 MXC_DCD_ITEM(IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT, 0x00000003) /* UART1 RXD INPUT_SEL */
687 MXC_DCD_ITEM(IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT, 0x00000002) /* UART1 RXD INPUT_SEL */
689 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0, 0x00000001) /* UART1 CTS */
690 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1, 0x00000001) /* UART1 RTS */
691 MXC_DCD_ITEM(IOMUXC_UART1_UART_RTS_B_SELECT_INPUT, 0x00000003) /* UART1 RTS INPUT_SEL */
693 #ifdef CONFIG_NAND_MXS
695 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CLE, 0x00000000) /* NANDF_CLE: NANDF_CLE */
696 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_ALE, 0x00000000) /* NANDF_ALE: NANDF_ALE */
697 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B, 0x00000000) /* NANDF_WP_B: NANDF_WPn */
698 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_READY, 0x00000000) /* NANDF_RB0: NANDF_READY0 */
699 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B, 0x00000000) /* NANDF_CS0: NANDF_CS0 */
700 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD4_CMD, 0x00000001) /* SD4_CMD: NANDF_RDn */
701 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD4_CLK, 0x00000001) /* SD4_CLK: NANDF_WRn */
702 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00, 0x00000000) /* NANDF_D0: NANDF_D0 */
703 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01, 0x00000000) /* NANDF_D1: NANDF_D1 */
704 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02, 0x00000000) /* NANDF_D2: NANDF_D2 */
705 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03, 0x00000000) /* NANDF_D3: NANDF_D3 */
706 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04, 0x00000000) /* NANDF_D4: NANDF_D4 */
707 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05, 0x00000000) /* NANDF_D5: NANDF_D5 */
708 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06, 0x00000000) /* NANDF_D6: NANDF_D6 */
709 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07, 0x00000000) /* NANDF_D7: NANDF_D7 */
712 MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B, 0x00000000) /* NANDF_CS2: NANDF_CS2 */
714 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0, DQM_MASK)
715 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1, DQM_MASK)
716 MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2, DQM_MASK)
717 MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3, DQM_MASK)
718 MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4, DQM_MASK)
719 MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5, DQM_MASK)
720 MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6, DQM_MASK)
721 MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7, DQM_MASK)
724 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00, DDR_ADDR_MASK)
725 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01, DDR_ADDR_MASK)
726 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02, DDR_ADDR_MASK)
727 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03, DDR_ADDR_MASK)
728 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04, DDR_ADDR_MASK)
729 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05, DDR_ADDR_MASK)
730 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06, DDR_ADDR_MASK)
731 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07, DDR_ADDR_MASK)
732 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08, DDR_ADDR_MASK)
733 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09, DDR_ADDR_MASK)
734 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10, DDR_ADDR_MASK)
735 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11, DDR_ADDR_MASK)
736 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12, DDR_ADDR_MASK)
737 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13, DDR_ADDR_MASK)
738 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14, DDR_ADDR_MASK)
739 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15, DDR_ADDR_MASK)
741 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS, DDR_CTRL_MASK)
743 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS, DDR_CTRL_MASK)
744 /* DRAM_SDCLK[0..1] */
745 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P, SDCLK_MASK)
746 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P, SDCLK_MASK)
748 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET, DDR_CTRL_MASK)
749 /* DRAM_SDCKE[0..1] */
750 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0, SDCKE_MASK)
751 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1, SDCKE_MASK)
752 /* DRAM_SDBA[0..2] */
753 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0, 0x00000000)
754 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1, 0x00000000)
755 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2, 0x00000000)
756 /* DRAM_SDODT[0..1] */
757 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0, SDODT_MASK)
758 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1, SDODT_MASK)
760 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B0DS, DSE1_MASK)
761 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B1DS, DSE1_MASK)
762 MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_GRP_B2DS, DSE1_MASK)
763 MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_GRP_B3DS, DSE1_MASK)
764 MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B4DS, DSE1_MASK)
765 MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B5DS, DSE1_MASK)
766 MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B6DS, DSE1_MASK)
767 MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B7DS, DSE1_MASK)
769 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_ADDDS, DSE2_MASK)
771 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL, DDR_MODE_MASK)
773 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRPKE, DDR_PKE_MASK)
775 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE, DDR_MODE_MASK)
777 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_CTLDS, DSE2_MASK)
779 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE, DDR_SEL_MASK)
781 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRPK, 1 << PUE_SHIFT)
783 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRHYS, 0x00000000)
785 #ifdef CONFIG_SOC_MX6Q
787 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0, ODT_MASK)
788 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1, ODT_MASK)
789 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2, ODT_MASK)
790 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3, ODT_MASK)
791 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4, ODT_MASK)
792 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5, ODT_MASK)
793 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6, ODT_MASK)
794 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7, ODT_MASK)
796 /* SDRAM initialization */
797 /* MPRDDQBY[0..7]DL */
798 MXC_DCD_ITEM(MMDC1_MPRDDQBY0DL, 0x33333333)
799 MXC_DCD_ITEM(MMDC1_MPRDDQBY1DL, 0x33333333)
800 MXC_DCD_ITEM_32(MMDC1_MPRDDQBY2DL, 0x33333333)
801 MXC_DCD_ITEM_32(MMDC1_MPRDDQBY3DL, 0x33333333)
802 MXC_DCD_ITEM_64(MMDC2_MPRDDQBY0DL, 0x33333333)
803 MXC_DCD_ITEM_64(MMDC2_MPRDDQBY1DL, 0x33333333)
804 MXC_DCD_ITEM_64(MMDC2_MPRDDQBY2DL, 0x33333333)
805 MXC_DCD_ITEM_64(MMDC2_MPRDDQBY3DL, 0x33333333)
807 MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL | 2) /* reset MMDC FSM */
808 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MDMISC, 0x00000002)
809 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
811 /* MSDSCR Conf Req */
812 MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008000)
813 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDSCR, 0x00004000)
814 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
817 MXC_DCD_ITEM(MMDC1_MDCTL, MDCTL_VAL)
818 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDMISC, 0x40000000)
819 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
821 MXC_DCD_ITEM(MMDC1_MDCFG0, MDCFG0_VAL)
822 MXC_DCD_ITEM(MMDC1_MDCFG1, MDCFG1_VAL)
823 MXC_DCD_ITEM(MMDC1_MDCFG2, MDCFG2_VAL)
824 MXC_DCD_ITEM(MMDC1_MDRWD, 0x000026d2)
825 MXC_DCD_ITEM(MMDC1_MDOR, MDOR_VAL)
826 MXC_DCD_ITEM(MMDC1_MDOTC, MDOTC_VAL)
827 MXC_DCD_ITEM(MMDC1_MDPDC, MDPDC_VAL_0)
828 MXC_DCD_ITEM_64(MMDC2_MDPDC, MDPDC_VAL_0)
829 MXC_DCD_ITEM(MMDC1_MDASP, (PHYS_SDRAM_1_SIZE + SZ_256M) / SZ_32M - 1)
832 MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 0, mr0_val))
833 MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 1, mr1_val))
834 MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 2, mr2_val))
835 MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 0))
836 #if BANK_ADDR_BITS > 1
838 MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 0, mr0_val))
839 MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 1, mr1_val))
840 MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 2, mr2_val))
841 MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 0))
844 MXC_DCD_ITEM(MMDC1_MDREF, 0x0000c000) /* disable refresh */
845 MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008020) /* issue one refresh cycle */
847 MXC_DCD_ITEM(MMDC1_MPODTCTRL, 0x00022222)
848 MXC_DCD_ITEM_64(MMDC2_MPODTCTRL, 0x00022222)
850 /* DDR3 calibration */
851 MXC_DCD_ITEM(MMDC1_MPPDCMPR2, 0x00000003) /* select default compare pattern for DQ calibration */
852 MXC_DCD_ITEM(MMDC1_MAPSR, 0x00001007)
855 MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008010) /* precharge all */
856 MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008040) /* MRS: ZQ calibration */
857 MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa1390001)
859 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPZQHWCTRL, 0x00010000)
860 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
862 MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa1380000)
864 #define WL_DLY_DQS_VAL 30
865 #define WL_DLY_DQS0 (WL_DLY_DQS_VAL + 0)
866 #define WL_DLY_DQS1 (WL_DLY_DQS_VAL + 0)
867 #define WL_DLY_DQS2 (WL_DLY_DQS_VAL + 0)
868 #define WL_DLY_DQS3 (WL_DLY_DQS_VAL + 0)
869 #define WL_DLY_DQS4 (WL_DLY_DQS_VAL + 0)
870 #define WL_DLY_DQS5 (WL_DLY_DQS_VAL + 0)
871 #define WL_DLY_DQS6 (WL_DLY_DQS_VAL + 0)
872 #define WL_DLY_DQS7 (WL_DLY_DQS_VAL + 0)
874 MXC_DCD_ITEM(MMDC1_MPWLDECTRL0, (WL_DLY_DQS1 << 16) | (WL_DLY_DQS0 << 0))
875 MXC_DCD_ITEM_32(MMDC1_MPWLDECTRL1, (WL_DLY_DQS3 << 16) | (WL_DLY_DQS2 << 0))
876 MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL0, (WL_DLY_DQS5 << 16) | (WL_DLY_DQS4 << 0))
877 MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL1, (WL_DLY_DQS7 << 16) | (WL_DLY_DQS6 << 0))
879 #if PHYS_SDRAM_1_WIDTH > 16
882 /* DQS gating calibration */
883 MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 4)) /* MRS: select MPR */
884 #if BANK_ADDR_BITS > 1
885 MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 4)) /* MRS: select MPR */
887 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK | 0x7000) /* enable Pullups on DQS pads */
888 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK | 0x7000)
889 MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, SDQS_MASK | 0x7000)
890 MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, SDQS_MASK | 0x7000)
891 MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P, SDQS_MASK | 0x7000)
892 MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, SDQS_MASK | 0x7000)
893 MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, SDQS_MASK | 0x7000)
894 MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, SDQS_MASK | 0x7000)
896 MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008020) /* issue one refresh cycle */
897 MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
899 MXC_DCD_ITEM(MMDC1_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */
900 MXC_DCD_ITEM(MMDC1_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */
901 MXC_DCD_ITEM_64(MMDC2_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */
902 MXC_DCD_ITEM_64(MMDC2_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */
904 MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x80000000) /* issue fifo reset */
905 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x80000000)
906 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
907 MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x80000000) /* issue 2nd fifo reset */
908 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x80000000)
909 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
910 MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x50800000) /* choose 32 wait cycles and start DQS calib. */
911 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x10001000)
912 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
913 #else /* DO_DDR_CALIB */
914 #define MPMUR_FRC_MSR (1 << 11)
915 MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x41e20160)
916 MXC_DCD_ITEM(MMDC1_MPDGCTRL1, 0x014d014f)
917 MXC_DCD_ITEM_64(MMDC2_MPDGCTRL0, 0x014f0150)
918 MXC_DCD_ITEM_64(MMDC2_MPDGCTRL1, 0x0144014a)
919 #endif /* DO_DDR_CALIB */
920 /* DRAM_SDQS[0..7] pad config */
921 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK)
922 MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK)
923 MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, SDQS_MASK)
924 MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, SDQS_MASK)
925 MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P, SDQS_MASK)
926 MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, SDQS_MASK)
927 MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, SDQS_MASK)
928 MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, SDQS_MASK)
930 /* Read delay calibration */
931 MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
932 MXC_DCD_ITEM(MMDC1_MPRDDLHWCTL, 0x00000030) /* MPRDDLHWCTL: HW_WR_DL_CMP_CYC | HW_RD_DL_EN */
933 MXC_DCD_ITEM_64(MMDC2_MPRDDLHWCTL, 0x00000030) /* MPRDDLHWCTL: HW_WR_DL_CMP_CYC | HW_RD_DL_EN */
934 MXC_DCD_CMD_CHK_16(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x00000013)
935 MXC_DCD_CMD_CHK_32(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x0000001f)
936 MXC_DCD_CMD_CHK_64(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPRDDLHWCTL, 0x0000001f)
937 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
938 #else /* DO_DDR_CALIB */
939 MXC_DCD_ITEM(MMDC1_MPRDDLCTL, 0x4a4f4e4c)
940 MXC_DCD_ITEM_64(MMDC2_MPRDDLCTL, 0x4e50504a)
941 #endif /* DO_DDR_CALIB */
943 /* Write delay calibration */
944 MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
945 MXC_DCD_ITEM(MMDC1_MPWRDLHWCTL, 0x00000030) /* start WR DL calibration */
946 MXC_DCD_CMD_CHK_16(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x00000013)
947 MXC_DCD_CMD_CHK_32(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x0000001f)
948 #if PHYS_SDRAM_1_WIDTH == 64
949 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
951 MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */
952 MXC_DCD_ITEM(MMDC2_MPWRDLHWCTL, 0x00000030) /* start WR DL calibration */
953 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWRDLHWCTL, 0x0000001f)
955 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
956 #else /* DO_DDR_CALIB */
957 MXC_DCD_ITEM(MMDC1_MPWRDLCTL, 0x3f3f3f3f)
958 MXC_DCD_ITEM_64(MMDC2_MPWRDLCTL, 0x3f3f3f3f)
959 MXC_DCD_ITEM(MMDC1_MPMUR0, MPMUR_FRC_MSR)
960 #endif /* DO_DDR_CALIB */
961 MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
962 #if BANK_ADDR_BITS > 1
963 MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 0)) /* MRS: select normal data path */
965 MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa138002b)
966 MXC_DCD_ITEM(MMDC1_MDREF, (3 << 11) | (0 << 14)) /* 4 cycles per 64kHz period (3.9us) */
967 MXC_DCD_ITEM(MMDC1_MAPSR, 0x00001006)
968 MXC_DCD_ITEM(MMDC1_MDPDC, MDPDC_VAL_1)
969 MXC_DCD_ITEM_64(MMDC2_MDPDC, MDPDC_VAL_1)
971 /* MDSCR: Normal operation */
972 MXC_DCD_ITEM(MMDC1_MDSCR, 0x00000000)
973 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MDSCR, 0x00004000)