2 * Copyright (C) 2012-2015 Lothar Waßmann <LW@KARO-electronics.de>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <fdt_support.h>
14 #include <fsl_esdhc.h>
22 #include <asm/arch/mx6-pins.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/hab.h>
25 #include <asm/arch/imx-regs.h>
26 #include <asm/arch/crm_regs.h>
27 #include <asm/arch/sys_proto.h>
29 #include "../common/karo.h"
32 #define __data __attribute__((section(".data")))
34 #define TX6_FEC_RST_GPIO IMX_GPIO_NR(7, 6)
35 #define TX6_FEC_PWR_GPIO IMX_GPIO_NR(3, 20)
36 #define TX6_FEC_INT_GPIO IMX_GPIO_NR(7, 1)
37 #define TX6_LED_GPIO IMX_GPIO_NR(2, 20)
39 #define TX6_LCD_PWR_GPIO IMX_GPIO_NR(2, 31)
40 #define TX6_LCD_RST_GPIO IMX_GPIO_NR(3, 29)
41 #define TX6_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 1)
43 #define TX6_RESET_OUT_GPIO IMX_GPIO_NR(7, 12)
44 #define TX6_I2C1_SCL_GPIO IMX_GPIO_NR(3, 21)
45 #define TX6_I2C1_SDA_GPIO IMX_GPIO_NR(3, 28)
47 #ifdef CONFIG_MX6_TEMPERATURE_MIN
48 #define TEMPERATURE_MIN CONFIG_MX6_TEMPERATURE_MIN
50 #define TEMPERATURE_MIN (-40)
52 #ifdef CONFIG_MX6_TEMPERATURE_HOT
53 #define TEMPERATURE_HOT CONFIG_MX6_TEMPERATURE_HOT
55 #define TEMPERATURE_HOT 80
58 DECLARE_GLOBAL_DATA_PTR;
60 #define MUX_CFG_SION IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
62 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
63 #ifdef CONFIG_SECURE_BOOT
64 char __csf_data[0] __attribute__((section(".__csf_data")));
67 static const iomux_v3_cfg_t const tx6qdl_pads[] = {
69 MX6_PAD_GPIO_17__GPIO7_IO12,
72 #if CONFIG_MXC_UART_BASE == UART1_BASE
73 MX6_PAD_SD3_DAT7__UART1_TX_DATA,
74 MX6_PAD_SD3_DAT6__UART1_RX_DATA,
75 MX6_PAD_SD3_DAT1__UART1_RTS_B,
76 MX6_PAD_SD3_DAT0__UART1_CTS_B,
78 #if CONFIG_MXC_UART_BASE == UART2_BASE
79 MX6_PAD_SD4_DAT4__UART2_RX_DATA,
80 MX6_PAD_SD4_DAT7__UART2_TX_DATA,
81 MX6_PAD_SD4_DAT5__UART2_RTS_B,
82 MX6_PAD_SD4_DAT6__UART2_CTS_B,
84 #if CONFIG_MXC_UART_BASE == UART3_BASE
85 MX6_PAD_EIM_D24__UART3_TX_DATA,
86 MX6_PAD_EIM_D25__UART3_RX_DATA,
87 MX6_PAD_SD3_RST__UART3_RTS_B,
88 MX6_PAD_SD3_DAT3__UART3_CTS_B,
91 MX6_PAD_EIM_D28__I2C1_SDA,
92 MX6_PAD_EIM_D21__I2C1_SCL,
94 /* FEC PHY GPIO functions */
95 MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_CFG_SION, /* PHY POWER */
96 MX6_PAD_SD3_DAT2__GPIO7_IO06 | MUX_CFG_SION, /* PHY RESET */
97 MX6_PAD_SD3_DAT4__GPIO7_IO01, /* PHY INT */
100 static const iomux_v3_cfg_t const tx6qdl_fec_pads[] = {
102 MX6_PAD_ENET_MDC__ENET_MDC,
103 MX6_PAD_ENET_MDIO__ENET_MDIO,
104 MX6_PAD_GPIO_16__ENET_REF_CLK,
105 MX6_PAD_ENET_RX_ER__ENET_RX_ER,
106 MX6_PAD_ENET_CRS_DV__ENET_RX_EN,
107 MX6_PAD_ENET_RXD1__ENET_RX_DATA1,
108 MX6_PAD_ENET_RXD0__ENET_RX_DATA0,
109 MX6_PAD_ENET_TX_EN__ENET_TX_EN,
110 MX6_PAD_ENET_TXD1__ENET_TX_DATA1,
111 MX6_PAD_ENET_TXD0__ENET_TX_DATA0,
114 #define TX6_I2C_GPIO_PAD_CTRL (PAD_CTL_PUS_22K_UP | \
115 PAD_CTL_SPEED_MED | \
116 PAD_CTL_DSE_34ohm | \
119 static const iomux_v3_cfg_t const tx6_i2c_gpio_pads[] = {
121 MX6_PAD_EIM_D28__GPIO3_IO28 | MUX_CFG_SION | MUX_PAD_CTRL(TX6_I2C_GPIO_PAD_CTRL),
122 MX6_PAD_EIM_D21__GPIO3_IO21 | MUX_CFG_SION | MUX_PAD_CTRL(TX6_I2C_GPIO_PAD_CTRL),
125 static const iomux_v3_cfg_t const tx6_i2c_pads[] = {
127 MX6_PAD_EIM_D28__I2C1_SDA,
128 MX6_PAD_EIM_D21__I2C1_SCL,
131 static const struct gpio const tx6qdl_gpios[] = {
132 /* These two entries are used to forcefully reinitialize the I2C bus */
133 { TX6_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", },
134 { TX6_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", },
136 { TX6_RESET_OUT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "#RESET_OUT", },
137 { TX6_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
138 { TX6_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
139 { TX6_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
142 static int pmic_addr __data;
144 #if defined(CONFIG_SOC_MX6Q)
145 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21 0x020e00a4
146 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28 0x020e00c4
147 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21 0x020e03b8
148 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28 0x020e03d8
149 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21 0x020e0898
150 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28 0x020e089c
151 #define I2C1_SEL_INPUT_VAL 0
153 #if defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)
154 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21 0x020e0158
155 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28 0x020e0174
156 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21 0x020e0528
157 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28 0x020e0544
158 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21 0x020e0868
159 #define IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28 0x020e086c
160 #define I2C1_SEL_INPUT_VAL 1
167 static void tx6_i2c_recover(void)
171 #define SCL_BIT (1 << (TX6_I2C1_SCL_GPIO % 32))
172 #define SDA_BIT (1 << (TX6_I2C1_SDA_GPIO % 32))
174 if ((readl(GPIO3_BASE_ADDR + GPIO_PSR) &
175 (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT))
178 debug("Clearing I2C bus\n");
179 if (!(readl(GPIO3_BASE_ADDR + GPIO_PSR) & SCL_BIT)) {
180 printf("I2C SCL stuck LOW\n");
183 writel(readl(GPIO3_BASE_ADDR + GPIO_DR) | SCL_BIT,
184 GPIO3_BASE_ADDR + GPIO_DR);
185 writel(readl(GPIO3_BASE_ADDR + GPIO_DIR) | SCL_BIT,
186 GPIO3_BASE_ADDR + GPIO_DIR);
188 if (!(readl(GPIO3_BASE_ADDR + GPIO_PSR) & SDA_BIT)) {
189 printf("I2C SDA stuck LOW\n");
192 writel(readl(GPIO3_BASE_ADDR + GPIO_DIR) & ~SDA_BIT,
193 GPIO3_BASE_ADDR + GPIO_DIR);
194 writel(readl(GPIO3_BASE_ADDR + GPIO_DR) | SCL_BIT,
195 GPIO3_BASE_ADDR + GPIO_DR);
196 writel(readl(GPIO3_BASE_ADDR + GPIO_DIR) | SCL_BIT,
197 GPIO3_BASE_ADDR + GPIO_DIR);
199 imx_iomux_v3_setup_multiple_pads(tx6_i2c_gpio_pads,
200 ARRAY_SIZE(tx6_i2c_gpio_pads));
203 for (i = 0; i < 18; i++) {
204 u32 reg = readl(GPIO3_BASE_ADDR + GPIO_DR) ^ SCL_BIT;
206 debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear");
207 writel(reg, GPIO3_BASE_ADDR + GPIO_DR);
210 readl(GPIO3_BASE_ADDR + GPIO_PSR) & SDA_BIT)
215 u32 reg = readl(GPIO3_BASE_ADDR + GPIO_PSR);
217 if ((reg & (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT)) {
218 printf("I2C bus recovery succeeded\n");
220 printf("I2C bus recovery FAILED: %08x:%08x\n", reg,
224 debug("Setting up I2C Pads\n");
225 imx_iomux_v3_setup_multiple_pads(tx6_i2c_pads,
226 ARRAY_SIZE(tx6_i2c_pads));
229 /* placed in section '.data' to prevent overwriting relocation info
232 static u32 wrsr __data;
234 #define WRSR_POR (1 << 4)
235 #define WRSR_TOUT (1 << 1)
236 #define WRSR_SFTW (1 << 0)
238 static void print_reset_cause(void)
240 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
241 void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
245 printf("Reset cause: ");
247 srsr = readl(&src_regs->srsr);
248 wrsr = readw(wdt_base + 4);
250 if (wrsr & WRSR_POR) {
251 printf("%sPOR", dlm);
254 if (srsr & 0x00004) {
255 printf("%sCSU", dlm);
258 if (srsr & 0x00008) {
259 printf("%sIPP USER", dlm);
262 if (srsr & 0x00010) {
263 if (wrsr & WRSR_SFTW) {
264 printf("%sSOFT", dlm);
267 if (wrsr & WRSR_TOUT) {
268 printf("%sWDOG", dlm);
272 if (srsr & 0x00020) {
273 printf("%sJTAG HIGH-Z", dlm);
276 if (srsr & 0x00040) {
277 printf("%sJTAG SW", dlm);
280 if (srsr & 0x10000) {
281 printf("%sWARM BOOT", dlm);
290 static const char __data *tx6_mod_suffix;
292 #ifdef CONFIG_IMX6_THERMAL
294 #include <imx_thermal.h>
297 static void print_temperature(void)
299 struct udevice *thermal_dev;
300 int cpu_tmp, minc, maxc, ret;
301 char const *grade_str;
302 static u32 __data thermal_calib;
304 puts("Temperature: ");
305 switch (get_cpu_temp_grade(&minc, &maxc)) {
306 case TEMP_AUTOMOTIVE:
307 grade_str = "Automotive";
309 case TEMP_INDUSTRIAL:
310 grade_str = "Industrial";
312 case TEMP_EXTCOMMERCIAL:
313 grade_str = "Extended Commercial";
316 grade_str = "Commercial";
318 printf("%s grade (%dC to %dC)", grade_str, minc, maxc);
319 ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
321 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
324 printf(" at %dC", cpu_tmp);
326 puts(" - failed to read sensor data");
328 puts(" - no sensor device found");
331 if (fuse_read(1, 6, &thermal_calib) == 0) {
332 printf(" - calibration data 0x%08x\n", thermal_calib);
334 puts(" - Failed to read thermal calib fuse\n");
338 static inline void print_temperature(void)
345 u32 cpurev = get_cpu_rev();
348 switch ((cpurev >> 12) & 0xff) {
351 tx6_mod_suffix = "?";
355 tx6_mod_suffix = "U";
357 case MXC_CPU_MX6SOLO:
359 tx6_mod_suffix = "S";
363 tx6_mod_suffix = "Q";
367 printf("CPU: Freescale i.MX6%s rev%d.%d at %d MHz\n",
369 (cpurev & 0x000F0) >> 4,
370 (cpurev & 0x0000F) >> 0,
371 mxc_get_clock(MXC_ARM_CLK) / 1000000);
375 #ifdef CONFIG_MX6_TEMPERATURE_HOT
376 check_cpu_temperature(1);
382 /* serial port not initialized at this point */
383 int board_early_init_f(void)
388 #ifndef CONFIG_MX6_TEMPERATURE_HOT
389 static bool tx6_temp_check_enabled = true;
391 #define tx6_temp_check_enabled 0
394 #ifdef CONFIG_TX6_NAND
395 #define TX6_FLASH_SZ (CONFIG_SYS_NAND_BLOCKS / 1024 - 1)
397 #ifdef CONFIG_MMC_BOOT_SIZE
398 #define TX6_FLASH_SZ (CONFIG_MMC_BOOT_SIZE / 4096 + 2)
400 #define TX6_FLASH_SZ 2
402 #endif /* CONFIG_TX6_NAND */
404 #define TX6_DDR_SZ (ffs(CONFIG_SYS_SDRAM_BUS_WIDTH / 16) - 1)
406 static char tx6_mem_table[] = {
407 '4', /* 256MiB SDRAM 16bit; 128MiB NAND */
408 '1', /* 512MiB SDRAM 32bit; 128MiB NAND */
409 '0', /* 1GiB SDRAM 64bit; 128MiB NAND */
410 '?', /* 256MiB SDRAM 16bit; 256MiB NAND */
411 '?', /* 512MiB SDRAM 32bit; 256MiB NAND */
412 '2', /* 1GiB SDRAM 64bit; 256MiB NAND */
413 '?', /* 256MiB SDRAM 16bit; 4GiB eMMC */
414 '5', /* 512MiB SDRAM 32bit; 4GiB eMMC */
415 '3', /* 1GiB SDRAM 64bit; 4GiB eMMC */
416 '?', /* 256MiB SDRAM 16bit; 8GiB eMMC */
417 '?', /* 512MiB SDRAM 32bit; 8GiB eMMC */
418 '0', /* 1GiB SDRAM 64bit; 8GiB eMMC */
430 static inline char tx6_mem_suffix(void)
432 size_t mem_idx = (TX6_FLASH_SZ * 3) + TX6_DDR_SZ;
434 debug("TX6_DDR_SZ=%d TX6_FLASH_SZ=%d idx=%d\n",
435 TX6_DDR_SZ, TX6_FLASH_SZ, mem_idx);
437 if (mem_idx >= ARRAY_SIZE(tx6_mem_table))
440 return tx6_mem_table[mem_idx];
443 static int tx6_get_mod_rev(unsigned int pmic_id)
445 if (pmic_id < ARRAY_SIZE(tx6_mod_revs))
446 return tx6_mod_revs[pmic_id].rev;
451 static int tx6_pmic_probe(void)
455 debug("%s@%d: \n", __func__, __LINE__);
457 for (i = 0; i < ARRAY_SIZE(tx6_mod_revs); i++) {
458 u8 i2c_addr = tx6_mod_revs[i].addr;
459 int ret = i2c_probe(i2c_addr);
462 debug("I2C probe succeeded for addr 0x%02x\n", i2c_addr);
465 debug("I2C probe returned %d for addr 0x%02x\n", ret, i2c_addr);
473 u32 cpurev = get_cpu_rev();
474 int cpu_variant = (cpurev >> 12) & 0xff;
477 debug("%s@%d: \n", __func__, __LINE__);
479 pmic_id = tx6_pmic_probe();
480 if (pmic_id >= 0 && pmic_id < ARRAY_SIZE(tx6_mod_revs))
481 pmic_addr = tx6_mod_revs[pmic_id].addr;
483 printf("Board: Ka-Ro TX6%s-%d%d%d%c\n",
485 cpu_variant == MXC_CPU_MX6Q ? 1 : 8,
486 is_lvds(), tx6_get_mod_rev(pmic_id),
491 ret = gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios));
493 printf("Failed to request tx6qdl_gpios: %d\n", ret);
495 imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads));
497 /* Address of boot parameters */
498 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
499 gd->bd->bi_arch_number = -1;
501 if (ctrlc() || (wrsr & WRSR_TOUT)) {
502 if (wrsr & WRSR_TOUT)
503 printf("WDOG RESET detected; Skipping PMIC setup\n");
505 printf("<CTRL-C> detected; safeboot enabled\n");
506 #ifndef CONFIG_MX6_TEMPERATURE_HOT
507 tx6_temp_check_enabled = false;
512 ret = tx6_pmic_init(pmic_addr, NULL, 0);
514 printf("Failed to setup PMIC voltages: %d\n", ret);
522 debug("%s@%d: \n", __func__, __LINE__);
524 /* dram_init must store complete ramsize in gd->ram_size */
525 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
526 PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
530 void dram_init_banksize(void)
532 debug("%s@%d: \n", __func__, __LINE__);
534 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
535 gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
537 #if CONFIG_NR_DRAM_BANKS > 1
538 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
539 gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
544 #ifdef CONFIG_FSL_ESDHC
545 #define SD_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
546 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
549 static const iomux_v3_cfg_t mmc0_pads[] = {
550 MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
551 MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
552 MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
553 MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
554 MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
555 MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
557 MX6_PAD_SD3_CMD__GPIO7_IO02,
560 static const iomux_v3_cfg_t mmc1_pads[] = {
561 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
562 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
563 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
564 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
565 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
566 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
568 MX6_PAD_SD3_CLK__GPIO7_IO03,
571 #ifdef CONFIG_TX6_EMMC
572 static const iomux_v3_cfg_t mmc3_pads[] = {
573 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(SD_PAD_CTRL),
574 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(SD_PAD_CTRL),
575 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(SD_PAD_CTRL),
576 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(SD_PAD_CTRL),
577 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(SD_PAD_CTRL),
578 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(SD_PAD_CTRL),
580 MX6_PAD_NANDF_ALE__SD4_RESET | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |
585 static struct tx6_esdhc_cfg {
586 const iomux_v3_cfg_t *pads;
588 enum mxc_clock clkid;
589 struct fsl_esdhc_cfg cfg;
591 } tx6qdl_esdhc_cfg[] = {
592 #ifdef CONFIG_TX6_EMMC
595 .num_pads = ARRAY_SIZE(mmc3_pads),
596 .clkid = MXC_ESDHC4_CLK,
598 .esdhc_base = (void __iomem *)USDHC4_BASE_ADDR,
606 .num_pads = ARRAY_SIZE(mmc0_pads),
607 .clkid = MXC_ESDHC_CLK,
609 .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
612 .cd_gpio = IMX_GPIO_NR(7, 2),
616 .num_pads = ARRAY_SIZE(mmc1_pads),
617 .clkid = MXC_ESDHC2_CLK,
619 .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
622 .cd_gpio = IMX_GPIO_NR(7, 3),
626 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
628 return container_of(cfg, struct tx6_esdhc_cfg, cfg);
631 int board_mmc_getcd(struct mmc *mmc)
633 struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
635 if (cfg->cd_gpio < 0)
638 debug("SD card %d is %spresent (GPIO %d)\n",
639 cfg - tx6qdl_esdhc_cfg,
640 gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
642 return !gpio_get_value(cfg->cd_gpio);
645 int board_mmc_init(bd_t *bis)
649 debug("%s@%d: \n", __func__, __LINE__);
651 for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) {
653 struct tx6_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i];
656 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
657 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
659 if (cfg->cd_gpio >= 0) {
660 ret = gpio_request_one(cfg->cd_gpio,
661 GPIOFLAG_INPUT, "MMC CD");
663 printf("Error %d requesting GPIO%d_%d\n",
664 ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
669 debug("%s: Initializing MMC slot %d\n", __func__, i);
670 fsl_esdhc_initialize(bis, &cfg->cfg);
672 mmc = find_mmc_device(i);
675 if (board_mmc_getcd(mmc))
680 #endif /* CONFIG_CMD_MMC */
682 #ifdef CONFIG_FEC_MXC
688 int board_eth_init(bd_t *bis)
692 debug("%s@%d: \n", __func__, __LINE__);
694 /* delay at least 21ms for the PHY internal POR signal to deassert */
697 imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads,
698 ARRAY_SIZE(tx6qdl_fec_pads));
700 /* Deassert RESET to the external phy */
701 gpio_set_value(TX6_FEC_RST_GPIO, 1);
703 ret = cpu_eth_init(bis);
705 printf("cpu_eth_init() failed: %d\n", ret);
710 static void tx6_init_mac(void)
714 imx_get_mac_from_fuse(0, mac);
715 if (!is_valid_ethaddr(mac)) {
716 printf("No valid MAC address programmed\n");
720 printf("MAC addr from fuse: %pM\n", mac);
721 eth_setenv_enetaddr("ethaddr", mac);
724 static inline void tx6_init_mac(void)
727 #endif /* CONFIG_FEC_MXC */
735 static inline int calc_blink_rate(void)
737 if (!tx6_temp_check_enabled)
738 return CONFIG_SYS_HZ;
740 return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
741 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
742 (TEMPERATURE_HOT - TEMPERATURE_MIN);
745 void show_activity(int arg)
747 static int led_state = LED_STATE_INIT;
748 static int blink_rate;
751 if (led_state == LED_STATE_INIT) {
753 gpio_set_value(TX6_LED_GPIO, 1);
754 led_state = LED_STATE_ON;
755 blink_rate = calc_blink_rate();
757 if (get_timer(last) > blink_rate) {
758 blink_rate = calc_blink_rate();
759 last = get_timer_masked();
760 if (led_state == LED_STATE_ON) {
761 gpio_set_value(TX6_LED_GPIO, 0);
763 gpio_set_value(TX6_LED_GPIO, 1);
765 led_state = 1 - led_state;
770 static const iomux_v3_cfg_t stk5_pads[] = {
771 /* SW controlled LED on STK5 baseboard */
772 MX6_PAD_EIM_A18__GPIO2_IO20,
774 /* I2C bus on DIMM pins 40/41 */
775 MX6_PAD_GPIO_6__I2C3_SDA,
776 MX6_PAD_GPIO_3__I2C3_SCL,
778 /* TSC200x PEN IRQ */
779 MX6_PAD_EIM_D26__GPIO3_IO26,
781 /* EDT-FT5x06 Polytouch panel */
782 MX6_PAD_NANDF_CS2__GPIO6_IO15, /* IRQ */
783 MX6_PAD_EIM_A16__GPIO2_IO22, /* RESET */
784 MX6_PAD_EIM_A17__GPIO2_IO21, /* WAKE */
787 MX6_PAD_EIM_D31__GPIO3_IO31, /* VBUSEN */
788 MX6_PAD_EIM_D30__GPIO3_IO30, /* OC */
790 MX6_PAD_EIM_D23__GPIO3_IO23, /* USBOTG ID */
791 MX6_PAD_GPIO_7__GPIO1_IO07, /* VBUSEN */
792 MX6_PAD_GPIO_8__GPIO1_IO08, /* OC */
795 static const struct gpio stk5_gpios[] = {
796 { TX6_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
798 { IMX_GPIO_NR(3, 23), GPIOFLAG_INPUT, "USBOTG ID", },
799 { IMX_GPIO_NR(1, 8), GPIOFLAG_INPUT, "USBOTG OC", },
800 { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
801 { IMX_GPIO_NR(3, 30), GPIOFLAG_INPUT, "USBH1 OC", },
802 { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
806 vidinfo_t panel_info = {
807 /* set to max. size supported by SoC */
811 .vl_bpix = LCD_COLOR32, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
814 static struct fb_videomode tx6_fb_modes[] = {
815 #ifndef CONFIG_SYS_LVDS_IF
817 /* Standard VGA timing */
822 .pixclock = KHZ2PICOS(25175),
829 .sync = FB_SYNC_CLK_LAT_FALL,
832 /* Emerging ETV570 640 x 480 display. Syncs low active,
833 * DE high active, 115.2 mm x 86.4 mm display area
834 * VGA compatible timing
840 .pixclock = KHZ2PICOS(25175),
847 .sync = FB_SYNC_CLK_LAT_FALL,
850 /* Emerging ET0350G0DH6 320 x 240 display.
851 * 70.08 mm x 52.56 mm display area.
857 .pixclock = KHZ2PICOS(6500),
858 .left_margin = 68 - 34,
861 .upper_margin = 18 - 3,
864 .sync = FB_SYNC_CLK_LAT_FALL,
867 /* Emerging ET0430G0DH6 480 x 272 display.
868 * 95.04 mm x 53.856 mm display area.
874 .pixclock = KHZ2PICOS(9000),
883 /* Emerging ET0500G0DH6 800 x 480 display.
884 * 109.6 mm x 66.4 mm display area.
890 .pixclock = KHZ2PICOS(33260),
891 .left_margin = 216 - 128,
893 .right_margin = 1056 - 800 - 216,
894 .upper_margin = 35 - 2,
896 .lower_margin = 525 - 480 - 35,
897 .sync = FB_SYNC_CLK_LAT_FALL,
900 /* Emerging ETQ570G0DH6 320 x 240 display.
901 * 115.2 mm x 86.4 mm display area.
907 .pixclock = KHZ2PICOS(6400),
911 .upper_margin = 16, /* 15 according to datasheet */
912 .vsync_len = 3, /* TVP -> 1>x>5 */
913 .lower_margin = 4, /* 4.5 according to datasheet */
914 .sync = FB_SYNC_CLK_LAT_FALL,
917 /* Emerging ET0700G0DH6 800 x 480 display.
918 * 152.4 mm x 91.44 mm display area.
924 .pixclock = KHZ2PICOS(33260),
925 .left_margin = 216 - 128,
927 .right_margin = 1056 - 800 - 216,
928 .upper_margin = 35 - 2,
930 .lower_margin = 525 - 480 - 35,
931 .sync = FB_SYNC_CLK_LAT_FALL,
934 /* Emerging ET070001DM6 800 x 480 display.
935 * 152.4 mm x 91.44 mm display area.
937 .name = "ET070001DM6",
941 .pixclock = KHZ2PICOS(33260),
942 .left_margin = 216 - 128,
944 .right_margin = 1056 - 800 - 216,
945 .upper_margin = 35 - 2,
947 .lower_margin = 525 - 480 - 35,
952 /* HannStar HSD100PXN1
953 * 202.7m mm x 152.06 mm display area.
955 .name = "HSD100PXN1",
959 .pixclock = KHZ2PICOS(65000),
966 .sync = FB_SYNC_CLK_LAT_FALL,
970 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
978 .sync = FB_SYNC_CLK_LAT_FALL,
982 static int lcd_enabled = 1;
983 static int lcd_bl_polarity;
985 static int lcd_backlight_polarity(void)
987 return lcd_bl_polarity;
990 void lcd_enable(void)
993 * global variable from common/lcd.c
994 * Set to 0 here to prevent messages from going to LCD
995 * rather than serial console
1000 karo_load_splashimage(1);
1002 debug("Switching LCD on\n");
1003 gpio_set_value(TX6_LCD_PWR_GPIO, 1);
1005 gpio_set_value(TX6_LCD_RST_GPIO, 1);
1007 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
1008 lcd_backlight_polarity());
1012 void lcd_disable(void)
1015 printf("Disabling LCD\n");
1016 ipuv3_fb_shutdown();
1020 void lcd_panel_disable(void)
1023 debug("Switching LCD off\n");
1024 gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
1025 !lcd_backlight_polarity());
1026 gpio_set_value(TX6_LCD_RST_GPIO, 0);
1027 gpio_set_value(TX6_LCD_PWR_GPIO, 0);
1031 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
1033 MX6_PAD_EIM_D29__GPIO3_IO29,
1034 /* LCD POWER_ENABLE */
1035 MX6_PAD_EIM_EB3__GPIO2_IO31,
1036 /* LCD Backlight (PWM) */
1037 MX6_PAD_GPIO_1__GPIO1_IO01,
1039 #ifndef CONFIG_SYS_LVDS_IF
1041 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
1042 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
1043 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
1044 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
1045 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
1046 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
1047 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
1048 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
1049 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
1050 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
1051 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
1052 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
1053 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
1054 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
1055 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
1056 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
1057 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
1058 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
1059 MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
1060 MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
1061 MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
1062 MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
1063 MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
1064 MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
1065 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* HSYNC */
1066 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* VSYNC */
1067 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */
1068 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */
1072 static const struct gpio stk5_lcd_gpios[] = {
1073 { TX6_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
1074 { TX6_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
1075 { TX6_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
1078 void lcd_ctrl_init(void *lcdbase)
1080 int color_depth = 24;
1081 const char *video_mode = karo_get_vmode(getenv("video_mode"));
1085 struct fb_videomode *p = &tx6_fb_modes[0];
1086 struct fb_videomode fb_mode;
1087 int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
1090 unsigned long di_clk_rate = 65000000;
1093 debug("LCD disabled\n");
1097 if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1098 debug("Disabling LCD\n");
1100 setenv("splashimage", NULL);
1104 karo_fdt_move_fdt();
1105 lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1107 if (video_mode == NULL) {
1108 debug("Disabling LCD\n");
1113 if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1115 debug("Using video mode from FDT\n");
1117 if (fb_mode.xres > panel_info.vl_col ||
1118 fb_mode.yres > panel_info.vl_row) {
1119 printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1120 fb_mode.xres, fb_mode.yres,
1121 panel_info.vl_col, panel_info.vl_row);
1126 if (p->name != NULL)
1127 debug("Trying compiled-in video modes\n");
1128 while (p->name != NULL) {
1129 if (strcmp(p->name, vm) == 0) {
1130 debug("Using video mode: '%s'\n", p->name);
1137 debug("Trying to decode video_mode: '%s'\n", vm);
1138 while (*vm != '\0') {
1139 if (*vm >= '0' && *vm <= '9') {
1142 val = simple_strtoul(vm, &end, 0);
1145 if (val > panel_info.vl_col)
1146 val = panel_info.vl_col;
1148 panel_info.vl_col = val;
1150 } else if (!yres_set) {
1151 if (val > panel_info.vl_row)
1152 val = panel_info.vl_row;
1154 panel_info.vl_row = val;
1156 } else if (!bpp_set) {
1161 pix_fmt = IPU_PIX_FMT_LVDS888;
1175 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1176 end - vm, vm, color_depth);
1179 } else if (!refresh_set) {
1206 if (p->xres == 0 || p->yres == 0) {
1207 printf("Invalid video mode: %s\n", getenv("video_mode"));
1209 printf("Supported video modes are:");
1210 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
1211 printf(" %s", p->name);
1216 if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1217 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1218 p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1222 panel_info.vl_col = p->xres;
1223 panel_info.vl_row = p->yres;
1225 switch (color_depth) {
1227 panel_info.vl_bpix = LCD_COLOR8;
1230 panel_info.vl_bpix = LCD_COLOR16;
1233 panel_info.vl_bpix = LCD_COLOR32;
1236 p->pixclock = KHZ2PICOS(refresh *
1237 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1238 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1240 debug("Pixel clock set to %lu.%03lu MHz\n",
1241 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1243 if (p != &fb_mode) {
1246 debug("Creating new display-timing node from '%s'\n",
1248 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1250 printf("Failed to create new display-timing node from '%s': %d\n",
1254 gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1255 imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1256 ARRAY_SIZE(stk5_lcd_pads));
1258 lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
1259 switch (lcd_bus_width) {
1261 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
1265 pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
1270 pix_fmt = IPU_PIX_FMT_RGB565;
1276 printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
1281 int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
1282 int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
1286 if (lvds_chan_mask == 0) {
1287 printf("No LVDS channel active\n");
1292 gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
1293 if (lcd_bus_width == 24)
1294 gpr2 |= (1 << 5) | (1 << 7);
1295 gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
1296 gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
1297 debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
1298 writel(gpr2, IOMUXC_BASE_ADDR + 8);
1300 gpr3 = readl(IOMUXC_BASE_ADDR + 0xc);
1301 gpr3 &= ~((3 << 8) | (3 << 6));
1302 writel(gpr3, IOMUXC_BASE_ADDR + 0xc);
1304 if (karo_load_splashimage(0) == 0) {
1307 debug("Initializing LCD controller\n");
1308 ret = ipuv3_fb_init(p, 0, pix_fmt,
1309 is_lvds() ? DI_PCLK_LDB : DI_PCLK_PLL3,
1312 printf("Failed to initialize FB driver: %d\n", ret);
1316 debug("Skipping initialization of LCD controller\n");
1320 #define lcd_enabled 0
1321 #endif /* CONFIG_LCD */
1323 static void stk5_board_init(void)
1327 ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1329 printf("Failed to request stk5_gpios: %d\n", ret);
1332 imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1335 static void stk5v3_board_init(void)
1340 static void stk5v5_board_init(void)
1346 ret = gpio_request_one(IMX_GPIO_NR(4, 21), GPIOFLAG_OUTPUT_INIT_HIGH,
1347 "Flexcan Transceiver");
1349 printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
1353 imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO4_IO21);
1356 static void tx6qdl_set_cpu_clock(void)
1358 unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1360 if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1363 if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1364 printf("%s detected; skipping cpu clock change\n",
1365 (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1368 if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1369 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1370 printf("CPU clock set to %lu.%03lu MHz\n",
1371 cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1373 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1377 int board_late_init(void)
1380 const char *baseboard;
1382 debug("%s@%d: \n", __func__, __LINE__);
1386 if (tx6_temp_check_enabled)
1387 check_cpu_temperature(1);
1389 tx6qdl_set_cpu_clock();
1392 setenv_ulong("safeboot", 1);
1393 else if (wrsr & WRSR_TOUT)
1394 setenv_ulong("wdreset", 1);
1396 karo_fdt_move_fdt();
1398 baseboard = getenv("baseboard");
1402 printf("Baseboard: %s\n", baseboard);
1404 if (strncmp(baseboard, "stk5", 4) == 0) {
1405 if ((strlen(baseboard) == 4) ||
1406 strcmp(baseboard, "stk5-v3") == 0) {
1407 stk5v3_board_init();
1408 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1409 const char *otg_mode = getenv("otg_mode");
1411 if (otg_mode && strcmp(otg_mode, "host") == 0) {
1412 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1413 otg_mode, baseboard);
1414 setenv("otg_mode", "none");
1416 stk5v5_board_init();
1418 printf("WARNING: Unsupported STK5 board rev.: %s\n",
1422 printf("WARNING: Unsupported baseboard: '%s'\n",
1430 gpio_set_value(TX6_RESET_OUT_GPIO, 1);
1435 #ifdef CONFIG_SERIAL_TAG
1436 void get_board_serial(struct tag_serialnr *serialnr)
1438 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1439 struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1441 serialnr->low = readl(&fuse->cfg0);
1442 serialnr->high = readl(&fuse->cfg1);
1446 #if defined(CONFIG_OF_BOARD_SETUP)
1447 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1448 #include <jffs2/jffs2.h>
1449 #include <mtd_node.h>
1450 static struct node_info nodes[] = {
1451 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1454 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1457 static const char *tx6_touchpanels[] = {
1463 int ft_board_setup(void *blob, bd_t *bd)
1465 const char *baseboard = getenv("baseboard");
1466 int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1467 const char *video_mode = karo_get_vmode(getenv("video_mode"));
1470 ret = fdt_increase_size(blob, 4096);
1472 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1476 karo_fdt_enable_node(blob, "stk5led", 0);
1478 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1480 karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
1481 ARRAY_SIZE(tx6_touchpanels));
1482 karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1483 karo_fdt_fixup_flexcan(blob, stk5_v5);
1485 karo_fdt_update_fb_mode(blob, video_mode);
1489 #endif /* CONFIG_OF_BOARD_SETUP */