2 * Copyright (C) 2015 Lothar Waßmann <LW@KARO-electronics.de>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <fdt_support.h>
14 #include <fsl_esdhc.h>
22 #include <asm/arch/mx6-pins.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/hab.h>
25 #include <asm/arch/imx-regs.h>
26 #include <asm/arch/crm_regs.h>
27 #include <asm/arch/sys_proto.h>
29 #include "../common/karo.h"
32 #define __data __attribute__((section(".data")))
34 #define TX6UL_FEC_RST_GPIO IMX_GPIO_NR(5, 6)
35 #define TX6UL_FEC_PWR_GPIO IMX_GPIO_NR(5, 7)
36 #define TX6UL_FEC_INT_GPIO IMX_GPIO_NR(5, 5)
37 #define TX6UL_LED_GPIO IMX_GPIO_NR(5, 9)
39 #define TX6UL_LCD_PWR_GPIO IMX_GPIO_NR(5, 4)
40 #define TX6UL_LCD_RST_GPIO IMX_GPIO_NR(3, 4)
41 #define TX6UL_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(4, 16)
43 #define TX6UL_I2C1_SCL_GPIO CONFIG_SOFT_I2C_GPIO_SCL
44 #define TX6UL_I2C1_SDA_GPIO CONFIG_SOFT_I2C_GPIO_SDA
46 #define TX6UL_SD1_CD_GPIO IMX_GPIO_NR(4, 14)
48 #ifdef CONFIG_MX6_TEMPERATURE_MIN
49 #define TEMPERATURE_MIN CONFIG_MX6_TEMPERATURE_MIN
51 #define TEMPERATURE_MIN (-40)
53 #ifdef CONFIG_MX6_TEMPERATURE_HOT
54 #define TEMPERATURE_HOT CONFIG_MX6_TEMPERATURE_HOT
56 #define TEMPERATURE_HOT 80
59 DECLARE_GLOBAL_DATA_PTR;
61 #define MUX_CFG_SION IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0)
63 char __uboot_img_end[0] __attribute__((section(".__uboot_img_end")));
64 #ifdef CONFIG_SECURE_BOOT
65 char __csf_data[0] __attribute__((section(".__csf_data")));
68 static const iomux_v3_cfg_t const tx6ul_pads[] = {
70 #if CONFIG_MXC_UART_BASE == UART1_BASE
71 MX6_PAD_UART1_TX_DATA__UART1_DCE_TX,
72 MX6_PAD_UART1_RX_DATA__UART1_DCE_RX,
73 MX6_PAD_UART1_RTS_B__UART1_DCE_RTS,
74 MX6_PAD_UART1_CTS_B__UART1_DCE_CTS,
76 #if CONFIG_MXC_UART_BASE == UART2_BASE
77 MX6_PAD_UART2_TX_DATA__UART2_DCE_TX,
78 MX6_PAD_UART2_RX_DATA__UART2_DCE_RX,
79 MX6_PAD_UART3_RX_DATA__UART2_DCE_RTS,
80 MX6_PAD_UART3_TX_DATA__UART2_DCE_CTS,
82 #if CONFIG_MXC_UART_BASE == UART5_BASE
83 MX6_PAD_GPIO1_IO04__UART5_DCE_TX,
84 MX6_PAD_GPIO1_IO05__UART5_DCE_RX,
85 MX6_PAD_GPIO1_IO08__UART5_DCE_RTS,
86 MX6_PAD_GPIO1_IO09__UART5_DCE_CTS,
89 MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION |
90 MUX_PAD_CTRL(PAD_CTL_DSE_240ohm), /* I2C SCL */
91 MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION |
92 MUX_PAD_CTRL(PAD_CTL_DSE_240ohm | PAD_CTL_HYS |
93 PAD_CTL_ODE), /* I2C SDA */
95 /* FEC PHY GPIO functions */
96 MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_CFG_SION, /* PHY POWER */
97 MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 | MUX_CFG_SION, /* PHY RESET */
98 MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
99 PAD_CTL_DSE_40ohm), /* PHY INT */
102 #define TX6_ENET_PAD_CTRL (PAD_CTL_SPEED_HIGH | \
103 PAD_CTL_DSE_48ohm | \
104 PAD_CTL_PUS_100K_UP | \
106 #define TX6_GPIO_OUT_PAD_CTRL (PAD_CTL_SPEED_LOW | \
107 PAD_CTL_DSE_60ohm | \
109 #define TX6_GPIO_IN_PAD_CTRL (PAD_CTL_SPEED_LOW | \
112 static const iomux_v3_cfg_t const tx6ul_enet1_pads[] = {
114 MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(PAD_CTL_DSE_48ohm |
116 MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP |
119 MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_CFG_SION |
120 MUX_PAD_CTRL(PAD_CTL_SPEED_MED |
123 MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
124 MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
125 MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
126 MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
127 MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
128 MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
129 MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
131 MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_CFG_SION |
132 MUX_PAD_CTRL(PAD_CTL_SPEED_HIGH |
135 MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
136 MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
137 MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
138 MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
139 MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
140 MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
141 MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(TX6_ENET_PAD_CTRL),
144 #define TX6_I2C_PAD_CTRL (PAD_CTL_PUS_22K_UP | \
145 PAD_CTL_SPEED_MED | \
146 PAD_CTL_DSE_34ohm | \
149 static const iomux_v3_cfg_t const tx6_i2c_gpio_pads[] = {
151 MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 | MUX_CFG_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
152 MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_CFG_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
155 static const struct gpio const tx6ul_gpios[] = {
156 /* These two entries are used to forcefully reinitialize the I2C bus */
157 { TX6UL_I2C1_SCL_GPIO, GPIOFLAG_INPUT, "I2C1 SCL", },
158 { TX6UL_I2C1_SDA_GPIO, GPIOFLAG_INPUT, "I2C1 SDA", },
160 { TX6UL_FEC_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "FEC PHY PWR", },
161 { TX6UL_FEC_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "FEC PHY RESET", },
162 { TX6UL_FEC_INT_GPIO, GPIOFLAG_INPUT, "FEC PHY INT", },
169 static void tx6_i2c_recover(void)
173 #define SCL_BIT (1 << (TX6UL_I2C1_SCL_GPIO % 32))
174 #define SDA_BIT (1 << (TX6UL_I2C1_SDA_GPIO % 32))
175 #define I2C_GPIO_BASE (GPIO1_BASE_ADDR + TX6UL_I2C1_SCL_GPIO / 32 * 0x4000)
177 if ((readl(I2C_GPIO_BASE + GPIO_PSR) &
178 (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT))
181 debug("Clearing I2C bus\n");
182 if (!(readl(I2C_GPIO_BASE + GPIO_PSR) & SCL_BIT)) {
183 printf("I2C SCL stuck LOW\n");
186 writel(readl(I2C_GPIO_BASE + GPIO_DR) | SCL_BIT,
187 I2C_GPIO_BASE + GPIO_DR);
188 writel(readl(I2C_GPIO_BASE + GPIO_DIR) | SCL_BIT,
189 I2C_GPIO_BASE + GPIO_DIR);
191 if (!(readl(I2C_GPIO_BASE + GPIO_PSR) & SDA_BIT)) {
192 printf("I2C SDA stuck LOW\n");
195 writel(readl(I2C_GPIO_BASE + GPIO_DIR) & ~SDA_BIT,
196 I2C_GPIO_BASE + GPIO_DIR);
197 writel(readl(I2C_GPIO_BASE + GPIO_DR) | SCL_BIT,
198 I2C_GPIO_BASE + GPIO_DR);
199 writel(readl(I2C_GPIO_BASE + GPIO_DIR) | SCL_BIT,
200 I2C_GPIO_BASE + GPIO_DIR);
202 imx_iomux_v3_setup_multiple_pads(tx6_i2c_gpio_pads,
203 ARRAY_SIZE(tx6_i2c_gpio_pads));
206 for (i = 0; i < 18; i++) {
207 u32 reg = readl(I2C_GPIO_BASE + GPIO_DR) ^ SCL_BIT;
209 debug("%sing SCL\n", (reg & SCL_BIT) ? "Sett" : "Clear");
210 writel(reg, I2C_GPIO_BASE + GPIO_DR);
213 readl(I2C_GPIO_BASE + GPIO_PSR) & SDA_BIT)
218 u32 reg = readl(I2C_GPIO_BASE + GPIO_PSR);
220 if ((reg & (SCL_BIT | SDA_BIT)) == (SCL_BIT | SDA_BIT)) {
221 printf("I2C bus recovery succeeded\n");
223 printf("I2C bus recovery FAILED: %08x:%08x\n", reg,
229 /* placed in section '.data' to prevent overwriting relocation info
232 static u32 wrsr __data;
234 #define WRSR_POR (1 << 4)
235 #define WRSR_TOUT (1 << 1)
236 #define WRSR_SFTW (1 << 0)
238 static void print_reset_cause(void)
240 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
241 void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR;
245 printf("Reset cause: ");
247 srsr = readl(&src_regs->srsr);
248 wrsr = readw(wdt_base + 4);
250 if (wrsr & WRSR_POR) {
251 printf("%sPOR", dlm);
254 if (srsr & 0x00004) {
255 printf("%sCSU", dlm);
258 if (srsr & 0x00008) {
259 printf("%sIPP USER", dlm);
262 if (srsr & 0x00010) {
263 if (wrsr & WRSR_SFTW) {
264 printf("%sSOFT", dlm);
267 if (wrsr & WRSR_TOUT) {
268 printf("%sWDOG", dlm);
272 if (srsr & 0x00020) {
273 printf("%sJTAG HIGH-Z", dlm);
276 if (srsr & 0x00040) {
277 printf("%sJTAG SW", dlm);
280 if (srsr & 0x10000) {
281 printf("%sWARM BOOT", dlm);
290 #ifdef CONFIG_IMX6_THERMAL
292 #include <imx_thermal.h>
295 static void print_temperature(void)
297 struct udevice *thermal_dev;
298 int cpu_tmp, minc, maxc, ret;
299 char const *grade_str;
300 static u32 __data thermal_calib;
302 puts("Temperature: ");
303 switch (get_cpu_temp_grade(&minc, &maxc)) {
304 case TEMP_AUTOMOTIVE:
305 grade_str = "Automotive";
307 case TEMP_INDUSTRIAL:
308 grade_str = "Industrial";
310 case TEMP_EXTCOMMERCIAL:
311 grade_str = "Extended Commercial";
314 grade_str = "Commercial";
316 printf("%s grade (%dC to %dC)", grade_str, minc, maxc);
317 ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
319 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
322 printf(" at %dC", cpu_tmp);
324 puts(" - failed to read sensor data");
326 puts(" - no sensor device found");
329 if (fuse_read(1, 6, &thermal_calib) == 0) {
330 printf(" - calibration data 0x%08x\n", thermal_calib);
332 puts(" - Failed to read thermal calib fuse\n");
336 static inline void print_temperature(void)
343 u32 cpurev = get_cpu_rev();
346 switch ((cpurev >> 12) & 0xff) {
353 case MXC_CPU_MX6SOLO:
364 printf("CPU: Freescale i.MX6%s rev%d.%d at %d MHz\n",
366 (cpurev & 0x000F0) >> 4,
367 (cpurev & 0x0000F) >> 0,
368 mxc_get_clock(MXC_ARM_CLK) / 1000000);
372 #ifdef CONFIG_MX6_TEMPERATURE_HOT
373 check_cpu_temperature(1);
379 /* serial port not initialized at this point */
380 int board_early_init_f(void)
385 #ifndef CONFIG_MX6_TEMPERATURE_HOT
386 static bool tx6_temp_check_enabled = true;
388 #define tx6_temp_check_enabled 0
391 static inline u8 tx6ul_mem_suffix(void)
393 #ifdef CONFIG_TX6_NAND
401 #define VDD_RTC_VAL rn5t_mV_to_regval_rtc(3000)
402 #define VDD_CORE_VAL rn5t_mV_to_regval(1300) /* DCDC1 */
403 #define VDD_CORE_VAL_LP rn5t_mV_to_regval(900)
404 #define VDD_DDR_VAL rn5t_mV_to_regval(1350) /* DCDC3 */
405 #define VDD_DDR_VAL_LP rn5t_mV_to_regval(1350)
406 #define VDD_HIGH_VAL rn5t_mV_to_regval(3300) /* DCDC4 */
407 #define VDD_HIGH_VAL_LP rn5t_mV_to_regval(3300)
408 #define VDD_CSI_VAL rn5t_mV_to_regval2(3300) /* LDO4 */
409 #define VDD_CSI_VAL_LP rn5t_mV_to_regval2(3300)
411 static struct pmic_regs rn5t567_regs[] = {
412 { RN5T567_NOETIMSET, NOETIMSET_DIS_OFF_NOE_TIM | 0x5, },
413 { RN5T567_DC2CTL, DC2_DC2DIS, },
414 { RN5T567_DC1DAC, VDD_CORE_VAL, },
415 { RN5T567_DC3DAC, VDD_DDR_VAL, },
416 { RN5T567_DC4DAC, VDD_HIGH_VAL, },
417 { RN5T567_DC1DAC_SLP, VDD_CORE_VAL_LP, },
418 { RN5T567_DC3DAC_SLP, VDD_DDR_VAL_LP, },
419 { RN5T567_DC4DAC_SLP, VDD_HIGH_VAL_LP, },
420 { RN5T567_LDOEN1, 0x01f, ~0x1f, },
421 { RN5T567_LDOEN2, 0x10, ~0x30, },
422 { RN5T567_LDODIS, 0x00, },
423 { RN5T567_LDO4DAC, VDD_CSI_VAL, },
424 { RN5T567_LDORTC1DAC, VDD_RTC_VAL, },
425 { RN5T567_LDORTC1_SLOT, 0x0f, ~0x3f, },
428 static int pmic_addr __maybe_unused = 0x33;
434 debug("%s@%d: \n", __func__, __LINE__);
436 printf("Board: Ka-Ro TXUL-001%c\n",
441 ret = gpio_request_array(tx6ul_gpios, ARRAY_SIZE(tx6ul_gpios));
443 printf("Failed to request tx6ul_gpios: %d\n", ret);
445 imx_iomux_v3_setup_multiple_pads(tx6ul_pads, ARRAY_SIZE(tx6ul_pads));
447 /* Address of boot parameters */
448 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
449 gd->bd->bi_arch_number = -1;
451 if (ctrlc() || (wrsr & WRSR_TOUT)) {
452 if (wrsr & WRSR_TOUT)
453 printf("WDOG RESET detected; Skipping PMIC setup\n");
455 printf("<CTRL-C> detected; safeboot enabled\n");
456 #ifndef CONFIG_MX6_TEMPERATURE_HOT
457 tx6_temp_check_enabled = false;
462 ret = tx6_pmic_init(pmic_addr, rn5t567_regs, ARRAY_SIZE(rn5t567_regs));
464 printf("Failed to setup PMIC voltages: %d\n", ret);
472 debug("%s@%d: \n", __func__, __LINE__);
474 /* dram_init must store complete ramsize in gd->ram_size */
475 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
476 PHYS_SDRAM_1_SIZE * CONFIG_NR_DRAM_BANKS);
480 void dram_init_banksize(void)
482 debug("%s@%d: \n", __func__, __LINE__);
484 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
485 gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1,
487 #if CONFIG_NR_DRAM_BANKS > 1
488 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
489 gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2,
494 #ifdef CONFIG_FSL_ESDHC
495 #define TX6_SD_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
496 PAD_CTL_SPEED_MED | \
497 PAD_CTL_DSE_40ohm | \
500 static const iomux_v3_cfg_t mmc0_pads[] = {
501 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
502 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
503 MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
504 MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
505 MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
506 MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
508 MX6_PAD_NAND_CE1_B__GPIO4_IO14 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
511 #ifdef CONFIG_TX6_EMMC
512 static const iomux_v3_cfg_t mmc1_pads[] = {
513 MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
514 MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
515 MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
516 MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
517 MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
518 MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(TX6_SD_PAD_CTRL),
520 MX6_PAD_NAND_ALE__USDHC2_RESET_B | MUX_PAD_CTRL(PAD_CTL_PUS_47K_UP |
525 static struct tx6_esdhc_cfg {
526 const iomux_v3_cfg_t *pads;
528 enum mxc_clock clkid;
529 struct fsl_esdhc_cfg cfg;
531 } tx6ul_esdhc_cfg[] = {
532 #ifdef CONFIG_TX6_EMMC
535 .num_pads = ARRAY_SIZE(mmc1_pads),
536 .clkid = MXC_ESDHC2_CLK,
538 .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR,
546 .num_pads = ARRAY_SIZE(mmc0_pads),
547 .clkid = MXC_ESDHC_CLK,
549 .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR,
552 .cd_gpio = TX6UL_SD1_CD_GPIO,
556 static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
558 return container_of(cfg, struct tx6_esdhc_cfg, cfg);
561 int board_mmc_getcd(struct mmc *mmc)
563 struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv);
565 if (cfg->cd_gpio < 0)
568 debug("SD card %d is %spresent (GPIO %d)\n",
569 cfg - tx6ul_esdhc_cfg,
570 gpio_get_value(cfg->cd_gpio) ? "NOT " : "",
572 return !gpio_get_value(cfg->cd_gpio);
575 int board_mmc_init(bd_t *bis)
579 debug("%s@%d: \n", __func__, __LINE__);
581 for (i = 0; i < ARRAY_SIZE(tx6ul_esdhc_cfg); i++) {
583 struct tx6_esdhc_cfg *cfg = &tx6ul_esdhc_cfg[i];
586 cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
587 imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
589 if (cfg->cd_gpio >= 0) {
590 ret = gpio_request_one(cfg->cd_gpio,
591 GPIOFLAG_INPUT, "MMC CD");
593 printf("Error %d requesting GPIO%d_%d\n",
594 ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32);
599 debug("%s: Initializing MMC slot %d\n", __func__, i);
600 fsl_esdhc_initialize(bis, &cfg->cfg);
602 mmc = find_mmc_device(i);
605 if (board_mmc_getcd(mmc))
610 #endif /* CONFIG_CMD_MMC */
612 #ifdef CONFIG_FEC_MXC
618 int board_eth_init(bd_t *bis)
622 debug("%s@%d: \n", __func__, __LINE__);
624 /* delay at least 21ms for the PHY internal POR signal to deassert */
627 imx_iomux_v3_setup_multiple_pads(tx6ul_enet1_pads,
628 ARRAY_SIZE(tx6ul_enet1_pads));
630 /* Deassert RESET to the external phy */
631 gpio_set_value(TX6UL_FEC_RST_GPIO, 1);
633 if (getenv("ethaddr")) {
634 ret = fecmxc_initialize_multi(bis, 0, -1, ENET_BASE_ADDR);
636 printf("failed to initialize FEC0: %d\n", ret);
640 if (getenv("eth1addr")) {
641 ret = fecmxc_initialize_multi(bis, 1, -1, ENET2_BASE_ADDR);
643 printf("failed to initialize FEC1: %d\n", ret);
650 static void tx6_init_mac(void)
654 imx_get_mac_from_fuse(0, mac);
655 if (!is_valid_ethaddr(mac)) {
656 printf("No valid MAC address programmed\n");
660 printf("MAC addr from fuse: %pM\n", mac);
661 eth_setenv_enetaddr("ethaddr", mac);
663 imx_get_mac_from_fuse(1, mac);
664 eth_setenv_enetaddr("eth1addr", mac);
667 static inline void tx6_init_mac(void)
670 #endif /* CONFIG_FEC_MXC */
678 static inline int calc_blink_rate(void)
680 if (!tx6_temp_check_enabled)
681 return CONFIG_SYS_HZ;
683 return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 -
684 (check_cpu_temperature(0) - TEMPERATURE_MIN) * CONFIG_SYS_HZ /
685 (TEMPERATURE_HOT - TEMPERATURE_MIN);
688 void show_activity(int arg)
690 static int led_state = LED_STATE_INIT;
691 static int blink_rate;
694 if (led_state == LED_STATE_INIT) {
696 gpio_set_value(TX6UL_LED_GPIO, 1);
697 led_state = LED_STATE_ON;
698 blink_rate = calc_blink_rate();
700 if (get_timer(last) > blink_rate) {
701 blink_rate = calc_blink_rate();
702 last = get_timer_masked();
703 if (led_state == LED_STATE_ON) {
704 gpio_set_value(TX6UL_LED_GPIO, 0);
706 gpio_set_value(TX6UL_LED_GPIO, 1);
708 led_state = 1 - led_state;
713 static const iomux_v3_cfg_t stk5_pads[] = {
714 /* SW controlled LED on STK5 baseboard */
715 MX6_PAD_SNVS_TAMPER9__GPIO5_IO09,
717 /* I2C bus on DIMM pins 40/41 */
718 MX6_PAD_GPIO1_IO01__I2C2_SDA | MUX_MODE_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
719 MX6_PAD_GPIO1_IO00__I2C2_SCL | MUX_MODE_SION | MUX_PAD_CTRL(TX6_I2C_PAD_CTRL),
721 /* TSC200x PEN IRQ */
722 MX6_PAD_JTAG_TMS__GPIO1_IO11 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL),
724 /* EDT-FT5x06 Polytouch panel */
725 MX6_PAD_NAND_CS2__GPIO6_IO15 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* IRQ */
726 MX6_PAD_EIM_A16__GPIO2_IO22 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* RESET */
727 MX6_PAD_EIM_A17__GPIO2_IO21 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* WAKE */
730 MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* VBUSEN */
731 MX6_PAD_EIM_D30__GPIO3_IO30 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* OC */
733 MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* USBOTG ID */
734 MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL), /* VBUSEN */
735 MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(TX6_GPIO_IN_PAD_CTRL), /* OC */
739 static const struct gpio stk5_gpios[] = {
740 { TX6UL_LED_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "HEARTBEAT LED", },
742 { IMX_GPIO_NR(3, 23), GPIOFLAG_INPUT, "USBOTG ID", },
743 { IMX_GPIO_NR(1, 8), GPIOFLAG_INPUT, "USBOTG OC", },
744 { IMX_GPIO_NR(1, 7), GPIOFLAG_OUTPUT_INIT_LOW, "USBOTG VBUS enable", },
745 { IMX_GPIO_NR(3, 30), GPIOFLAG_INPUT, "USBH1 OC", },
746 { IMX_GPIO_NR(3, 31), GPIOFLAG_OUTPUT_INIT_LOW, "USBH1 VBUS enable", },
750 static u16 tx6_cmap[256];
751 vidinfo_t panel_info = {
752 /* set to max. size supported by SoC */
756 .vl_bpix = LCD_COLOR32, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
760 static struct fb_videomode tx6_fb_modes[] = {
761 #ifndef CONFIG_SYS_LVDS_IF
763 /* Standard VGA timing */
768 .pixclock = KHZ2PICOS(25175),
775 .sync = FB_SYNC_CLK_LAT_FALL,
778 /* Emerging ETV570 640 x 480 display. Syncs low active,
779 * DE high active, 115.2 mm x 86.4 mm display area
780 * VGA compatible timing
786 .pixclock = KHZ2PICOS(25175),
793 .sync = FB_SYNC_CLK_LAT_FALL,
796 /* Emerging ET0350G0DH6 320 x 240 display.
797 * 70.08 mm x 52.56 mm display area.
803 .pixclock = KHZ2PICOS(6500),
804 .left_margin = 68 - 34,
807 .upper_margin = 18 - 3,
810 .sync = FB_SYNC_CLK_LAT_FALL,
813 /* Emerging ET0430G0DH6 480 x 272 display.
814 * 95.04 mm x 53.856 mm display area.
820 .pixclock = KHZ2PICOS(9000),
829 /* Emerging ET0500G0DH6 800 x 480 display.
830 * 109.6 mm x 66.4 mm display area.
836 .pixclock = KHZ2PICOS(33260),
837 .left_margin = 216 - 128,
839 .right_margin = 1056 - 800 - 216,
840 .upper_margin = 35 - 2,
842 .lower_margin = 525 - 480 - 35,
843 .sync = FB_SYNC_CLK_LAT_FALL,
846 /* Emerging ETQ570G0DH6 320 x 240 display.
847 * 115.2 mm x 86.4 mm display area.
853 .pixclock = KHZ2PICOS(6400),
857 .upper_margin = 16, /* 15 according to datasheet */
858 .vsync_len = 3, /* TVP -> 1>x>5 */
859 .lower_margin = 4, /* 4.5 according to datasheet */
860 .sync = FB_SYNC_CLK_LAT_FALL,
863 /* Emerging ET0700G0DH6 800 x 480 display.
864 * 152.4 mm x 91.44 mm display area.
870 .pixclock = KHZ2PICOS(33260),
871 .left_margin = 216 - 128,
873 .right_margin = 1056 - 800 - 216,
874 .upper_margin = 35 - 2,
876 .lower_margin = 525 - 480 - 35,
877 .sync = FB_SYNC_CLK_LAT_FALL,
880 /* Emerging ET070001DM6 800 x 480 display.
881 * 152.4 mm x 91.44 mm display area.
883 .name = "ET070001DM6",
887 .pixclock = KHZ2PICOS(33260),
888 .left_margin = 216 - 128,
890 .right_margin = 1056 - 800 - 216,
891 .upper_margin = 35 - 2,
893 .lower_margin = 525 - 480 - 35,
898 /* HannStar HSD100PXN1
899 * 202.7m mm x 152.06 mm display area.
901 .name = "HSD100PXN1",
905 .pixclock = KHZ2PICOS(65000),
912 .sync = FB_SYNC_CLK_LAT_FALL,
916 /* unnamed entry for assigning parameters parsed from 'video_mode' string */
924 .sync = FB_SYNC_CLK_LAT_FALL,
928 static int lcd_enabled = 1;
929 static int lcd_bl_polarity;
931 static int lcd_backlight_polarity(void)
933 return lcd_bl_polarity;
936 void lcd_enable(void)
939 * global variable from common/lcd.c
940 * Set to 0 here to prevent messages from going to LCD
941 * rather than serial console
946 karo_load_splashimage(1);
948 debug("Switching LCD on\n");
949 gpio_set_value(TX6UL_LCD_PWR_GPIO, 1);
951 gpio_set_value(TX6UL_LCD_RST_GPIO, 1);
953 gpio_set_value(TX6UL_LCD_BACKLIGHT_GPIO,
954 lcd_backlight_polarity());
958 void lcd_disable(void)
961 printf("Disabling LCD\n");
962 panel_info.vl_row = 0;
967 static const iomux_v3_cfg_t stk5_lcd_pads[] = {
970 MX6_PAD_LCD_RESET__LCDIF_RESET,
971 /* LCD POWER_ENABLE */
972 MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL),
973 /* LCD Backlight (PWM) */
974 MX6_PAD_NAND_DQS__GPIO4_IO16 | MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL),
978 MX6_PAD_LCD_DATA00__LCDIF_DATA00,
979 MX6_PAD_LCD_DATA01__LCDIF_DATA01,
980 MX6_PAD_LCD_DATA02__LCDIF_DATA02,
981 MX6_PAD_LCD_DATA03__LCDIF_DATA03,
982 MX6_PAD_LCD_DATA04__LCDIF_DATA04,
983 MX6_PAD_LCD_DATA05__LCDIF_DATA05,
984 MX6_PAD_LCD_DATA06__LCDIF_DATA06,
985 MX6_PAD_LCD_DATA07__LCDIF_DATA07,
986 MX6_PAD_LCD_DATA08__LCDIF_DATA08,
987 MX6_PAD_LCD_DATA09__LCDIF_DATA09,
988 MX6_PAD_LCD_DATA10__LCDIF_DATA10,
989 MX6_PAD_LCD_DATA11__LCDIF_DATA11,
990 MX6_PAD_LCD_DATA12__LCDIF_DATA12,
991 MX6_PAD_LCD_DATA13__LCDIF_DATA13,
992 MX6_PAD_LCD_DATA14__LCDIF_DATA14,
993 MX6_PAD_LCD_DATA15__LCDIF_DATA15,
994 MX6_PAD_LCD_DATA16__LCDIF_DATA16,
995 MX6_PAD_LCD_DATA17__LCDIF_DATA17,
996 MX6_PAD_LCD_DATA18__LCDIF_DATA18,
997 MX6_PAD_LCD_DATA19__LCDIF_DATA19,
998 MX6_PAD_LCD_DATA20__LCDIF_DATA20,
999 MX6_PAD_LCD_DATA21__LCDIF_DATA21,
1000 MX6_PAD_LCD_DATA22__LCDIF_DATA22,
1001 MX6_PAD_LCD_DATA23__LCDIF_DATA23,
1002 MX6_PAD_LCD_HSYNC__LCDIF_HSYNC, /* HSYNC */
1003 MX6_PAD_LCD_VSYNC__LCDIF_VSYNC, /* VSYNC */
1004 MX6_PAD_LCD_ENABLE__LCDIF_ENABLE, /* OE_ACD */
1005 MX6_PAD_LCD_CLK__LCDIF_CLK, /* LSCLK */
1009 static const struct gpio stk5_lcd_gpios[] = {
1010 { TX6UL_LCD_RST_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD RESET", },
1011 { TX6UL_LCD_PWR_GPIO, GPIOFLAG_OUTPUT_INIT_LOW, "LCD POWER", },
1012 { TX6UL_LCD_BACKLIGHT_GPIO, GPIOFLAG_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", },
1015 void lcd_ctrl_init(void *lcdbase)
1017 int color_depth = 24;
1018 const char *video_mode = karo_get_vmode(getenv("video_mode"));
1022 struct fb_videomode *p = &tx6_fb_modes[0];
1023 struct fb_videomode fb_mode;
1024 int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
1027 debug("LCD disabled\n");
1031 if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1033 setenv("splashimage", NULL);
1037 karo_fdt_move_fdt();
1038 lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
1040 if (video_mode == NULL) {
1045 if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
1047 debug("Using video mode from FDT\n");
1049 if (fb_mode.xres > panel_info.vl_col ||
1050 fb_mode.yres > panel_info.vl_row) {
1051 printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n",
1052 fb_mode.xres, fb_mode.yres,
1053 panel_info.vl_col, panel_info.vl_row);
1058 if (p->name != NULL)
1059 debug("Trying compiled-in video modes\n");
1060 while (p->name != NULL) {
1061 if (strcmp(p->name, vm) == 0) {
1062 debug("Using video mode: '%s'\n", p->name);
1069 debug("Trying to decode video_mode: '%s'\n", vm);
1070 while (*vm != '\0') {
1071 if (*vm >= '0' && *vm <= '9') {
1074 val = simple_strtoul(vm, &end, 0);
1077 if (val > panel_info.vl_col)
1078 val = panel_info.vl_col;
1080 panel_info.vl_col = val;
1082 } else if (!yres_set) {
1083 if (val > panel_info.vl_row)
1084 val = panel_info.vl_row;
1086 panel_info.vl_row = val;
1088 } else if (!bpp_set) {
1099 printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n",
1100 end - vm, vm, color_depth);
1103 } else if (!refresh_set) {
1130 if (p->xres == 0 || p->yres == 0) {
1131 printf("Invalid video mode: %s\n", getenv("video_mode"));
1133 printf("Supported video modes are:");
1134 for (p = &tx6_fb_modes[0]; p->name != NULL; p++) {
1135 printf(" %s", p->name);
1140 if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) {
1141 printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n",
1142 p->xres, p->yres, panel_info.vl_col, panel_info.vl_row);
1146 panel_info.vl_col = p->xres;
1147 panel_info.vl_row = p->yres;
1149 switch (color_depth) {
1151 panel_info.vl_bpix = LCD_COLOR8;
1154 panel_info.vl_bpix = LCD_COLOR16;
1157 panel_info.vl_bpix = LCD_COLOR32;
1160 p->pixclock = KHZ2PICOS(refresh *
1161 (p->xres + p->left_margin + p->right_margin + p->hsync_len) *
1162 (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
1164 debug("Pixel clock set to %lu.%03lu MHz\n",
1165 PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
1167 if (p != &fb_mode) {
1170 debug("Creating new display-timing node from '%s'\n",
1172 ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
1174 printf("Failed to create new display-timing node from '%s': %d\n",
1178 gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
1179 imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
1180 ARRAY_SIZE(stk5_lcd_pads));
1182 debug("video format: %ux%u-%u@%u\n", p->xres, p->yres,
1183 color_depth, refresh);
1185 if (karo_load_splashimage(0) == 0) {
1188 /* setup env variable for mxsfb display driver */
1189 snprintf(vmode, sizeof(vmode),
1190 "x:%d,y:%d,le:%d,ri:%d,up:%d,lo:%d,hs:%d,vs:%d,sync:%d,pclk:%d,depth:%d",
1191 p->xres, p->yres, p->left_margin, p->right_margin,
1192 p->upper_margin, p->lower_margin, p->hsync_len,
1193 p->vsync_len, p->sync, p->pixclock, color_depth);
1194 setenv("videomode", vmode);
1196 debug("Initializing LCD controller\n");
1199 setenv("videomode", NULL);
1201 debug("Skipping initialization of LCD controller\n");
1205 #define lcd_enabled 0
1206 #endif /* CONFIG_LCD */
1208 static void stk5_board_init(void)
1212 ret = gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios));
1214 printf("Failed to request stk5_gpios: %d\n", ret);
1217 imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads));
1218 debug("%s@%d: \n", __func__, __LINE__);
1221 static void stk5v3_board_init(void)
1223 debug("%s@%d: \n", __func__, __LINE__);
1225 debug("%s@%d: \n", __func__, __LINE__);
1228 static void stk5v5_board_init(void)
1234 ret = gpio_request_one(IMX_GPIO_NR(3, 5), GPIOFLAG_OUTPUT_INIT_HIGH,
1235 "Flexcan Transceiver");
1237 printf("Failed to request Flexcan Transceiver GPIO: %d\n", ret);
1241 imx_iomux_v3_setup_pad(MX6_PAD_LCD_DATA00__GPIO3_IO05 |
1242 MUX_PAD_CTRL(TX6_GPIO_OUT_PAD_CTRL));
1245 static void tx6ul_set_cpu_clock(void)
1247 unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
1249 if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
1252 if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
1253 printf("%s detected; skipping cpu clock change\n",
1254 (wrsr & WRSR_TOUT) ? "WDOG RESET" : "<CTRL-C>");
1257 if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) {
1258 cpu_clk = mxc_get_clock(MXC_ARM_CLK);
1259 printf("CPU clock set to %lu.%03lu MHz\n",
1260 cpu_clk / 1000000, cpu_clk / 1000 % 1000);
1262 printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
1266 int board_late_init(void)
1269 const char *baseboard;
1271 debug("%s@%d: \n", __func__, __LINE__);
1275 if (tx6_temp_check_enabled)
1276 check_cpu_temperature(1);
1278 tx6ul_set_cpu_clock();
1281 setenv_ulong("safeboot", 1);
1282 else if (wrsr & WRSR_TOUT)
1283 setenv_ulong("wdreset", 1);
1285 karo_fdt_move_fdt();
1287 baseboard = getenv("baseboard");
1291 printf("Baseboard: %s\n", baseboard);
1293 if (strncmp(baseboard, "stk5", 4) == 0) {
1294 if ((strlen(baseboard) == 4) ||
1295 strcmp(baseboard, "stk5-v3") == 0) {
1296 stk5v3_board_init();
1297 } else if (strcmp(baseboard, "stk5-v5") == 0) {
1298 const char *otg_mode = getenv("otg_mode");
1300 if (otg_mode && strcmp(otg_mode, "host") == 0) {
1301 printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n",
1302 otg_mode, baseboard);
1303 setenv("otg_mode", "none");
1305 stk5v5_board_init();
1307 printf("WARNING: Unsupported STK5 board rev.: %s\n",
1311 printf("WARNING: Unsupported baseboard: '%s'\n",
1317 debug("%s@%d: \n", __func__, __LINE__);
1319 debug("%s@%d: \n", __func__, __LINE__);
1325 #ifdef CONFIG_SERIAL_TAG
1326 void get_board_serial(struct tag_serialnr *serialnr)
1328 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1329 struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs;
1331 serialnr->low = readl(&fuse->cfg0);
1332 serialnr->high = readl(&fuse->cfg1);
1336 #if defined(CONFIG_OF_BOARD_SETUP)
1337 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
1338 #include <jffs2/jffs2.h>
1339 #include <mtd_node.h>
1340 static struct node_info nodes[] = {
1341 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
1344 #define fdt_fixup_mtdparts(b,n,c) do { } while (0)
1347 static const char *tx6_touchpanels[] = {
1353 int ft_board_setup(void *blob, bd_t *bd)
1355 const char *baseboard = getenv("baseboard");
1356 int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
1357 const char *video_mode = karo_get_vmode(getenv("video_mode"));
1360 ret = fdt_increase_size(blob, 4096);
1362 printf("Failed to increase FDT size: %s\n", fdt_strerror(ret));
1366 karo_fdt_enable_node(blob, "stk5led", 0);
1368 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1370 karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
1371 ARRAY_SIZE(tx6_touchpanels));
1372 karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply");
1373 karo_fdt_fixup_flexcan(blob, stk5_v5);
1375 karo_fdt_update_fb_mode(blob, video_mode);
1379 #endif /* CONFIG_OF_BOARD_SETUP */