3 * Marvell Semiconductor <www.marvell.com>
4 * Prafulla Wadaskar <prafulla@marvell.com>
7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
10 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
38 #include <asm/arch/cpu.h>
39 #include <asm/arch/kirkwood.h>
40 #include <asm/arch/mpp.h>
42 #include "../common/common.h"
44 DECLARE_GLOBAL_DATA_PTR;
47 * BOCO FPGA definitions
50 #define REG_CTRL_H 0x02
51 #define MASK_WRL_UNITRUN 0x01
52 #define MASK_RBX_PGY_PRESENT 0x40
53 #define REG_IRQ_CIRQ2 0x2d
54 #define MASK_RBI_DEFECT_16 0x01
56 /* Multi-Purpose Pins Functionality configuration */
57 u32 kwmpp_config[] = {
66 #if defined(CONFIG_SOFT_I2C)
70 #if defined(CONFIG_HARD_I2C)
76 MPP12_GPO, /* Reserved */
79 MPP15_GPIO, /* Not used */
80 MPP16_GPIO, /* Not used */
81 MPP17_GPIO, /* Reserved */
98 MPP34_GPIO, /* CDL1 (input) */
99 MPP35_GPIO, /* CDL2 (input) */
100 MPP36_GPIO, /* MAIN_IRQ (input) */
101 MPP37_GPIO, /* BOARD_LED */
102 MPP38_GPIO, /* Piggy3 LED[1] */
103 MPP39_GPIO, /* Piggy3 LED[2] */
104 MPP40_GPIO, /* Piggy3 LED[3] */
105 MPP41_GPIO, /* Piggy3 LED[4] */
106 MPP42_GPIO, /* Piggy3 LED[5] */
107 MPP43_GPIO, /* Piggy3 LED[6] */
108 MPP44_GPIO, /* Piggy3 LED[7], BIST_EN_L */
109 MPP45_GPIO, /* Piggy3 LED[8] */
110 MPP46_GPIO, /* Reserved */
111 MPP47_GPIO, /* Reserved */
112 MPP48_GPIO, /* Reserved */
113 MPP49_GPIO, /* SW_INTOUTn */
117 #if defined(CONFIG_KM_MGCOGE3UN)
119 * Wait for startup OK from mgcoge3ne
121 int startup_allowed(void)
126 * Read CIRQ16 bit (bit 0)
128 if (i2c_read(BOCO, REG_IRQ_CIRQ2, 1, &buf, 1) != 0)
129 printf("%s: Error reading Boco\n", __func__);
131 if ((buf & MASK_RBI_DEFECT_16) == MASK_RBI_DEFECT_16)
137 #if (defined(CONFIG_KM_PIGGY4_88E6061)|defined(CONFIG_KM_PIGGY4_88E6352))
139 * All boards with PIGGY4 connected via a simple switch have ethernet always
142 int ethernet_present(void)
147 int ethernet_present(void)
152 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
153 printf("%s: Error reading Boco\n", __func__);
156 if ((buf & MASK_RBX_PGY_PRESENT) == MASK_RBX_PGY_PRESENT)
163 int initialize_unit_leds(void)
166 * Init the unit LEDs per default they all are
167 * ok apart from bootstat
171 if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
172 printf("%s: Error reading Boco\n", __func__);
175 buf |= MASK_WRL_UNITRUN;
176 if (i2c_write(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
177 printf("%s: Error writing Boco\n", __func__);
183 #if defined(CONFIG_BOOTCOUNT_LIMIT)
184 void set_bootcount_addr(void)
187 unsigned int bootcountaddr;
188 bootcountaddr = gd->ram_size - BOOTCOUNT_ADDR;
189 sprintf((char *)buf, "0x%x", bootcountaddr);
190 setenv("bootcountaddr", (char *)buf);
194 int misc_init_r(void)
199 str = getenv("mach_type");
201 mach_type = simple_strtoul(str, NULL, 10);
202 printf("Overwriting MACH_TYPE with %d!!!\n", mach_type);
203 gd->bd->bi_arch_number = mach_type;
205 #if defined(CONFIG_KM_MGCOGE3UN)
207 wait_for_ne = getenv("waitforne");
208 if (wait_for_ne != NULL) {
209 if (strcmp(wait_for_ne, "true") == 0) {
213 while (startup_allowed() == 0) {
215 (void) getc(); /* consume input */
222 puts("wait\b\b\b\b");
229 printf("\nAbort waiting for ne\n");
236 initialize_unit_leds();
238 #if defined(CONFIG_BOOTCOUNT_LIMIT)
239 set_bootcount_addr();
244 int board_early_init_f(void)
248 kirkwood_mpp_conf(kwmpp_config, NULL);
251 * The FLASH_GPIO_PIN switches between using a
252 * NAND or a SPI FLASH. Set this pin on start
255 tmp = readl(KW_GPIO0_BASE);
256 writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
257 tmp = readl(KW_GPIO0_BASE + 4);
258 writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4);
260 #if defined(CONFIG_SOFT_I2C)
261 /* init the GPIO for I2C Bitbang driver */
262 kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1);
263 kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1);
264 kw_gpio_direction_output(KM_KIRKWOOD_SDA_PIN, 0);
265 kw_gpio_direction_output(KM_KIRKWOOD_SCL_PIN, 0);
267 #if defined(CONFIG_SYS_EEPROM_WREN)
268 kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38);
269 kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1);
276 /* address of boot parameters */
277 gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
279 #if defined(CONFIG_KM_FPGA_CONFIG)
280 trigger_fpga_config();
286 int board_late_init(void)
288 #if defined(CONFIG_KMCOGE5UN)
289 /* I/O pin to erase flash RGPP09 = MPP43 */
290 #define KM_FLASH_ERASE_ENABLE 43
291 u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE);
293 /* if pin 1 do full erase */
294 if (dip_switch != 0) {
295 /* start bootloader */
296 puts("DIP: Enabled\n");
297 setenv("actual_bank", "0");
301 #if defined(CONFIG_KM_FPGA_CONFIG)
302 wait_for_fpga_config();
304 toggle_eeprom_spi_bus();
309 int board_spi_claim_bus(struct spi_slave *slave)
311 kw_gpio_set_value(KM_FLASH_GPIO_PIN, 0);
316 void board_spi_release_bus(struct spi_slave *slave)
318 kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1);
323 /* dram_init must store complete ramsize in gd->ram_size */
325 gd->ram_size = get_ram_size((void *)kw_sdram_bar(0),
330 void dram_init_banksize(void)
334 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
335 gd->bd->bi_dram[i].start = kw_sdram_bar(i);
336 gd->bd->bi_dram[i].size = get_ram_size((long *)kw_sdram_bar(i),
341 #if (defined(CONFIG_KM_PIGGY4_88E6061))
343 #define PHY_LED_SEL_REG 0x18
344 #define PHY_LED0_LINK (0x5)
345 #define PHY_LED1_ACT (0x8<<4)
346 #define PHY_LED2_INT (0xe<<8)
347 #define PHY_SPEC_CTRL_REG 0x1c
348 #define PHY_RGMII_CLK_STABLE (0x1<<10)
349 #define PHY_CLSA (0x1<<1)
351 /* Configure and enable MV88E3018 PHY */
354 char *name = "egiga0";
357 if (miiphy_set_current_dev(name))
360 /* RGMII clk transition on data stable */
361 if (!miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, ®))
362 printf("Error reading PHY spec ctrl reg\n");
363 if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG,
364 reg | PHY_RGMII_CLK_STABLE | PHY_CLSA))
365 printf("Error writing PHY spec ctrl reg\n");
368 if (!miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG,
369 PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT))
370 printf("Error writing PHY LED reg\n");
373 miiphy_reset(name, CONFIG_PHY_BASE_ADR);
376 /* Configure and enable MV88E1118 PHY on the piggy*/
379 char *name = "egiga0";
381 if (miiphy_set_current_dev(name))
385 miiphy_reset(name, CONFIG_PHY_BASE_ADR);
390 #if defined(CONFIG_HUSH_INIT_VAR)
391 int hush_init_var(void)
398 #if defined(CONFIG_BOOTCOUNT_LIMIT)
399 const ulong patterns[] = { 0x00000000,
404 const ulong NBR_OF_PATTERNS = ARRAY_SIZE(patterns);
405 const ulong OFFS_PATTERN = 3;
406 const ulong REPEAT_PATTERN = 1000;
408 void bootcount_store(ulong a)
414 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
415 size += gd->bd->bi_dram[i].size;
416 save_addr = (ulong *)(size - BOOTCOUNT_ADDR);
417 writel(a, save_addr);
418 writel(BOOTCOUNT_MAGIC, &save_addr[1]);
420 for (i = 0; i < REPEAT_PATTERN; i++)
421 writel(patterns[i % NBR_OF_PATTERNS],
422 &save_addr[i+OFFS_PATTERN]);
426 ulong bootcount_load(void)
433 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
434 size += gd->bd->bi_dram[i].size;
435 save_addr = (ulong *)(size - BOOTCOUNT_ADDR);
437 counter = readl(&save_addr[0]);
439 /* Is the counter reliable, check in the big pattern for bit errors */
440 for (i = 0; (i < REPEAT_PATTERN) && (counter != 0); i++) {
441 tmp = readl(&save_addr[i+OFFS_PATTERN]);
442 if (tmp != patterns[i % NBR_OF_PATTERNS])
449 #if defined(CONFIG_SOFT_I2C)
450 void set_sda(int state)
456 void set_scl(int state)
469 return kw_gpio_get_value(KM_KIRKWOOD_SCL_PIN) ? 1 : 0;
473 #if defined(CONFIG_POST)
475 #define KM_POST_EN_L 44
476 #define POST_WORD_OFF 8
478 int post_hotkeys_pressed(void)
480 #if defined(CONFIG_KM_COGE5UN)
481 return kw_gpio_get_value(KM_POST_EN_L);
483 return !kw_gpio_get_value(KM_POST_EN_L);
487 ulong post_word_load(void)
489 void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
490 return in_le32(addr);
493 void post_word_store(ulong value)
495 void* addr = (void *) (gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
496 out_le32(addr, value);
499 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
501 *vstart = CONFIG_SYS_SDRAM_BASE;
503 /* we go up to relocation plus a 1 MB margin */
504 *size = CONFIG_SYS_TEXT_BASE - (1<<20);
510 #if defined(CONFIG_SYS_EEPROM_WREN)
511 int eeprom_write_enable(unsigned dev_addr, int state)
513 kw_gpio_set_value(KM_KIRKWOOD_ENV_WP, !state);
515 return !kw_gpio_get_value(KM_KIRKWOOD_ENV_WP);