3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
30 extern int ivm_read_eeprom (void);
32 DECLARE_GLOBAL_DATA_PTR;
34 const uint sdram_table[] =
36 0x0f07fc04, 0x0ffffc04, 0x00bdfc04, 0x0ff77c00,
37 0x1ffffc05, 0xfffffc04, 0xfffffc04, 0xfffffc04,
39 0x0f07fc04, 0x0ffffc04, 0x00bdfc04, 0x00fffc00,
40 0x00fffc00, 0x00fffc00, 0x0ff77c00, 0x1ffffc05,
41 /* 0x10 Load mode register */
42 0x0ffffc34, 0x0ff57c04, 0x0ffffc04, 0x1ffffc05,
43 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
44 /* 0x18 Single Write */
45 0x0f07fc04, 0x0ffffc00, 0x00bd7c04, 0x0ffffc04,
46 0x0ff77c04, 0x1ffffc05, 0xfffffc04, 0xfffffc04,
47 /* 0x20 Burst Write */
48 0x0f07fc04, 0x0ffffc00, 0x00bd7c00, 0x00fffc00,
49 0x00fffc00, 0x00fffc04, 0x0ffffc04, 0x0ff77c04,
50 0x1ffffc05, 0xfffffc04, 0xfffffc04, 0xfffffc04,
51 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
52 /* 0x30 Precharge all and Refresh */
53 0x0ff77c04, 0x0ffffc04, 0x0ff5fc84, 0x0ffffc04,
54 0x0ffffc04, 0x0ffffc84, 0x1ffffc05, 0xfffffc04,
55 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
57 0x7ffffc04, 0xfffffc07, 0xfffffc04, 0xfffffc04,
62 puts ("Board: Keymile mgsuvd\n");
66 phys_size_t initdram (int board_type)
68 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
69 volatile memctl8xx_t *memctl = &immap->im_memctl;
72 upmconfig (UPMB, (uint *) sdram_table,
73 sizeof (sdram_table) / sizeof (uint));
76 * Preliminary prescaler for refresh (depends on number of
77 * banks): This value is selected for four cycles every 62.4 us
78 * with two SDRAM banks or four cycles every 31.2 us with one
79 * bank. It will be adjusted after memory sizing.
81 memctl->memc_mptpr = CONFIG_SYS_MPTPR;
84 * The following value is used as an address (i.e. opcode) for
85 * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
86 * the port size is 32bit the SDRAM does NOT "see" the lower two
87 * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
90 * | | | | +- Burst Length = 4
91 * | | | +----- Burst Type = Sequential
92 * | | +------- CAS Latency = 2
93 * | +----------- Operating Mode = Standard
94 * +-------------- Write Burst Mode = Programmed Burst Length
96 memctl->memc_mar = CONFIG_SYS_MAR;
99 * Map controller banks 1 to the SDRAM banks 1 at
100 * preliminary addresses - these have to be modified after the
101 * SDRAM size has been determined.
103 memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
104 memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
106 memctl->memc_mbmr = CONFIG_SYS_MBMR & (~(MBMR_PTBE)); /* no refresh yet */
110 /* perform SDRAM initializsation sequence */
112 memctl->memc_mcr = 0x80802830; /* SDRAM bank 0 */
114 memctl->memc_mcr = 0x80802110; /* SDRAM bank 0 - execute twice */
117 memctl->memc_mbmr |= MBMR_PTBE; /* enable refresh */
122 * Check Bank 0 Memory Size for re-configuration
125 size = get_ram_size(SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
129 debug ("SDRAM Bank 0: %ld MB\n", size >> 20);
135 * Early board initalization.
137 int board_early_init_r(void)
139 /* setup the UPIOx */
140 *(char *)(CONFIG_SYS_PIGGY_BASE + 0x02) = 0xc0;
141 *(char *)(CONFIG_SYS_PIGGY_BASE + 0x03) = 0x35;
145 int hush_init_var (void)
151 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
153 * update "memory" property in the blob
155 void ft_blob_update (void *blob, bd_t *bd)
157 int ret, nodeoffset = 0;
158 ulong brg_data[1] = {0};
159 ulong memory_data[2] = {0};
160 ulong flash_data[4] = {0};
162 memory_data[0] = cpu_to_be32 (bd->bi_memstart);
163 memory_data[1] = cpu_to_be32 (bd->bi_memsize);
165 nodeoffset = fdt_path_offset (blob, "/memory");
166 if (nodeoffset >= 0) {
167 ret = fdt_setprop (blob, nodeoffset, "reg", memory_data,
168 sizeof (memory_data));
170 printf("ft_blob_update(): cannot set /memory/reg "
171 "property err:%s\n", fdt_strerror (ret));
173 /* memory node is required in dts */
174 printf("ft_blob_update(): cannot find /memory node "
175 "err:%s\n", fdt_strerror (nodeoffset));
178 flash_data[2] = cpu_to_be32 (bd->bi_flashstart);
179 flash_data[3] = cpu_to_be32 (bd->bi_flashsize);
180 nodeoffset = fdt_path_offset (blob, "/localbus");
181 if (nodeoffset >= 0) {
182 ret = fdt_setprop (blob, nodeoffset, "ranges", flash_data,
183 sizeof (flash_data));
185 printf("ft_blob_update(): cannot set /localbus/ranges "
186 "property err:%s\n", fdt_strerror (ret));
188 /* memory node is required in dts */
189 printf("ft_blob_update(): cannot find /localbus node "
190 "err:%s\n", fdt_strerror (nodeoffset));
193 brg_data[0] = cpu_to_be32 (bd->bi_busfreq);
194 nodeoffset = fdt_path_offset (blob, "/soc/cpm");
195 if (nodeoffset >= 0) {
196 ret = fdt_setprop (blob, nodeoffset, "brg-frequency", brg_data,
199 printf("ft_blob_update(): cannot set /soc/cpm/brg-frequency "
200 "property err:%s\n", fdt_strerror(ret));
202 /* memory node is required in dts */
203 printf("ft_blob_update(): cannot find /soc/cpm node "
204 "err:%s\n", fdt_strerror (nodeoffset));
207 nodeoffset = fdt_path_offset (blob, "/soc/cpm/ethernet");
208 if (nodeoffset >= 0) {
209 ret = fdt_setprop (blob, nodeoffset, "mac-address", bd->bi_enetaddr,
212 printf("ft_blob_update(): cannot set /soc/cpm/scc/mac-address "
213 "property err:%s\n", fdt_strerror (ret));
215 /* memory node is required in dts */
216 printf("ft_blob_update(): cannot find /soc/cpm/ethernet node "
217 "err:%s\n", fdt_strerror (nodeoffset));
221 void ft_board_setup(void *blob, bd_t *bd)
223 ft_cpu_setup (blob, bd);
224 ft_blob_update (blob, bd);
226 #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
228 int i2c_soft_read_pin (void)
232 *(unsigned short *)(I2C_BASE_DIR) &= ~SDA_CONF;
234 val = *(unsigned char *)(I2C_BASE_PORT);
236 return ((val & SDA_BIT) == SDA_BIT);