2 * (C) Copyright 2003-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 //###CHD: es gibt eigentlich kein DDR bei uns -> weg damit!; dto. PCI!
32 #if defined(CONFIG_MPC5200_DDR)
33 #include "mt46v16m16-75.h"
35 //#include "mt48lc16m16a2-75.h"
36 #include "mt48lc8m32b2-6-7.h"
39 //###CHD: wenn RAMBOOT gehen wuerde, ....
41 static void sdram_start (int hi_addr)
43 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
45 /* unlock mode register */
46 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
47 __asm__ volatile ("sync");
49 /* precharge all banks */
50 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
51 __asm__ volatile ("sync");
54 /* set mode register: extended mode */
55 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
56 __asm__ volatile ("sync");
58 /* set mode register: reset DLL */
59 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
60 __asm__ volatile ("sync");
63 /* precharge all banks */
64 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
65 __asm__ volatile ("sync");
68 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
69 __asm__ volatile ("sync");
71 /* set mode register */
72 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
73 __asm__ volatile ("sync");
75 /* normal operation */
76 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
77 __asm__ volatile ("sync");
82 * ATTENTION: Although partially referenced initdram does NOT make real use
83 * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
84 * is something else than 0x00000000.
87 #if defined(CONFIG_MPC5200)
88 long int initdram (int board_type)
95 /* setup SDRAM chip selects */
96 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
97 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
98 __asm__ volatile ("sync");
100 /* setup config registers */
101 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
102 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
103 __asm__ volatile ("sync");
107 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
108 __asm__ volatile ("sync");
111 /* find RAM size using SDRAM CS0 only */
113 test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
115 test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
123 /* memory smaller than 1MB is impossible */
124 if (dramsize < (1 << 20)) {
128 /* set SDRAM CS0 size according to the amount of RAM found */
130 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
132 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
135 /* let SDRAM CS1 start right after CS0 */
136 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
138 /* find RAM size using SDRAM CS1 only */
141 test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
144 test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
153 /* memory smaller than 1MB is impossible */
154 if (dramsize2 < (1 << 20)) {
158 /* set SDRAM CS1 size according to the amount of RAM found */
160 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
161 | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
163 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
166 #else /* CFG_RAMBOOT */
168 /* retrieve size of memory connected to SDRAM CS0 */
169 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
170 if (dramsize >= 0x13) {
171 dramsize = (1 << (dramsize - 0x13)) << 20;
176 /* retrieve size of memory connected to SDRAM CS1 */
177 dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
178 if (dramsize2 >= 0x13) {
179 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
184 #endif /* CFG_RAMBOOT */
186 return dramsize + dramsize2;
189 //###CHD: sowas gibt es bei usn nicht!
190 #elif defined(CONFIG_MGT5100)
192 long int initdram (int board_type)
198 /* setup and enable SDRAM chip selects */
199 *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
200 *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
201 *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
202 __asm__ volatile ("sync");
204 /* setup config registers */
205 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
206 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
208 /* address select register */
209 *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
210 __asm__ volatile ("sync");
214 test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
216 test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
224 /* set SDRAM end address according to size */
225 *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
227 #else /* CFG_RAMBOOT */
229 /* Retrieve amount of SDRAM available */
230 dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
232 #endif /* CFG_RAMBOOT */
238 #error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
241 int checkboard (void)
243 puts("Board: Bluetechnix DevMPC5200Leica \n");
245 #if defined(CONFIG_MPC5200)
246 puts ("Board: MicroSys PM520 \n");
247 #elif defined(CONFIG_MGT5100)
248 puts ("Board: MicroSys PM510 \n");
253 void flash_preinit(void)
256 * Now, when we are in RAM, enable flash write
257 * access for detection process.
258 * Note that CS_BOOT cannot be cleared when
259 * executing in flash.
261 #if defined(CONFIG_MGT5100)
262 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
263 *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
265 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
268 void flash_afterinit(ulong start, ulong size)
270 #if defined(CONFIG_BOOT_ROM)
272 *(vu_long *)MPC5XXX_CS1_START =
274 *(vu_long *)MPC5XXX_CS1_STOP =
275 STOP_REG(start, size);
278 *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
280 *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
281 STOP_REG(start, size);
286 extern flash_info_t flash_info[]; /* info for FLASH chips */
288 int misc_init_r (void)
290 DECLARE_GLOBAL_DATA_PTR;
291 /* adjust flash start */
292 gd->bd->bi_flashstart = flash_info[0].start[0];
297 static struct pci_controller hose;
299 extern void pci_mpc5xxx_init(struct pci_controller *);
301 void pci_init_board(void)
303 pci_mpc5xxx_init(&hose);
307 #if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
309 void init_ide_reset (void)
311 debug ("init_ide_reset\n");
315 void ide_set_reset (int idereset)
317 debug ("ide_reset(%d)\n", idereset);
320 #endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
322 #if (CONFIG_COMMANDS & CFG_CMD_DOC)
323 extern void doc_probe (ulong physadr);
326 doc_probe (CFG_DOC_BASE);