2 * (C) Copyright 2002,2003, Motorola Inc.
3 * Xianghua Xiao, (X.Xiao@motorola.com)
5 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 extern long int spd_sdram (void);
30 #include <asm/processor.h>
31 #include <asm/immap_85xx.h>
34 long int fixed_sdram (void);
36 /* MPC8540ADS Board Status & Control Registers */
38 typedef struct bscr_ {
50 int board_early_init_f (void)
52 #if defined(CONFIG_PCI)
53 volatile immap_t *immr = (immap_t *)CFG_IMMR;
54 volatile ccsr_pcix_t *pci = &immr->im_pcix;
56 pci->peer &= 0xffffffdf; /* disable master abort */
65 get_sys_info (&sysinfo);
67 printf ("Board: Motorola MPC8540ADS Board\n");
68 printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
69 printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
70 printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
71 if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \
72 || (CFG_LBC_LCRR & 0x0f) == 8) {
73 printf ("\tLBC: %lu MHz\n", sysinfo.freqSystemBus / 1000000 /(CFG_LBC_LCRR & 0x0f));
75 printf("\tLBC: unknown\n");
77 printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
81 long int initdram (int board_type)
84 extern long spd_sdram (void);
85 volatile immap_t *immap = (immap_t *)CFG_IMMR;
86 #if !defined(CONFIG_RAM_AS_FLASH)
87 volatile ccsr_lbc_t *lbc= &immap->im_lbc;
91 #if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
92 volatile ccsr_gur_t *gur= &immap->im_gur;
94 #if defined(CONFIG_DDR_DLL)
97 /* Work around to stabilize DDR DLL */
98 temp_ddrdll = gur->ddrdllcr;
99 gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
100 asm("sync;isync;msync");
103 #if defined(CONFIG_SPD_EEPROM)
104 dram_size = spd_sdram ();
106 dram_size = fixed_sdram ();
109 #if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */
110 get_sys_info(&sysinfo);
111 /* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
112 if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) {
113 lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000;
115 #if defined(CONFIG_MPC85xx_REV1) /* need change CLKDIV before enable DLL */
116 lbc->lcrr = 0x10000004; /* default CLKDIV is 8, change it to 4 temporarily */
118 lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
120 temp_lbcdll = gur->lbcdllcr;
121 gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
122 asm("sync;isync;msync");
124 lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */
125 lbc->br2 = CFG_BR2_PRELIM;
126 lbc->lbcr = CFG_LBC_LBCR;
127 lbc->lsdmr = CFG_LBC_LSDMR_1;
129 (unsigned int) * (ulong *)0 = 0x000000ff;
130 lbc->lsdmr = CFG_LBC_LSDMR_2;
132 (unsigned int) * (ulong *)0 = 0x000000ff;
133 lbc->lsdmr = CFG_LBC_LSDMR_3;
135 (unsigned int) * (ulong *)0 = 0x000000ff;
136 lbc->lsdmr = CFG_LBC_LSDMR_4;
138 (unsigned int) * (ulong *)0 = 0x000000ff;
139 lbc->lsdmr = CFG_LBC_LSDMR_5;
141 lbc->lsrt = CFG_LBC_LSRT;
143 lbc->mrtpr = CFG_LBC_MRTPR;
147 #if defined(CONFIG_DDR_ECC)
149 /* Initialize all of memory for ECC, then
153 volatile immap_t *immap = (immap_t *)CFG_IMMR;
154 volatile ccsr_ddr_t *ddr= &immap->im_ddr;
156 for (*p = 0; p < (uint *)(8 * 1024); p++) {
157 if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
158 *p = (unsigned int)0xdeadbeef;
159 if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
163 dma_xfer((uint *)0x2000,0x2000,(uint *)0);
165 dma_xfer((uint *)0x4000,0x4000,(uint *)0);
167 dma_xfer((uint *)0x8000,0x8000,(uint *)0);
169 dma_xfer((uint *)0x10000,0x10000,(uint *)0);
171 dma_xfer((uint *)0x20000,0x20000,(uint *)0);
173 dma_xfer((uint *)0x40000,0x40000,(uint *)0);
175 dma_xfer((uint *)0x80000,0x80000,(uint *)0);
177 dma_xfer((uint *)0x100000,0x100000,(uint *)0);
179 dma_xfer((uint *)0x200000,0x200000,(uint *)0);
181 dma_xfer((uint *)0x400000,0x400000,(uint *)0);
183 for (i = 1; i < dram_size / 0x800000; i++) {
184 dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0);
187 /* Enable errors for ECC */
188 ddr->err_disable = 0x00000000;
189 asm("sync;isync;msync");
197 #if defined(CFG_DRAM_TEST)
200 uint *pstart = (uint *) CFG_MEMTEST_START;
201 uint *pend = (uint *) CFG_MEMTEST_END;
204 printf("SDRAM test phase 1:\n");
205 for (p = pstart; p < pend; p++)
208 for (p = pstart; p < pend; p++) {
209 if (*p != 0xaaaaaaaa) {
210 printf ("SDRAM test fails at: %08x\n", (uint) p);
215 printf("SDRAM test phase 2:\n");
216 for (p = pstart; p < pend; p++)
219 for (p = pstart; p < pend; p++) {
220 if (*p != 0x55555555) {
221 printf ("SDRAM test fails at: %08x\n", (uint) p);
226 printf("SDRAM test passed.\n");
232 #if !defined(CONFIG_SPD_EEPROM)
233 /*************************************************************************
234 * fixed sdram init -- doesn't use serial presence detect.
235 ************************************************************************/
236 long int fixed_sdram (void)
239 volatile immap_t *immap = (immap_t *)CFG_IMMR;
240 volatile ccsr_ddr_t *ddr= &immap->im_ddr;
242 ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
243 ddr->cs0_config = CFG_DDR_CS0_CONFIG;
244 ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
245 ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
246 ddr->sdram_mode = CFG_DDR_MODE;
247 ddr->sdram_interval = CFG_DDR_INTERVAL;
248 #if defined (CONFIG_DDR_ECC)
249 ddr->err_disable = 0x0000000D;
250 ddr->err_sbe = 0x00ff0000;
252 asm("sync;isync;msync");
254 #if defined (CONFIG_DDR_ECC)
255 /* Enable ECC checking */
256 ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
258 ddr->sdram_cfg = CFG_DDR_CONTROL;
260 asm("sync; isync; msync");
263 return (CFG_SDRAM_SIZE * 1024 * 1024);
265 #endif /* !defined(CONFIG_SPD_EEPROM) */