2 * Copyright 2004 Freescale Semiconductor.
3 * (C) Copyright 2002,2003, Motorola Inc.
4 * Xianghua Xiao, (X.Xiao@motorola.com)
6 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/processor.h>
30 #include <asm/immap_85xx.h>
33 #if defined(CONFIG_DDR_ECC)
34 extern void ddr_enable_ecc(unsigned int dram_size);
37 extern long int spd_sdram(void);
39 void sdram_init(void);
40 long int fixed_sdram(void);
43 int board_early_init_f (void)
45 #if defined(CONFIG_PCI)
46 volatile immap_t *immr = (immap_t *) CFG_IMMR;
47 volatile ccsr_pcix_t *pci = &immr->im_pcix;
49 pci->peer &= 0xffffffdf; /* disable master abort */
60 printf(" PCI1: 32 bit, %d MHz (compiled)\n",
61 CONFIG_SYS_CLK_FREQ / 1000000);
63 printf(" PCI1: disabled\n");
71 initdram(int board_type)
74 extern long spd_sdram (void);
75 volatile immap_t *immap = (immap_t *)CFG_IMMR;
77 puts("Initializing\n");
79 #if defined(CONFIG_DDR_DLL)
81 volatile ccsr_gur_t *gur= &immap->im_gur;
85 * Work around to stabilize DDR DLL
87 temp_ddrdll = gur->ddrdllcr;
88 gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
89 asm("sync;isync;msync");
93 #if defined(CONFIG_SPD_EEPROM)
94 dram_size = spd_sdram ();
96 dram_size = fixed_sdram ();
99 #if defined(CONFIG_DDR_ECC)
101 * Initialize and enable DDR ECC.
103 ddr_enable_ecc(dram_size);
117 * Initialize SDRAM memory on the Local Bus.
120 void sdram_init (void)
122 #if !defined(CONFIG_RAM_AS_FLASH)
124 volatile immap_t *immap = (immap_t *) CFG_IMMR;
125 volatile ccsr_lbc_t *lbc = &immap->im_lbc;
126 uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE;
129 print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
132 * LocalBus SDRAM is not emulating flash.
136 * Fix Local Bus clock glitch. Errata LBC11.
138 * If localbus freq is less than 66Mhz, use bypass mode,
140 * lcrr is the local-bus clock ratio register.
142 get_sys_info (&sysinfo);
143 if (sysinfo.freqSystemBus / (CFG_LBC_LCRR & 0x0f) < 66000000) {
144 lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff) | 0x80000000;
148 * On REV1 boards, need to change CLKDIV before enable DLL.
149 * Default CLKDIV is 8, change it to 4 temporarily.
151 volatile ccsr_gur_t *gur = &immap->im_gur;
152 uint pvr = get_pvr ();
153 uint temp_lbcdll = 0;
155 if (pvr == PVR_85xx_REV1) {
156 lbc->lcrr = 0x10000004;
159 /* FIXME: jdl Should lcrr have 0x8000000 OR'ed in here too? */
160 lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
162 temp_lbcdll = gur->lbcdllcr;
163 gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16) | 0x80000000;
164 asm ("sync;isync;msync");
168 * Setup SDRAM Base and Option Registers
170 lbc->or2 = CFG_OR2_PRELIM;
171 lbc->br2 = CFG_BR2_PRELIM;
172 lbc->lbcr = CFG_LBC_LBCR;
175 lbc->lsrt = CFG_LBC_LSRT;
176 lbc->mrtpr = CFG_LBC_MRTPR;
180 * Configure the SDRAM controller.
182 lbc->lsdmr = CFG_LBC_LSDMR_1;
185 ppcDcbf ((unsigned long) sdram_addr);
188 lbc->lsdmr = CFG_LBC_LSDMR_2;
191 ppcDcbf ((unsigned long) sdram_addr);
194 lbc->lsdmr = CFG_LBC_LSDMR_3;
197 ppcDcbf ((unsigned long) sdram_addr);
200 lbc->lsdmr = CFG_LBC_LSDMR_4;
203 ppcDcbf ((unsigned long) sdram_addr);
206 lbc->lsdmr = CFG_LBC_LSDMR_5;
209 ppcDcbf ((unsigned long) sdram_addr);
216 #if defined(CFG_DRAM_TEST)
219 uint *pstart = (uint *) CFG_MEMTEST_START;
220 uint *pend = (uint *) CFG_MEMTEST_END;
223 printf("SDRAM test phase 1:\n");
224 for (p = pstart; p < pend; p++)
227 for (p = pstart; p < pend; p++) {
228 if (*p != 0xaaaaaaaa) {
229 printf ("SDRAM test fails at: %08x\n", (uint) p);
234 printf("SDRAM test phase 2:\n");
235 for (p = pstart; p < pend; p++)
238 for (p = pstart; p < pend; p++) {
239 if (*p != 0x55555555) {
240 printf ("SDRAM test fails at: %08x\n", (uint) p);
245 printf("SDRAM test passed.\n");
251 #if !defined(CONFIG_SPD_EEPROM)
252 /*************************************************************************
253 * fixed sdram init -- doesn't use serial presence detect.
254 ************************************************************************/
255 long int fixed_sdram (void)
258 volatile immap_t *immap = (immap_t *)CFG_IMMR;
259 volatile ccsr_ddr_t *ddr= &immap->im_ddr;
261 ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
262 ddr->cs0_config = CFG_DDR_CS0_CONFIG;
263 ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
264 ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
265 ddr->sdram_mode = CFG_DDR_MODE;
266 ddr->sdram_interval = CFG_DDR_INTERVAL;
267 #if defined (CONFIG_DDR_ECC)
268 ddr->err_disable = 0x0000000D;
269 ddr->err_sbe = 0x00ff0000;
271 asm("sync;isync;msync");
273 #if defined (CONFIG_DDR_ECC)
274 /* Enable ECC checking */
275 ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
277 ddr->sdram_cfg = CFG_DDR_CONTROL;
279 asm("sync; isync; msync");
282 return CFG_SDRAM_SIZE * 1024 * 1024;
284 #endif /* !defined(CONFIG_SPD_EEPROM) */