3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
5 * (C) Copyright 2001-2002
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 DECLARE_GLOBAL_DATA_PTR;
33 static long int dram_size (long int, long int *, long int);
35 #define _NOT_USED_ 0xFFFFFFFF
37 const uint sdram_table[] = {
38 #if (MPC8XX_SPEED <= 50000000L)
40 * Single Read. (Offset 0 in UPMA RAM)
42 0x0F07EC04, 0x01BBD804, 0x1FF7F440, 0xFFFFFC07,
46 * SDRAM Initialization (offset 5 in UPMA RAM)
48 * This is no UPM entry point. The following definition uses
49 * the remaining space to establish an initialization
50 * sequence, which is executed by a RUN command.
53 0x1FE7F434, 0xEFABE834, 0x1FA7D435,
56 * Burst Read. (Offset 8 in UPMA RAM)
58 0x0F07EC04, 0x10EFDC04, 0xF0AFFC00, 0xF0AFFC00,
59 0xF1AFFC00, 0xFFAFFC40, 0xFFAFFC07, 0xFFFFFFFF,
60 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
61 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
64 * Single Write. (Offset 18 in UPMA RAM)
66 0x0E07E804, 0x01BBD000, 0x1FF7F447, 0xFFFFFFFF,
67 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
70 * Burst Write. (Offset 20 in UPMA RAM)
72 0x0E07E800, 0x10EFD400, 0xF0AFFC00, 0xF0AFFC00,
73 0xF1AFFC47, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
74 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
75 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
78 * Refresh (Offset 30 in UPMA RAM)
80 0x1FF7DC84, 0xFFFFFC04, 0xFFFFFC84, 0xFFFFFC07,
81 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
82 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
85 * Exception. (Offset 3c in UPMA RAM)
87 0x7FFFFC07, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF
91 * Single Read. (Offset 0 in UPMA RAM)
93 0x1F07FC04, 0xEEAFEC04, 0x11AFDC04, 0xEFBBF800,
97 * SDRAM Initialization (offset 5 in UPMA RAM)
99 * This is no UPM entry point. The following definition uses
100 * the remaining space to establish an initialization
101 * sequence, which is executed by a RUN command.
104 0x1FF7F434, 0xEFEBE834, 0x1FB7D435,
107 * Burst Read. (Offset 8 in UPMA RAM)
109 0x1F07FC04, 0xEEAFEC04, 0x10AFDC04, 0xF0AFFC00,
110 0xF0AFFC00, 0xF1AFFC00, 0xEFBBF800, 0x1FF7F447,
111 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
112 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
115 * Single Write. (Offset 18 in UPMA RAM)
117 0x1F07FC04, 0xEEAFE800, 0x01BBD004, 0x1FF7F447,
118 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
121 * Burst Write. (Offset 20 in UPMA RAM)
123 0x1F07FC04, 0xEEAFE800, 0x10AFD400, 0xF0AFFC00,
124 0xF0AFFC00, 0xE1BBF804, 0x1FF7F447, _NOT_USED_,
125 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
126 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
129 * Refresh (Offset 30 in UPMA RAM)
131 0x1FF7DC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
132 0xFFFFFC84, 0xFFFFFC07,
133 _NOT_USED_, _NOT_USED_, _NOT_USED_,
134 _NOT_USED_, _NOT_USED_, _NOT_USED_,
137 * Exception. (Offset 3c in UPMA RAM)
139 0x7FFFFC07, /* last */
140 _NOT_USED_, _NOT_USED_, _NOT_USED_,
144 /* ------------------------------------------------------------------------- */
148 * Check Board Identity:
152 int checkboard (void)
154 printf ("Board: Nexus NX823");
158 /* ------------------------------------------------------------------------- */
160 phys_size_t initdram (int board_type)
162 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
163 volatile memctl8xx_t *memctl = &immap->im_memctl;
164 long int size_b0, size_b1, size8, size9;
166 upmconfig (UPMA, (uint *) sdram_table,
167 sizeof (sdram_table) / sizeof (uint));
170 * Up to 2 Banks of 64Mbit x 2 devices
171 * Initial builds only have 1
173 memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_4K;
174 memctl->memc_mar = 0x00000088;
177 * Map controller SDRAM bank 0
179 memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
180 memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
181 memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
185 * Map controller SDRAM bank 1
187 memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
188 memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
191 * Perform SDRAM initializsation sequence
193 memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */
195 memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - execute twice */
198 memctl->memc_mcr = 0x80004105; /* SDRAM bank 1 */
200 memctl->memc_mcr = 0x80004230; /* SDRAM bank 1 - execute twice */
203 memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
207 * Preliminary prescaler for refresh (depends on number of
208 * banks): This value is selected for four cycles every 62.4 us
209 * with two SDRAM banks or four cycles every 31.2 us with one
210 * bank. It will be adjusted after memory sizing.
212 memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
214 memctl->memc_mar = 0x00000088;
218 * Check Bank 0 Memory Size for re-configuration
222 size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE1_PRELIM,
230 size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE1_PRELIM,
233 if (size8 < size9) { /* leave configuration at 9 columns */
235 /* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
236 } else { /* back to 8 columns */
238 memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
240 /* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
244 * Check Bank 1 Memory Size
245 * use current column settings
246 * [9 column SDRAM may also be used in 8 column mode,
247 * but then only half the real size will be used.]
249 size_b1 = dram_size (memctl->memc_mamr, (long *) SDRAM_BASE2_PRELIM,
251 /* debug ("SDRAM Bank 1: %ld MB\n", size8 >> 20); */
256 * Adjust refresh rate depending on SDRAM type, both banks
257 * For types > 128 MBit leave it at the current (fast) rate
259 if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
260 /* reduce to 15.6 us (62.4 us / quad) */
261 memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
266 * Final mapping: map bigger bank first
268 if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */
271 ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
273 (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
277 * Position Bank 0 immediately above Bank 1
280 ((-size_b0) & 0xFFFF0000) |
281 CONFIG_SYS_OR_TIMING_SDRAM;
283 ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA |
294 memctl->memc_br1 = 0;
296 /* adjust refresh rate depending on SDRAM type, one bank */
297 reg = memctl->memc_mptpr;
298 reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
299 memctl->memc_mptpr = reg;
302 } else { /* SDRAM Bank 0 is bigger - map first */
305 ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
307 (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
311 * Position Bank 1 immediately above Bank 0
314 ((-size_b1) & 0xFFFF0000) |
315 CONFIG_SYS_OR_TIMING_SDRAM;
317 ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA |
328 memctl->memc_br2 = 0;
330 /* adjust refresh rate depending on SDRAM type, one bank */
331 reg = memctl->memc_mptpr;
332 reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
333 memctl->memc_mptpr = reg;
339 return (size_b0 + size_b1);
342 /* ------------------------------------------------------------------------- */
345 * Check memory range for valid RAM. A simple memory test determines
346 * the actually available RAM size between addresses `base' and
347 * `base + maxsize'. Some (not all) hardware errors are detected:
348 * - short between address lines
349 * - short between data lines
352 static long int dram_size (long int mamr_value, long int *base,
355 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
356 volatile memctl8xx_t *memctl = &immap->im_memctl;
358 memctl->memc_mamr = mamr_value;
360 return (get_ram_size (base, maxsize));
365 int misc_init_r (void)
368 u_char *e = gd->bd->bi_enetaddr;
370 /* save serial numbre from flash (uniquely programmed) */
371 my_sernum = malloc (8);
372 memcpy (my_sernum, gd->bd->bi_sernum, 8);
374 /* save env variables according to sernum */
375 sprintf (tmp, "%08lx%08lx", my_sernum[0], my_sernum[1]);
376 setenv ("serial#", tmp);
378 sprintf (tmp, "%02x:%02x:%02x:%02x:%02x:%02x", e[0], e[1], e[2], e[3],
380 setenv ("ethaddr", tmp);
384 void load_sernum_ethaddr (void)
389 for (i = 0; i < 8; i++) {
390 bd->bi_sernum[i] = *(u_char *) (CONFIG_SYS_FLASH_SN_BASE + i);
392 bd->bi_enetaddr[0] = 0x10;
393 bd->bi_enetaddr[1] = 0x20;
394 bd->bi_enetaddr[2] = 0x30;
395 bd->bi_enetaddr[3] = bd->bi_sernum[1] << 4 | bd->bi_sernum[2];
396 bd->bi_enetaddr[4] = bd->bi_sernum[5];
397 bd->bi_enetaddr[5] = bd->bi_sernum[6];