4 * Board functions for Phytec phyCORE-AM335x (pcm051) based boards
6 * Copyright (C) 2013 Lemonage Software GmbH
7 * Author Lars Poeschel <poeschel@lemonage.de>
9 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch/cpu.h>
16 #include <asm/arch/hardware.h>
17 #include <asm/arch/omap.h>
18 #include <asm/arch/ddr_defs.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/gpio.h>
21 #include <asm/arch/mmc_host_def.h>
22 #include <asm/arch/sys_proto.h>
31 DECLARE_GLOBAL_DATA_PTR;
33 /* MII mode defines */
34 #define RMII_RGMII2_MODE_ENABLE 0x49
36 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
38 #ifdef CONFIG_SPL_BUILD
41 #define DDR_CLK_MHZ 303 /* DDR_DPLL_MULT value */
43 #define OSC (V_OSCK/1000000)
44 const struct dpll_params dpll_ddr = {
45 DDR_CLK_MHZ, OSC-1, 1, -1, -1, -1, -1};
47 const struct dpll_params *get_dpll_ddr_params(void)
53 static const struct ddr_data ddr3_data = {
54 .datardsratio0 = MT41J256M8HX15E_RD_DQS,
55 .datawdsratio0 = MT41J256M8HX15E_WR_DQS,
56 .datafwsratio0 = MT41J256M8HX15E_PHY_FIFO_WE,
57 .datawrsratio0 = MT41J256M8HX15E_PHY_WR_DATA,
58 .datadldiff0 = PHY_DLL_LOCK_DIFF,
61 static const struct cmd_control ddr3_cmd_ctrl_data = {
62 .cmd0csratio = MT41J256M8HX15E_RATIO,
63 .cmd0dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
64 .cmd0iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
66 .cmd1csratio = MT41J256M8HX15E_RATIO,
67 .cmd1dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
68 .cmd1iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
70 .cmd2csratio = MT41J256M8HX15E_RATIO,
71 .cmd2dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
72 .cmd2iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
75 static struct emif_regs ddr3_emif_reg_data = {
76 .sdram_config = MT41J256M8HX15E_EMIF_SDCFG,
77 .ref_ctrl = MT41J256M8HX15E_EMIF_SDREF,
78 .sdram_tim1 = MT41J256M8HX15E_EMIF_TIM1,
79 .sdram_tim2 = MT41J256M8HX15E_EMIF_TIM2,
80 .sdram_tim3 = MT41J256M8HX15E_EMIF_TIM3,
81 .zq_config = MT41J256M8HX15E_ZQ_CFG,
82 .emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY |
88 config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data,
89 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
92 static const struct ddr_data ddr3_data = {
93 .datardsratio0 = MT41K256M16HA125E_RD_DQS,
94 .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
95 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
96 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
97 .datadldiff0 = PHY_DLL_LOCK_DIFF,
100 static const struct cmd_control ddr3_cmd_ctrl_data = {
101 .cmd0csratio = MT41K256M16HA125E_RATIO,
102 .cmd0dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
103 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
105 .cmd1csratio = MT41K256M16HA125E_RATIO,
106 .cmd1dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
107 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
109 .cmd2csratio = MT41K256M16HA125E_RATIO,
110 .cmd2dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
111 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
114 static struct emif_regs ddr3_emif_reg_data = {
115 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
116 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
117 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
118 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
119 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
120 .zq_config = MT41K256M16HA125E_ZQ_CFG,
121 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY |
125 void sdram_init(void)
127 config_ddr(DDR_CLK_MHZ, MT41K256M16HA125E_IOCTRL_VALUE, &ddr3_data,
128 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
132 void set_uart_mux_conf(void)
134 enable_uart0_pin_mux();
137 void set_mux_conf_regs(void)
139 /* Initalize the board header */
140 enable_i2c0_pin_mux();
141 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
143 enable_board_pin_mux();
148 * Basic board specific setup. Pinmux has been handled already.
152 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
154 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
159 #ifdef CONFIG_DRIVER_TI_CPSW
160 static void cpsw_control(int enabled)
162 /* VTP can be added here */
167 static struct cpsw_slave_data cpsw_slaves[] = {
169 .slave_reg_ofs = 0x208,
170 .sliver_reg_ofs = 0xd80,
172 .phy_if = PHY_INTERFACE_MODE_RGMII,
175 .slave_reg_ofs = 0x308,
176 .sliver_reg_ofs = 0xdc0,
178 .phy_if = PHY_INTERFACE_MODE_RGMII,
182 static struct cpsw_platform_data cpsw_data = {
183 .mdio_base = CPSW_MDIO_BASE,
184 .cpsw_base = CPSW_BASE,
187 .cpdma_reg_ofs = 0x800,
189 .slave_data = cpsw_slaves,
190 .ale_reg_ofs = 0xd00,
192 .host_port_reg_ofs = 0x108,
193 .hw_stats_reg_ofs = 0x900,
194 .bd_ram_ofs = 0x2000,
195 .mac_control = (1 << 5),
196 .control = cpsw_control,
198 .version = CPSW_CTRL_VERSION_2,
202 #if defined(CONFIG_DRIVER_TI_CPSW) || \
203 (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
204 int board_eth_init(bd_t *bis)
207 #ifdef CONFIG_DRIVER_TI_CPSW
209 uint32_t mac_hi, mac_lo;
211 if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
212 printf("<ethaddr> not set. Reading from E-fuse\n");
213 /* try reading mac address from efuse */
214 mac_lo = readl(&cdev->macid0l);
215 mac_hi = readl(&cdev->macid0h);
216 mac_addr[0] = mac_hi & 0xFF;
217 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
218 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
219 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
220 mac_addr[4] = mac_lo & 0xFF;
221 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
223 if (is_valid_ether_addr(mac_addr))
224 eth_setenv_enetaddr("ethaddr", mac_addr);
229 writel(RMII_RGMII2_MODE_ENABLE, &cdev->miisel);
231 rv = cpsw_register(&cpsw_data);
233 printf("Error %d registering CPSW switch\n", rv);
239 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_SPL_BUILD)
240 rv = usb_eth_initialize(bis);
242 printf("Error %d registering USB_ETHER\n", rv);