2 * Memory Setup stuff - taken from blob memsetup.S
4 * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
5 * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
7 * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
8 * Copyright (C) 2009 Jean-Christopher PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/arch/hardware.h>
32 #include <asm/arch/at91_pmc.h>
33 #include <asm/arch/at91_pio.h>
34 #include <asm/arch/at91_rstc.h>
35 #include <asm/arch/at91_wdt.h>
36 #include <asm/arch/at91sam9_sdramc.h>
37 #include <asm/arch/at91sam9_smc.h>
38 #include <asm/arch/at91sam9261_matrix.h>
44 .type lowlevel_init,function
47 mov r5, pc /* r5 = POS1 + 4 current */
49 ldr r0, =POS1 /* r0 = POS1 compile */
51 sub r0, r0, r2 /* r0 = POS1-_TEXT_BASE (POS1 relative) */
52 sub r5, r5, r0 /* r0 = TEXT_BASE-1 */
53 sub r5, r5, #4 /* r1 = text base - current */
55 /* memory control configuration 1 */
72 /* ----------------------------------------------------------------------------
74 * ----------------------------------------------------------------------------
75 * - Check if the PLL is already initialized
76 * ----------------------------------------------------------------------------
78 ldr r1, =(AT91_BASE_SYS + AT91_PMC_MCKR)
84 /* ---------------------------------------------------------------------------
85 * - Enable the Main Oscillator
86 * ---------------------------------------------------------------------------
88 ldr r1, =(AT91_BASE_SYS + AT91_CKGR_MOR)
89 ldr r2, =(AT91_BASE_SYS + AT91_PMC_SR)
90 /* Main oscillator Enable register PMC_MOR: */
91 /* Enable main oscillator, OSCOUNT = 0xFF */
92 ldr r0, =CONFIG_SYS_MOR_VAL
95 /* Reading the PMC Status to detect when the Main Oscillator is enabled */
96 mov r4, #AT91_PMC_MOSCS
100 cmp r3, #AT91_PMC_MOSCS
103 /* ----------------------------------------------------------------------------
105 * ----------------------------------------------------------------------------
107 * ----------------------------------------------------------------------------
109 ldr r1, =(AT91_BASE_SYS + AT91_CKGR_PLLAR)
110 ldr r0, =CONFIG_SYS_PLLAR_VAL
113 /* Reading the PMC Status register to detect when the PLLA is locked */
114 mov r4, #AT91_PMC_LOCKA
118 cmp r3, #AT91_PMC_LOCKA
121 /* ----------------------------------------------------------------------------
123 * ----------------------------------------------------------------------------
124 * - Switch on the Main Oscillator 18.432 MHz
125 * ----------------------------------------------------------------------------
127 ldr r1, =(AT91_BASE_SYS + AT91_PMC_MCKR)
129 /* -Master Clock Controller register PMC_MCKR */
130 ldr r0, =CONFIG_SYS_MCKR1_VAL
133 /* Reading the PMC Status to detect when the Master clock is ready */
134 mov r4, #AT91_PMC_MCKRDY
138 cmp r3, #AT91_PMC_MCKRDY
141 ldr r0, =CONFIG_SYS_MCKR2_VAL
144 /* Reading the PMC Status to detect when the Master clock is ready */
145 mov r4, #AT91_PMC_MCKRDY
149 cmp r3, #AT91_PMC_MCKRDY
154 /* ----------------------------------------------------------------------------
155 * - memory control configuration 2
156 * ----------------------------------------------------------------------------
158 ldr r0, =(AT91_BASE_SYS + AT91_SDRAMC_TR)
181 /* everything is fine now */
187 .word (AT91_BASE_SYS + AT91_WDT_MR)
188 .word CONFIG_SYS_WDTC_WDMR_VAL
190 .word (AT91_BASE_SYS + AT91_PIOC + PIO_PDR)
191 .word CONFIG_SYS_PIOC_PDR_VAL1
192 .word (AT91_BASE_SYS + AT91_PIOC + PIO_PUDR)
193 .word CONFIG_SYS_PIOC_PPUDR_VAL
195 .word (AT91_BASE_SYS + AT91_MATRIX_EBICSA)
196 .word CONFIG_SYS_MATRIX_EBICSA_VAL
199 .word (AT91_BASE_SYS + AT91_SMC_MODE(0))
200 .word CONFIG_SYS_SMC0_MODE0_VAL
202 .word (AT91_BASE_SYS + AT91_SMC_CYCLE(0))
203 .word CONFIG_SYS_SMC0_CYCLE0_VAL
205 .word (AT91_BASE_SYS + AT91_SMC_PULSE(0))
206 .word CONFIG_SYS_SMC0_PULSE0_VAL
208 .word (AT91_BASE_SYS + AT91_SMC_SETUP(0))
209 .word CONFIG_SYS_SMC0_SETUP0_VAL
212 .word (AT91_BASE_SYS + AT91_SDRAMC_MR)
213 .word CONFIG_SYS_SDRC_MR_VAL1
214 .word (AT91_BASE_SYS + AT91_SDRAMC_TR)
215 .word CONFIG_SYS_SDRC_TR_VAL1
216 .word (AT91_BASE_SYS + AT91_SDRAMC_CR)
217 .word CONFIG_SYS_SDRC_CR_VAL
218 .word (AT91_BASE_SYS + AT91_SDRAMC_MDR)
219 .word CONFIG_SYS_SDRC_MDR_VAL
220 .word (AT91_BASE_SYS + AT91_SDRAMC_MR)
221 .word CONFIG_SYS_SDRC_MR_VAL2
222 .word AT91_SDRAM_BASE
223 .word CONFIG_SYS_SDRAM_VAL1
224 .word (AT91_BASE_SYS + AT91_SDRAMC_MR)
225 .word CONFIG_SYS_SDRC_MR_VAL3
226 .word AT91_SDRAM_BASE
227 .word CONFIG_SYS_SDRAM_VAL2
228 .word AT91_SDRAM_BASE
229 .word CONFIG_SYS_SDRAM_VAL3
230 .word AT91_SDRAM_BASE
231 .word CONFIG_SYS_SDRAM_VAL4
232 .word AT91_SDRAM_BASE
233 .word CONFIG_SYS_SDRAM_VAL5
234 .word AT91_SDRAM_BASE
235 .word CONFIG_SYS_SDRAM_VAL6
236 .word AT91_SDRAM_BASE
237 .word CONFIG_SYS_SDRAM_VAL7
238 .word AT91_SDRAM_BASE
239 .word CONFIG_SYS_SDRAM_VAL8
240 .word AT91_SDRAM_BASE
241 .word CONFIG_SYS_SDRAM_VAL9
242 .word (AT91_BASE_SYS + AT91_SDRAMC_MR)
243 .word CONFIG_SYS_SDRC_MR_VAL4
244 .word AT91_SDRAM_BASE
245 .word CONFIG_SYS_SDRAM_VAL10
246 .word (AT91_BASE_SYS + AT91_SDRAMC_MR)
247 .word CONFIG_SYS_SDRC_MR_VAL5
248 .word AT91_SDRAM_BASE
249 .word CONFIG_SYS_SDRAM_VAL11
250 .word (AT91_BASE_SYS + AT91_SDRAMC_TR)
251 .word CONFIG_SYS_SDRC_TR_VAL2
252 .word AT91_SDRAM_BASE
253 .word CONFIG_SYS_SDRAM_VAL12
254 /* User reset enable*/
255 .word (AT91_BASE_SYS + AT91_RSTC_MR)
256 .word CONFIG_SYS_RSTC_RMR_VAL