2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian@popies.net>
4 * Lead Tech Design <www.leadtechdesign.com>
5 * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
6 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
8 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/sizes.h>
14 #include <asm/arch/at91sam9_smc.h>
15 #include <asm/arch/at91_common.h>
16 #include <asm/arch/at91_pmc.h>
17 #include <asm/arch/at91_rstc.h>
18 #include <asm/arch/at91_matrix.h>
19 #include <asm/arch/clk.h>
20 #include <asm/arch/gpio.h>
22 #include <atmel_lcdc.h>
23 #include <dataflash.h>
24 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
29 DECLARE_GLOBAL_DATA_PTR;
31 /* ------------------------------------------------------------------------- */
33 * Miscelaneous platform dependent initialisations
36 #ifdef CONFIG_CMD_NAND
37 static void pm9263_nand_hw_init(void)
40 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC0;
41 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
44 csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
45 writel(csa, &matrix->csa[0]);
47 /* Configure SMC CS3 for NAND/SmartMedia */
48 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
49 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
52 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
53 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
56 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
59 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
60 AT91_SMC_MODE_EXNW_DISABLE |
61 #ifdef CONFIG_SYS_NAND_DBW_16
62 AT91_SMC_MODE_DBW_16 |
63 #else /* CONFIG_SYS_NAND_DBW_8 */
66 AT91_SMC_MODE_TDF_CYCLE(2),
69 /* Configure RDY/BSY */
70 at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
72 /* Enable NandFlash */
73 at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
78 static void pm9263_macb_hw_init(void)
80 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
83 * PB27 enables the 50MHz oscillator for Ethernet PHY
87 at91_set_pio_output(AT91_PIO_PORTB, 27, 1);
88 at91_set_pio_value(AT91_PIO_PORTB, 27, 1); /* 1- enable, 0 - disable */
91 writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
95 * RXDV (PC25) => PHY normal mode (not Test mode)
96 * ERX0 (PE25) => PHY ADDR0
97 * ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
99 * PHY has internal pull-down
102 at91_set_pio_pullup(AT91_PIO_PORTC, 25, 0);
103 at91_set_pio_pullup(AT91_PIO_PORTE, 25, 0);
104 at91_set_pio_pullup(AT91_PIO_PORTE, 26, 0);
106 /* Re-enable pull-up */
107 at91_set_pio_pullup(AT91_PIO_PORTC, 25, 1);
108 at91_set_pio_pullup(AT91_PIO_PORTE, 25, 1);
109 at91_set_pio_pullup(AT91_PIO_PORTE, 26, 1);
116 vidinfo_t panel_info = {
120 vl_sync: ATMEL_LCDC_INVLINE_INVERTED |
121 ATMEL_LCDC_INVFRAME_INVERTED,
130 mmio: ATMEL_BASE_LCDC,
133 void lcd_enable(void)
135 at91_set_pio_value(AT91_PIO_PORTA, 22, 1); /* power up */
138 void lcd_disable(void)
140 at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */
143 #ifdef CONFIG_LCD_IN_PSRAM
145 #define PSRAM_CRE_PIN AT91_PIO_PORTB, 29
146 #define PSRAM_CTRL_REG (PHYS_PSRAM + PHYS_PSRAM_SIZE - 2)
148 /* Initialize the PSRAM memory */
149 static int pm9263_lcd_hw_psram_init(void)
152 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC1;
153 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
155 /* Enable CS3 3.3v, no pull-ups */
156 csa = readl(&matrix->csa[1]) | AT91_MATRIX_CSA_DBPUC |
157 AT91_MATRIX_CSA_VDDIOMSEL_3_3V;
159 writel(csa, &matrix->csa[1]);
161 /* Configure SMC1 CS0 for PSRAM - 16-bit */
162 writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
163 AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
166 writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) |
167 AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(7),
170 writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
173 writel(AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_PMEN | AT91_SMC_MODE_PS_32,
176 /* setup PB29 as output */
177 at91_set_pio_output(PSRAM_CRE_PIN, 1);
179 at91_set_pio_value(PSRAM_CRE_PIN, 0); /* set PSRAM_CRE_PIN to '0' */
181 /* PSRAM: write BCR */
182 readw(PSRAM_CTRL_REG);
183 readw(PSRAM_CTRL_REG);
184 writew(1, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */
185 writew(0x9d4f, PSRAM_CTRL_REG); /* write the BCR */
187 /* write RCR of the PSRAM */
188 readw(PSRAM_CTRL_REG);
189 readw(PSRAM_CTRL_REG);
190 writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */
191 /* set RCR; 0x10-async mode,0x90-page mode */
192 writew(0x90, PSRAM_CTRL_REG);
195 * test to see if the PSRAM is MT45W2M16A or MT45W2M16B
196 * MT45W2M16B - CRE must be 0
197 * MT45W2M16A - CRE must be 1
199 writew(0x1234, PHYS_PSRAM);
200 writew(0x5678, PHYS_PSRAM + 2);
202 /* test if the chip is MT45W2M16B */
203 if ((readw(PHYS_PSRAM) != 0x1234) || (readw(PHYS_PSRAM+2) != 0x5678)) {
204 /* try with CRE=1 (MT45W2M16A) */
205 at91_set_pio_value(PSRAM_CRE_PIN, 1); /* set PSRAM_CRE_PIN to '1' */
207 /* write RCR of the PSRAM */
208 readw(PSRAM_CTRL_REG);
209 readw(PSRAM_CTRL_REG);
210 writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */
211 /* set RCR;0x10-async mode,0x90-page mode */
212 writew(0x90, PSRAM_CTRL_REG);
215 writew(0x1234, PHYS_PSRAM);
216 writew(0x5678, PHYS_PSRAM+2);
217 if ((readw(PHYS_PSRAM) != 0x1234)
218 || (readw(PHYS_PSRAM + 2) != 0x5678))
224 writel(AT91_MATRIX_PRA_M5(3), &matrix->pr[5].a);
225 writel(CONFIG_PSRAM_SCFG, &matrix->scfg[5]);
231 static void pm9263_lcd_hw_init(void)
233 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
235 at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */
236 at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */
237 at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */
238 at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */
239 at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */
240 at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */
241 at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */
242 at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */
243 at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */
244 at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */
245 at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */
246 at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */
247 at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */
248 at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */
249 at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */
250 at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */
251 at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */
252 at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */
253 at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */
254 at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */
255 at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */
256 at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */
257 at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */
259 writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
262 at91_set_pio_output(AT91_PIO_PORTA, 22, 1);
263 at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */
265 #ifdef CONFIG_LCD_IN_PSRAM
266 /* initialize te PSRAM */
267 int stat = pm9263_lcd_hw_psram_init();
269 gd->fb_base = (stat == 0) ? PHYS_PSRAM : ATMEL_BASE_SRAM0;
271 gd->fb_base = ATMEL_BASE_SRAM0;
276 #ifdef CONFIG_LCD_INFO
280 extern flash_info_t flash_info[];
282 void lcd_show_board_info(void)
284 ulong dram_size, nand_size, flash_size, dataflash_size;
288 lcd_printf ("%s\n", U_BOOT_VERSION);
289 lcd_printf ("(C) 2009 Ronetix GmbH\n");
290 lcd_printf ("support@ronetix.at\n");
291 lcd_printf ("%s CPU at %s MHz",
292 CONFIG_SYS_AT91_CPU_NAME,
293 strmhz(temp, get_cpu_clk_rate()));
296 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
297 dram_size += gd->bd->bi_dram[i].size;
300 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
301 nand_size += nand_info[i].size;
304 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
305 flash_size += flash_info[i].size;
308 for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++)
309 dataflash_size += (unsigned int) dataflash_info[i].Device.pages_number *
310 dataflash_info[i].Device.pages_size;
312 lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n"
313 "4 MB PSRAM, %ld MB DataFlash\n",
317 dataflash_size >> 20);
319 #endif /* CONFIG_LCD_INFO */
321 #endif /* CONFIG_LCD */
323 int board_early_init_f(void)
325 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
327 /* Enable clocks for all PIOs */
328 writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
329 (1 << ATMEL_ID_PIOCDE),
332 at91_seriald_hw_init();
339 /* arch number of AT91SAM9263EK-Board */
340 gd->bd->bi_arch_number = MACH_TYPE_PM9263;
342 /* adress of boot parameters */
343 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
345 #ifdef CONFIG_CMD_NAND
346 pm9263_nand_hw_init();
348 #ifdef CONFIG_HAS_DATAFLASH
349 at91_spi0_hw_init(1 << 0);
352 pm9263_macb_hw_init();
354 #ifdef CONFIG_USB_OHCI_NEW
358 pm9263_lcd_hw_init();
365 /* dram_init must store complete ramsize in gd->ram_size */
366 gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
371 void dram_init_banksize(void)
373 gd->bd->bi_dram[0].start = PHYS_SDRAM;
374 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
377 #ifdef CONFIG_RESET_PHY_R
383 int board_eth_init(bd_t *bis)
387 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x01);
392 #ifdef CONFIG_DISPLAY_BOARDINFO
393 int checkboard (void)
397 printf ("Board : Ronetix PM9263\n");
399 switch (gd->fb_base) {
404 case ATMEL_BASE_SRAM0:
405 ss = "(Internal SRAM)";
412 printf("Video memory : 0x%08lX %s\n", gd->fb_base, ss );