4 * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/ic/sc520.h>
30 #include <asm/ic/pci.h>
35 DECLARE_GLOBAL_DATA_PTR;
37 #undef SC520_CDP_DEBUG
39 #ifdef SC520_CDP_DEBUG
40 #define PRINTF(fmt,args...) printf (fmt ,##args)
42 #define PRINTF(fmt,args...)
45 /* ------------------------------------------------------------------------- */
50 * We first set up all IRQs to be non-pci, edge triggered,
51 * when we later enumerate the pci bus and pci_sc520_fixup_irq() gets
52 * called we reallocate irqs to the pci bus with sc520_pci_set_irq()
53 * as needed. Whe choose the irqs to gram from a configurable list
54 * inside pci_sc520_fixup_irq() (If this list contains stupid irq's
55 * such as 0 thngas will not work)
58 static void irq_init(void)
60 /* disable global interrupt mode */
61 sc520_mmcr->picicr = 0x40;
63 /* set all irqs to edge */
64 sc520_mmcr->pic_mode[0] = 0x00;
65 sc520_mmcr->pic_mode[1] = 0x00;
66 sc520_mmcr->pic_mode[2] = 0x00;
68 /* active low polarity on PIC interrupt pins,
69 * active high polarity on all other irq pins */
70 sc520_mmcr->intpinpol = 0x0000;
72 /* set irq number mapping */
73 sc520_mmcr->gp_tmr_int_map[0] = SC520_IRQ_DISABLED; /* disable GP timer 0 INT */
74 sc520_mmcr->gp_tmr_int_map[1] = SC520_IRQ_DISABLED; /* disable GP timer 1 INT */
75 sc520_mmcr->gp_tmr_int_map[2] = SC520_IRQ_DISABLED; /* disable GP timer 2 INT */
76 sc520_mmcr->pit_int_map[0] = SC520_IRQ0; /* Set PIT timer 0 INT to IRQ0 */
77 sc520_mmcr->pit_int_map[1] = SC520_IRQ_DISABLED; /* disable PIT timer 1 INT */
78 sc520_mmcr->pit_int_map[2] = SC520_IRQ_DISABLED; /* disable PIT timer 2 INT */
79 sc520_mmcr->pci_int_map[0] = SC520_IRQ_DISABLED; /* disable PCI INT A */
80 sc520_mmcr->pci_int_map[1] = SC520_IRQ_DISABLED; /* disable PCI INT B */
81 sc520_mmcr->pci_int_map[2] = SC520_IRQ_DISABLED; /* disable PCI INT C */
82 sc520_mmcr->pci_int_map[3] = SC520_IRQ_DISABLED; /* disable PCI INT D */
83 sc520_mmcr->dmabcintmap = SC520_IRQ_DISABLED; /* disable DMA INT */
84 sc520_mmcr->ssimap = SC520_IRQ_DISABLED; /* disable Synchronius serial INT */
85 sc520_mmcr->wdtmap = SC520_IRQ_DISABLED; /* disable Watchdog INT */
86 sc520_mmcr->rtcmap = SC520_IRQ8; /* Set RTC int to 8 */
87 sc520_mmcr->wpvmap = SC520_IRQ_DISABLED; /* disable write protect INT */
88 sc520_mmcr->icemap = SC520_IRQ1; /* Set ICE Debug Serielport INT to IRQ1 */
89 sc520_mmcr->ferrmap = SC520_IRQ13; /* Set FP error INT to IRQ13 */
91 if (CONFIG_SYS_USE_SIO_UART) {
92 sc520_mmcr->uart_int_map[0] = SC520_IRQ_DISABLED; /* disable internal UART1 INT */
93 sc520_mmcr->uart_int_map[1] = SC520_IRQ_DISABLED; /* disable internal UART2 INT */
94 sc520_mmcr->gp_int_map[3] = SC520_IRQ3; /* Set GPIRQ3 (ISA IRQ3) to IRQ3 */
95 sc520_mmcr->gp_int_map[4] = SC520_IRQ4; /* Set GPIRQ4 (ISA IRQ4) to IRQ4 */
97 sc520_mmcr->uart_int_map[0] = SC520_IRQ4; /* Set internal UART2 INT to IRQ4 */
98 sc520_mmcr->uart_int_map[1] = SC520_IRQ3; /* Set internal UART2 INT to IRQ3 */
99 sc520_mmcr->gp_int_map[3] = SC520_IRQ_DISABLED; /* disable GPIRQ3 (ISA IRQ3) */
100 sc520_mmcr->gp_int_map[4] = SC520_IRQ_DISABLED; /* disable GPIRQ4 (ISA IRQ4) */
103 sc520_mmcr->gp_int_map[1] = SC520_IRQ1; /* Set GPIRQ1 (SIO IRQ1) to IRQ1 */
104 sc520_mmcr->gp_int_map[5] = SC520_IRQ5; /* Set GPIRQ5 (ISA IRQ5) to IRQ5 */
105 sc520_mmcr->gp_int_map[6] = SC520_IRQ6; /* Set GPIRQ6 (ISA IRQ6) to IRQ6 */
106 sc520_mmcr->gp_int_map[7] = SC520_IRQ7; /* Set GPIRQ7 (ISA IRQ7) to IRQ7 */
107 sc520_mmcr->gp_int_map[8] = SC520_IRQ8; /* Set GPIRQ8 (SIO IRQ8) to IRQ8 */
108 sc520_mmcr->gp_int_map[9] = SC520_IRQ9; /* Set GPIRQ9 (ISA IRQ2) to IRQ9 */
109 sc520_mmcr->gp_int_map[0] = SC520_IRQ11; /* Set GPIRQ0 (ISA IRQ11) to IRQ10 */
110 sc520_mmcr->gp_int_map[2] = SC520_IRQ12; /* Set GPIRQ2 (ISA IRQ12) to IRQ12 */
111 sc520_mmcr->gp_int_map[10] = SC520_IRQ14; /* Set GPIRQ10 (ISA IRQ14) to IRQ14 */
113 sc520_mmcr->pcihostmap = 0x11f; /* Map PCI hostbridge INT to NMI */
114 sc520_mmcr->eccmap = 0x100; /* Map SDRAM ECC failure INT to NMI */
119 static void pci_sc520_cdp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
121 /* a configurable lists of irqs to steal
122 * when we need one (a board with more pci interrupt pins
123 * would use a larger table */
124 static int irq_list[] = {
125 CONFIG_SYS_FIRST_PCI_IRQ,
126 CONFIG_SYS_SECOND_PCI_IRQ,
127 CONFIG_SYS_THIRD_PCI_IRQ,
128 CONFIG_SYS_FORTH_PCI_IRQ
130 static int next_irq_index=0;
135 pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin);
138 pin-=1; /* pci config space use 1-based numbering */
140 return; /* device use no irq */
144 /* map device number + pin to a pin on the sc520 */
145 switch (PCI_DEV(dev)) {
166 pin&=3; /* wrap around */
168 if (sc520_pci_ints[pin] == -1) {
169 /* re-route one interrupt for us */
170 if (next_irq_index > 3) {
173 if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) {
180 if (-1 != sc520_pci_ints[pin]) {
181 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
182 sc520_pci_ints[pin]);
184 PRINTF("fixup_irq: device %d pin %c irq %d\n",
185 PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]);
188 static struct pci_controller sc520_cdp_hose = {
189 fixup_irq: pci_sc520_cdp_fixup_irq,
192 void pci_init_board(void)
194 pci_sc520_init(&sc520_cdp_hose);
198 static void silence_uart(int port)
203 void setup_ali_sio(int uart_primary)
207 ali512x_set_fdc(ALI_ENABLED, 0x3f2, 6, 0);
208 ali512x_set_pp(ALI_ENABLED, 0x278, 7, 3);
209 ali512x_set_uart(ALI_ENABLED, ALI_UART1, uart_primary?0x3f8:0x3e8, 4);
210 ali512x_set_uart(ALI_ENABLED, ALI_UART2, uart_primary?0x2f8:0x2e8, 3);
211 ali512x_set_rtc(ALI_DISABLED, 0, 0);
212 ali512x_set_kbc(ALI_ENABLED, 1, 12);
213 ali512x_set_cio(ALI_ENABLED);
216 ali512x_cio_function(12, 1, 0, 0);
217 ali512x_cio_function(13, 1, 0, 0);
219 /* SSI chip select pins */
220 ali512x_cio_function(14, 0, 0, 0); /* SSI_CS */
221 ali512x_cio_function(15, 0, 0, 0); /* SSI_MV */
222 ali512x_cio_function(16, 0, 0, 0); /* SSI_SPI# */
225 ali512x_cio_function(20, 0, 0, 1);
226 ali512x_cio_function(21, 0, 0, 1);
227 ali512x_cio_function(22, 0, 0, 1);
228 ali512x_cio_function(23, 0, 0, 1);
232 /* set up the ISA bus timing and system address mappings */
233 static void bus_init(void)
236 /* set up the GP IO pins */
237 sc520_mmcr->piopfs31_16 = 0xf7ff; /* set the GPIO pin function 31-16 reg */
238 sc520_mmcr->piopfs15_0 = 0xffff; /* set the GPIO pin function 15-0 reg */
239 sc520_mmcr->cspfs = 0xf8; /* set the CS pin function reg */
240 sc520_mmcr->clksel = 0x70;
242 sc520_mmcr->gpcsrt = 1; /* set the GP CS offset */
243 sc520_mmcr->gpcspw = 3; /* set the GP CS pulse width */
244 sc520_mmcr->gpcsoff = 1; /* set the GP CS offset */
245 sc520_mmcr->gprdw = 3; /* set the RD pulse width */
246 sc520_mmcr->gprdoff = 1; /* set the GP RD offset */
247 sc520_mmcr->gpwrw = 3; /* set the GP WR pulse width */
248 sc520_mmcr->gpwroff = 1; /* set the GP WR offset */
250 sc520_mmcr->bootcsctl = 0x1823; /* set up timing of BOOTCS */
251 sc520_mmcr->romcs1ctl = 0x1823; /* set up timing of ROMCS1 */
252 sc520_mmcr->romcs2ctl = 0x1823; /* set up timing of ROMCS2 */
254 /* adjust the memory map:
255 * by default the first 256MB (0x00000000 - 0x0fffffff) is mapped to SDRAM
256 * and 256MB to 1G-128k (0x1000000 - 0x37ffffff) is mapped to PCI mmio
257 * we need to map 1G-128k - 1G (0x38000000 - 0x3fffffff) to CS1 */
260 /* SRAM = GPCS3 128k @ d0000-effff*/
261 sc520_mmcr->par[2] = 0x4e00400d;
263 /* IDE0 = GPCS6 1f0-1f7 */
264 sc520_mmcr->par[3] = 0x380801f0;
266 /* IDE1 = GPCS7 3f6 */
267 sc520_mmcr->par[4] = 0x3c0003f6;
269 sc520_mmcr->par[12] = 0x8bffe800;
271 sc520_mmcr->par[13] = 0xcbfff000;
273 sc520_mmcr->par[14] = 0xabfff800;
275 sc520_mmcr->par[15] = 0x30000640;
277 sc520_mmcr->adddecctl = 0;
279 asm ("wbinvd\n"); /* Flush cache, req. after setting the unchached attribute ona PAR */
281 if (CONFIG_SYS_USE_SIO_UART) {
282 sc520_mmcr->adddecctl = sc520_mmcr->adddecctl | UART2_DIS | UART1_DIS;
285 sc520_mmcr->adddecctl = sc520_mmcr->adddecctl & ~(UART2_DIS|UART1_DIS);
307 * PAR1 PCI ROM mapping
321 * PAR15 Port 0x680 LED display
325 * This function should map a chunk of size bytes
326 * of the system address space to the ISA bus
328 * The function will return the memory address
329 * as seen by the host (which may very will be the
330 * same as the bus address)
332 u32 isa_map_rom(u32 bus_addr, int size)
336 PRINTF("isa_map_rom asked to map %d bytes at %x\n",
347 par |= (bus_addr>>12);
350 PRINTF ("setting PAR11 to %x\n", par);
352 /* Map rom 0x10000 with PAR1 */
353 sc520_mmcr->par[11] = par;
359 * this function removed any mapping created
360 * with pci_get_rom_window()
362 void isa_unmap_rom(u32 addr)
364 PRINTF("isa_unmap_rom asked to unmap %x", addr);
365 if ((addr>>12) == (sc520_mmcr->par[11] & 0x3ffff)) {
366 sc520_mmcr->par[11] = 0;
370 PRINTF(" not ours\n");
374 #define PCI_ROM_TEMP_SPACE 0x10000
376 * This function should map a chunk of size bytes
377 * of the system address space to the PCI bus,
378 * suitable to map PCI ROMS (bus address < 16M)
379 * the function will return the host memory address
380 * which should be converted into a bus address
381 * before used to configure the PCI rom address
384 u32 pci_get_rom_window(struct pci_controller *hose, int size)
396 par |= (PCI_ROM_TEMP_SPACE>>16);
399 PRINTF ("setting PAR1 to %x\n", par);
401 /* Map rom 0x10000 with PAR1 */
402 sc520_mmcr->par[1] = par;
404 return PCI_ROM_TEMP_SPACE;
408 * this function removed any mapping created
409 * with pci_get_rom_window()
411 void pci_remove_rom_window(struct pci_controller *hose, u32 addr)
413 PRINTF("pci_remove_rom_window: %x", addr);
414 if (addr == PCI_ROM_TEMP_SPACE) {
415 sc520_mmcr->par[1] = 0;
419 PRINTF(" not ours\n");
424 * This function is called in order to provide acces to the
425 * legacy video I/O ports on the PCI bus.
426 * After this function accesses to I/O ports 0x3b0-0x3bb and
427 * 0x3c0-0x3df shuld result in transactions on the PCI bus.
430 int pci_enable_legacy_video_ports(struct pci_controller *hose)
432 /* Map video memory to 0xa0000*/
433 sc520_mmcr->par[0] = 0x7200400a;
435 /* forward all I/O accesses to PCI */
436 sc520_mmcr->adddecctl = sc520_mmcr->adddecctl | IO_HOLE_DEST_PCI;
439 /* so we map away all io ports to pci (only way to access pci io
440 * below 0x400. But then we have to map back the portions that we dont
441 * use so that the generate cycles on the GPIO bus where the sio and
442 * ISA slots are connected, this requre the use of several PAR registers
445 /* bring 0x100 - 0x1ef back to ISA using PAR5 */
446 sc520_mmcr->par[5] = 0x30ef0100;
448 /* IDE use 1f0-1f7 */
450 /* bring 0x1f8 - 0x2f7 back to ISA using PAR6 */
451 sc520_mmcr->par[6] = 0x30ff01f8;
453 /* com2 use 2f8-2ff */
455 /* bring 0x300 - 0x3af back to ISA using PAR7 */
456 sc520_mmcr->par[7] = 0x30af0300;
458 /* vga use 3b0-3bb */
460 /* bring 0x3bc - 0x3bf back to ISA using PAR8 */
461 sc520_mmcr->par[8] = 0x300303bc;
463 /* vga use 3c0-3df */
465 /* bring 0x3e0 - 0x3f5 back to ISA using PAR9 */
466 sc520_mmcr->par[9] = 0x301503e0;
470 /* bring 0x3f7 back to ISA using PAR10 */
471 sc520_mmcr->par[10] = 0x300003f7;
473 /* com1 use 3f8-3ff */
480 * Miscelaneous platform dependent initialisations
489 /* max drive current on SDRAM */
490 sc520_mmcr->dsctl = 0x0100;
492 /* enter debug mode after next reset (only if jumper is also set) */
493 sc520_mmcr->rescfg = 0x08;
494 /* configure the software timer to 33.333MHz */
495 sc520_mmcr->swtmrcfg = 0;
496 gd->bus_clk = 33333000;
507 void show_boot_progress(int val)
509 if (val < -32) val = -1; /* let things compatible */
510 outb(val&0xff, 0x80);
511 outb((val&0xff00)>>8, 0x680);
515 int last_stage_init(void)
521 major |= ali512x_cio_in(23)?2:0;
522 major |= ali512x_cio_in(22)?1:0;
523 minor |= ali512x_cio_in(21)?2:0;
524 minor |= ali512x_cio_in(20)?1:0;
526 printf("AMD SC520 CDP revision %d.%d\n", major, minor);
532 void ssi_chip_select(int dev)
535 /* Spunk board: SPI EEPROM is active-low, MW EEPROM and AUX are active high */
537 case 1: /* SPI EEPROM */
538 ali512x_cio_out(16, 0);
541 case 2: /* MW EEPROM */
542 ali512x_cio_out(15, 1);
546 ali512x_cio_out(14, 1);
550 ali512x_cio_out(16, 1);
551 ali512x_cio_out(15, 0);
552 ali512x_cio_out(14, 0);
556 printf("Illegal SSI device requested: %d\n", dev);
560 void spi_eeprom_probe(int x)
564 int spi_eeprom_read(int x, int offset, uchar *buffer, int len)
569 int spi_eeprom_write(int x, int offset, uchar *buffer, int len)
574 void spi_init_f(void)
576 #ifdef CONFIG_SYS_SC520_CDP_USE_SPI
579 #ifdef CONFIG_SYS_SC520_CDP_USE_MW
584 ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len)
591 for (i=0;i<alen;i++) {
596 #ifdef CONFIG_SYS_SC520_CDP_USE_SPI
597 res = spi_eeprom_read(1, offset, buffer, len);
599 #ifdef CONFIG_SYS_SC520_CDP_USE_MW
600 res = mw_eeprom_read(2, offset, buffer, len);
602 #if !defined(CONFIG_SYS_SC520_CDP_USE_SPI) && !defined(CONFIG_SYS_SC520_CDP_USE_MW)
608 ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len)
615 for (i=0;i<alen;i++) {
620 #ifdef CONFIG_SYS_SC520_CDP_USE_SPI
621 res = spi_eeprom_write(1, offset, buffer, len);
623 #ifdef CONFIG_SYS_SC520_CDP_USE_MW
624 res = mw_eeprom_write(2, offset, buffer, len);
626 #if !defined(CONFIG_SYS_SC520_CDP_USE_SPI) && !defined(CONFIG_SYS_SC520_CDP_USE_MW)
632 int board_eth_init(bd_t *bis)
634 return pci_eth_init(bis);