]> git.kernelconcepts.de Git - karo-tx-uboot.git/blob - board/scb9328/lowlevel_init.S
board: h2200: Delete an unnecessary make rule
[karo-tx-uboot.git] / board / scb9328 / lowlevel_init.S
1 /*
2  * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #include <config.h>
8 #include <version.h>
9 #include <asm/arch/imx-regs.h>
10
11 .globl lowlevel_init
12 lowlevel_init:
13
14         mov     r10, lr
15
16 /* Change PERCLK1DIV to 14 ie 14+1 */
17         ldr             r0,     =PCDR
18         ldr             r1,     =CONFIG_SYS_PCDR_VAL
19         str             r1,   [r0]
20
21 /* set MCU PLL Control Register 0 */
22
23         ldr             r0,     =MPCTL0
24         ldr             r1,     =CONFIG_SYS_MPCTL0_VAL
25         str             r1,   [r0]
26
27 /* set mpll restart bit */
28         ldr             r0, =CSCR
29         ldr             r1, [r0]
30         orr             r1,r1,#(1<<21)
31         str             r1, [r0]
32
33         mov             r2,#0x10
34 1:
35         mov             r3,#0x2000
36 2:
37         subs    r3,r3,#1
38         bne             2b
39
40         subs    r2,r2,#1
41         bne             1b
42
43 /* set System PLL Control Register 0 */
44
45         ldr             r0,     =SPCTL0
46         ldr             r1,     =CONFIG_SYS_SPCTL0_VAL
47         str             r1,   [r0]
48
49 /* set spll restart bit */
50         ldr             r0, =CSCR
51         ldr             r1, [r0]
52         orr             r1,r1,#(1<<22)
53         str             r1, [r0]
54
55         mov             r2,#0x10
56 1:
57         mov             r3,#0x2000
58 2:
59         subs    r3,r3,#1
60         bne             2b
61
62         subs    r2,r2,#1
63         bne             1b
64
65         ldr             r0,   =CSCR
66         ldr             r1,   =CONFIG_SYS_CSCR_VAL
67         str             r1,   [r0]
68
69 /* I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon
70  *this.....
71  *
72  * It would appear that from a Cold-Boot the ARM920T enters "FastBus" mode CP15
73  * register 1, this stops it using the output of the PLL and thus runs at the
74  * slow rate. Unless you place the Core into "Asynch" mode, the CPU will never
75  * use the value set in the CM_OSC registers...regardless of what you set it
76  * too!  Thus, although i thought i was running at 140MHz, i'm actually running
77  * at 40!..
78
79  * Slapping this into my bootloader does the trick...
80
81  * MRC p15,0,r0,c1,c0,0    ; read core configuration register
82  * ORR r0,r0,#0xC0000000   ; set asynchronous clocks and not fastbus mode
83  * MCR p15,0,r0,c1,c0,0    ; write modified value to core configuration
84  * register
85  */
86         MRC p15,0,r0,c1,c0,0
87         ORR r0,r0,#0xC0000000
88         MCR p15,0,r0,c1,c0,0
89
90         ldr             r0,     =GPR(0)
91         ldr             r1,     =CONFIG_SYS_GPR_A_VAL
92         str             r1,   [r0]
93
94         ldr             r0,     =GIUS(0)
95         ldr             r1,     =CONFIG_SYS_GIUS_A_VAL
96         str             r1,   [r0]
97
98 /* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */
99
100         ldr             r0,     =FMCR
101         ldr             r1,     =CONFIG_SYS_FMCR_VAL
102         str             r1,   [r0]
103
104         ldr             r0,     =CS0U
105         ldr             r1,     =CONFIG_SYS_CS0U_VAL
106         str             r1,   [r0]
107
108         ldr             r0,     =CS0L
109         ldr             r1,     =CONFIG_SYS_CS0L_VAL
110         str             r1,   [r0]
111
112         ldr             r0,     =CS1U
113         ldr             r1,     =CONFIG_SYS_CS1U_VAL
114         str             r1,   [r0]
115
116         ldr             r0,     =CS1L
117         ldr             r1,     =CONFIG_SYS_CS1L_VAL
118         str             r1,   [r0]
119
120         ldr             r0,     =CS2U
121         ldr             r1,     =CONFIG_SYS_CS2U_VAL
122         str             r1,   [r0]
123
124         ldr             r0,     =CS2L
125         ldr             r1,     =CONFIG_SYS_CS2L_VAL
126         str             r1,   [r0]
127
128         ldr             r0,     =CS3U
129         ldr             r1,     =CONFIG_SYS_CS3U_VAL
130         str             r1,   [r0]
131
132         ldr             r0,     =CS3L
133         ldr             r1,     =CONFIG_SYS_CS3L_VAL
134         str             r1,   [r0]
135
136         ldr             r0,     =CS4U
137         ldr             r1,     =CONFIG_SYS_CS4U_VAL
138         str             r1,   [r0]
139
140         ldr             r0,     =CS4L
141         ldr             r1,     =CONFIG_SYS_CS4L_VAL
142         str             r1,   [r0]
143
144         ldr             r0,     =CS5U
145         ldr             r1,     =CONFIG_SYS_CS5U_VAL
146         str             r1,   [r0]
147
148         ldr             r0,     =CS5L
149         ldr             r1,     =CONFIG_SYS_CS5L_VAL
150         str             r1,   [r0]
151
152 /* SDRAM Setup */
153
154         ldr             r0, =SDCTL0
155         ldr             r1, =PRECHARGE_CMD
156         str             r1,   [r0]
157
158         ldr             r0, =0x08200000
159         ldr             r1, =0x0 /* Issue Precharge all Command */
160         str             r1,   [r0]
161
162         ldr             r0, =SDCTL0
163         ldr             r1, =AUTOREFRESH_CMD
164         str             r1,   [r0]
165
166         ldr             r0, =0x08000000
167         ldr             r1, =0x0 /* Issue AutoRefresh Command */
168         str             r1,   [r0]
169         str             r1,   [r0]
170         str             r1,   [r0]
171         str             r1,   [r0]
172         str             r1,   [r0]
173         str             r1,   [r0]
174         str             r1,   [r0]
175         str             r1,   [r0]
176
177         ldr             r0, =SDCTL0
178         ldr             r1, =0xb10a8300
179         str             r1,   [r0]
180
181         ldr             r0, =0x08223000 /* CAS Latency 2 */
182         ldr             r1, =0x0   /* Issue Mode Register Command, Burst Length = 8 */
183         str             r1,   [r0]
184
185         ldr             r0, =SDCTL0
186         ldr             r1, =0x810a8200 /* Set to Normal Mode CAS 2 */
187         str             r1,   [r0]
188
189         mov     pc,r10