board/siemens/dxr2/board.c

   1 /*
   2  * Board functions for TI AM335X based dxr2 board
   3  * (C) Copyright 2013 Siemens Schweiz AG
   4  * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
   5  *
   6  * Based on:
   7  *
   8  * Board functions for TI AM335X based boards
   9  * u-boot:/board/ti/am335x/board.c
  10  *
  11  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  12  *
  13  * SPDX-License-Identifier:     GPL-2.0+
  14  */
  15
  16 #include <common.h>
  17 #include <errno.h>
  18 #include <spl.h>
  19 #include <asm/arch/cpu.h>
  20 #include <asm/arch/hardware.h>
  21 #include <asm/arch/omap.h>
  22 #include <asm/arch/ddr_defs.h>
  23 #include <asm/arch/clock.h>
  24 #include <asm/arch/gpio.h>
  25 #include <asm/arch/mmc_host_def.h>
  26 #include <asm/arch/sys_proto.h>
  27 #include <asm/io.h>
  28 #include <asm/emif.h>
  29 #include <asm/gpio.h>
  30 #include <i2c.h>
  31 #include <miiphy.h>
  32 #include <cpsw.h>
  33 #include <watchdog.h>
  34 #include "board.h"
  35 #include "../common/factoryset.h"
  36
  37 DECLARE_GLOBAL_DATA_PTR;
  38
  39 #ifdef CONFIG_SPL_BUILD
  40 static struct dxr2_baseboard_id __attribute__((section(".data"))) settings;
  41
  42 #if DDR_PLL_FREQ == 303
  43 /* Default@303MHz-i0 */
  44 const struct ddr3_data ddr3_default = {
  45         0x33524444, 0x56312e35, 0x0080, 0x0000, 0x003A, 0x003F, 0x009F,
  46         0x0079, 0x0888A39B, 0x26247FDA, 0x501F821F, 0x00100206, 0x61A44A32,
  47         0x0000093B, 0x0000014A,
  48         "default name @303MHz           \0",
  49         "default marking                \0",
  50 };
  51 #elif DDR_PLL_FREQ == 400
  52 /* Default@400MHz-i0 */
  53 const struct ddr3_data ddr3_default = {
  54         0x33524444, 0x56312e35, 0x0080, 0x0000, 0x0039, 0x0046, 0x00ab,
  55         0x0080, 0x0AAAA4DB, 0x26307FDA, 0x501F821F, 0x00100207, 0x61A45232,
  56         0x00000618, 0x0000014A,
  57         "default name @400MHz           \0",
  58         "default marking                \0",
  59 };
  60 #endif
  61
  62 static void set_default_ddr3_timings(void)
  63 {
  64         printf("Set default DDR3 settings\n");
  65         settings.ddr3 = ddr3_default;
  66 }
  67
  68 static void print_ddr3_timings(void)
  69 {
  70         printf("\nDDR3\n");
  71         printf("clock:\t\t%d MHz\n", DDR_PLL_FREQ);
  72         printf("device:\t\t%s\n", settings.ddr3.manu_name);
  73         printf("marking:\t%s\n", settings.ddr3.manu_marking);
  74         printf("timing parameters\n");
  75         printf("diff\teeprom\tdefault\n");
  76         PRINTARGS(magic);
  77         PRINTARGS(version);
  78         PRINTARGS(ddr3_sratio);
  79         PRINTARGS(iclkout);
  80
  81         PRINTARGS(dt0rdsratio0);
  82         PRINTARGS(dt0wdsratio0);
  83         PRINTARGS(dt0fwsratio0);
  84         PRINTARGS(dt0wrsratio0);
  85
  86         PRINTARGS(sdram_tim1);
  87         PRINTARGS(sdram_tim2);
  88         PRINTARGS(sdram_tim3);
  89
  90         PRINTARGS(emif_ddr_phy_ctlr_1);
  91
  92         PRINTARGS(sdram_config);
  93         PRINTARGS(ref_ctrl);
  94         PRINTARGS(ioctr_val);
  95 }
  96
  97 static void print_chip_data(void)
  98 {
  99         printf("\nCPU BOARD\n");
 100         printf("device: \t'%s'\n", settings.chip.sdevname);
 101         printf("hw version: \t'%s'\n", settings.chip.shwver);
 102 }
 103 #endif /* CONFIG_SPL_BUILD */
 104
 105 /*
 106  * Read header information from EEPROM into global structure.
 107  */
 108 static int read_eeprom(void)
 109 {
 110         /* Check if baseboard eeprom is available */
 111         if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
 112                 printf("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n");
 113                 return 1;
 114         }
 115
 116 #ifdef CONFIG_SPL_BUILD
 117         /* Read Siemens eeprom data (DDR3) */
 118         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_DDR3, 2,
 119                      (uchar *)&settings.ddr3, sizeof(struct ddr3_data))) {
 120                 printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\nUse default DDR3 timings\n");
 121                 set_default_ddr3_timings();
 122         }
 123         /* Read Siemens eeprom data (CHIP) */
 124         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_CHIP, 2,
 125                      (uchar *)&settings.chip, sizeof(settings.chip)))
 126                 printf("Could not read chip settings\n");
 127
 128         if (ddr3_default.magic == settings.ddr3.magic &&
 129             ddr3_default.version == settings.ddr3.version) {
 130                 printf("Using DDR3 settings from EEPROM\n");
 131         } else {
 132                 if (ddr3_default.magic != settings.ddr3.magic)
 133                         printf("Warning: No valid DDR3 data in eeprom.\n");
 134                 if (ddr3_default.version != settings.ddr3.version)
 135                         printf("Warning: DDR3 data version does not match.\n");
 136
 137                 printf("Using default settings\n");
 138                 set_default_ddr3_timings();
 139         }
 140
 141         if (MAGIC_CHIP == settings.chip.magic) {
 142                 print_chip_data();
 143         } else {
 144                 printf("Warning: No chip data in eeprom\n");
 145         }
 146
 147         print_ddr3_timings();
 148 #endif
 149         return 0;
 150 }
 151
 152 #ifdef CONFIG_SPL_BUILD
 153 static void board_init_ddr(void)
 154 {
 155 struct emif_regs dxr2_ddr3_emif_reg_data = {
 156         .zq_config = 0x50074BE4,
 157 };
 158
 159 struct ddr_data dxr2_ddr3_data = {
 160 };
 161
 162 struct cmd_control dxr2_ddr3_cmd_ctrl_data = {
 163 };
 164
 165 struct ctrl_ioregs dxr2_ddr3_ioregs = {
 166 };
 167
 168         /* pass values from eeprom */
 169         dxr2_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1;
 170         dxr2_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2;
 171         dxr2_ddr3_emif_reg_data.sdram_tim3 = settings.ddr3.sdram_tim3;
 172         dxr2_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 =
 173                 settings.ddr3.emif_ddr_phy_ctlr_1;
 174         dxr2_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config;
 175         dxr2_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl;
 176
 177         dxr2_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0;
 178         dxr2_ddr3_data.datawdsratio0 = settings.ddr3.dt0wdsratio0;
 179         dxr2_ddr3_data.datafwsratio0 = settings.ddr3.dt0fwsratio0;
 180         dxr2_ddr3_data.datawrsratio0 = settings.ddr3.dt0wrsratio0;
 181
 182         dxr2_ddr3_cmd_ctrl_data.cmd0csratio = settings.ddr3.ddr3_sratio;
 183         dxr2_ddr3_cmd_ctrl_data.cmd0iclkout = settings.ddr3.iclkout;
 184         dxr2_ddr3_cmd_ctrl_data.cmd1csratio = settings.ddr3.ddr3_sratio;
 185         dxr2_ddr3_cmd_ctrl_data.cmd1iclkout = settings.ddr3.iclkout;
 186         dxr2_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio;
 187         dxr2_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout;
 188
 189         dxr2_ddr3_ioregs.cm0ioctl = settings.ddr3.ioctr_val,
 190         dxr2_ddr3_ioregs.cm1ioctl = settings.ddr3.ioctr_val,
 191         dxr2_ddr3_ioregs.cm2ioctl = settings.ddr3.ioctr_val,
 192         dxr2_ddr3_ioregs.dt0ioctl = settings.ddr3.ioctr_val,
 193         dxr2_ddr3_ioregs.dt1ioctl = settings.ddr3.ioctr_val,
 194
 195         config_ddr(DDR_PLL_FREQ, &dxr2_ddr3_ioregs, &dxr2_ddr3_data,
 196                    &dxr2_ddr3_cmd_ctrl_data, &dxr2_ddr3_emif_reg_data, 0);
 197 }
 198
 199 static void spl_siemens_board_init(void)
 200 {
 201         return;
 202 }
 203 #endif /* if def CONFIG_SPL_BUILD */
 204
 205 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 206         (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 207 static void cpsw_control(int enabled)
 208 {
 209         /* VTP can be added here */
 210
 211         return;
 212 }
 213
 214 static struct cpsw_slave_data cpsw_slaves[] = {
 215         {
 216                 .slave_reg_ofs  = 0x208,
 217                 .sliver_reg_ofs = 0xd80,
 218                 .phy_addr       = 0,
 219                 .phy_if         = PHY_INTERFACE_MODE_MII,
 220         },
 221 };
 222
 223 static struct cpsw_platform_data cpsw_data = {
 224         .mdio_base              = CPSW_MDIO_BASE,
 225         .cpsw_base              = CPSW_BASE,
 226         .mdio_div               = 0xff,
 227         .channels               = 4,
 228         .cpdma_reg_ofs          = 0x800,
 229         .slaves                 = 1,
 230         .slave_data             = cpsw_slaves,
 231         .ale_reg_ofs            = 0xd00,
 232         .ale_entries            = 1024,
 233         .host_port_reg_ofs      = 0x108,
 234         .hw_stats_reg_ofs       = 0x900,
 235         .bd_ram_ofs             = 0x2000,
 236         .mac_control            = (1 << 5),
 237         .control                = cpsw_control,
 238         .host_port_num          = 0,
 239         .version                = CPSW_CTRL_VERSION_2,
 240 };
 241
 242 #if defined(CONFIG_DRIVER_TI_CPSW) || \
 243         (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
 244 int board_eth_init(bd_t *bis)
 245 {
 246         struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 247         int n = 0;
 248         int rv;
 249
 250         factoryset_setenv();
 251
 252         /* Set rgmii mode and enable rmii clock to be sourced from chip */
 253         writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
 254
 255         rv = cpsw_register(&cpsw_data);
 256         if (rv < 0)
 257                 printf("Error %d registering CPSW switch\n", rv);
 258         else
 259                 n += rv;
 260         return n;
 261 }
 262
 263 static int do_switch_reset(cmd_tbl_t *cmdtp, int flag, int argc,
 264                            char *const argv[])
 265 {
 266         /* Reset SMSC LAN9303 switch for default configuration */
 267         gpio_request(GPIO_LAN9303_NRST, "nRST");
 268         gpio_direction_output(GPIO_LAN9303_NRST, 0);
 269         /* assert active low reset for 200us */
 270         udelay(200);
 271         gpio_set_value(GPIO_LAN9303_NRST, 1);
 272
 273         return 0;
 274 };
 275
 276 U_BOOT_CMD(
 277         switch_rst, CONFIG_SYS_MAXARGS, 1,      do_switch_reset,
 278         "Reset LAN9303 switch via its reset pin",
 279         ""
 280 );
 281 #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
 282 #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
 283
 284 #include "../common/board.c"