2 * (C) Copyright 2001, 2002
3 * Dave Ellis, SIXNET, dge@sixnetio.com.
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * and other contributors to U-Boot. See file CREDITS for list
7 * of people who contributed to this project.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <net.h> /* for eth_init() */
32 #define ORMASK(size) ((-size) & OR_AM_MSK)
34 static long ram_size(ulong *, long);
36 /* ------------------------------------------------------------------------- */
39 * Check Board Identity:
40 * returns 0 if recognized, -1 if unknown
45 puts ("Board: SIXNET SXNI855T\n");
49 /* ------------------------------------------------------------------------- */
51 #if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
52 #error "SXNI855T has no PCMCIA port"
53 #endif /* CFG_CMD_PCMCIA */
55 /* ------------------------------------------------------------------------- */
57 #define _not_used_ 0xffffffff
59 /* UPMB table for dual UART. */
61 /* this table is for 50MHz operation, it should work at all lower speeds */
62 const uint duart_table[] =
64 /* single read. (offset 0 in upm RAM) */
65 0xfffffc04, 0x0ffffc04, 0x0ff3fc04, 0x0ff3fc04,
66 0x0ff3fc00, 0x0ff3fc04, 0xfffffc04, 0xfffffc05,
68 /* burst read. (offset 8 in upm RAM) */
69 _not_used_, _not_used_, _not_used_, _not_used_,
70 _not_used_, _not_used_, _not_used_, _not_used_,
71 _not_used_, _not_used_, _not_used_, _not_used_,
72 _not_used_, _not_used_, _not_used_, _not_used_,
74 /* single write. (offset 18 in upm RAM) */
75 0xfffffc04, 0x0ffffc04, 0x00fffc04, 0x00fffc04,
76 0x00fffc04, 0x00fffc00, 0xfffffc04, 0xfffffc05,
78 /* burst write. (offset 20 in upm RAM) */
79 _not_used_, _not_used_, _not_used_, _not_used_,
80 _not_used_, _not_used_, _not_used_, _not_used_,
81 _not_used_, _not_used_, _not_used_, _not_used_,
82 _not_used_, _not_used_, _not_used_, _not_used_,
84 /* refresh. (offset 30 in upm RAM) */
85 _not_used_, _not_used_, _not_used_, _not_used_,
86 _not_used_, _not_used_, _not_used_, _not_used_,
87 _not_used_, _not_used_, _not_used_, _not_used_,
89 /* exception. (offset 3c in upm RAM) */
90 _not_used_, _not_used_, _not_used_, _not_used_,
93 /* Load FPGA very early in boot sequence, since it must be
94 * loaded before the 16C2550 serial channels can be used as
97 * Note: Much of the configuration is not complete. The
98 * stack is in DPRAM since SDRAM has not been initialized,
99 * so the stack must be kept small. Global variables
100 * are still in FLASH, so they cannot be written.
101 * Only the FLASH, DPRAM, immap and FPGA can be addressed,
102 * the other chip selects may not have been initialized.
103 * The clocks have been initialized, so udelay() can be
106 #define FPGA_DONE 0x0080 /* PA8, input, high when FPGA load complete */
107 #define FPGA_PROGRAM_L 0x0040 /* PA9, output, low to reset, high to start */
108 #define FPGA_INIT_L 0x0020 /* PA10, input, low indicates not ready */
109 #define fpga (*(volatile unsigned char *)(CFG_FPGA_PROG)) /* FPGA port */
111 int board_postclk_init (void)
114 /* the data to load to the XCSxxXL FPGA */
115 static const unsigned char fpgadata[] = {
116 # include "fpgadata.c"
119 volatile immap_t *immap = (immap_t *)CFG_IMMR;
120 volatile memctl8xx_t *memctl = &immap->im_memctl;
121 #define porta (immap->im_ioport.iop_padat)
122 const unsigned char* pdata;
124 /* /INITFPGA and DONEFPGA signals are inputs */
125 immap->im_ioport.iop_padir &= ~(FPGA_INIT_L | FPGA_DONE);
127 /* Force output pin to begin at 0, /PROGRAM asserted (0) resets FPGA */
128 porta &= ~FPGA_PROGRAM_L;
130 /* Set FPGA as an output */
131 immap->im_ioport.iop_padir |= FPGA_PROGRAM_L;
133 /* delay a little to make sure FPGA sees it, really
134 * only need less than a microsecond.
138 /* unassert /PROGRAM */
139 porta |= FPGA_PROGRAM_L;
141 /* delay while FPGA does last erase, indicated by
142 * /INITFPGA going high. This should happen within a
145 /* ### FIXME - a timeout check would be good, maybe flash
146 * the status LED to indicate the error?
148 while ((porta & FPGA_INIT_L) == 0)
151 /* write program data to FPGA at the programming address
152 * so extra /CS1 strobes at end of configuration don't actually
153 * write to any registers.
155 fpga = 0xff; /* first write is ignored */
156 fpga = 0xff; /* fill byte */
157 fpga = 0xff; /* fill byte */
158 fpga = 0x4f; /* preamble code */
159 fpga = 0x80; fpga = 0xaf; fpga = 0x9b; /* length (ignored) */
160 fpga = 0x4b; /* field check code */
163 /* while no error write out each of the 28 byte frames */
164 while ((porta & (FPGA_INIT_L | FPGA_DONE)) == FPGA_INIT_L
165 && pdata < fpgadata + sizeof(fpgadata)) {
167 fpga = 0x4f; /* preamble code */
169 /* 21 bytes of data in a frame */
170 fpga = *(pdata++); fpga = *(pdata++);
171 fpga = *(pdata++); fpga = *(pdata++);
172 fpga = *(pdata++); fpga = *(pdata++);
173 fpga = *(pdata++); fpga = *(pdata++);
174 fpga = *(pdata++); fpga = *(pdata++);
175 fpga = *(pdata++); fpga = *(pdata++);
176 fpga = *(pdata++); fpga = *(pdata++);
177 fpga = *(pdata++); fpga = *(pdata++);
178 fpga = *(pdata++); fpga = *(pdata++);
179 fpga = *(pdata++); fpga = *(pdata++);
182 fpga = 0x4b; /* field check code */
183 fpga = 0xff; /* extended write cycle */
184 fpga = 0x4b; /* extended write cycle
185 * (actually 0x4b from bitgen.exe)
187 fpga = 0xff; /* extended write cycle */
188 fpga = 0xff; /* extended write cycle */
189 fpga = 0xff; /* extended write cycle */
192 fpga = 0xff; /* startup byte */
193 fpga = 0xff; /* startup byte */
194 fpga = 0xff; /* startup byte */
195 fpga = 0xff; /* startup byte */
197 #if 0 /* ### FIXME */
198 /* If didn't load all the data or FPGA_DONE is low the load failed.
199 * Maybe someday stop here and flash the status LED? The console
200 * is not configured, so can't print an error message. Can't write
201 * global variables to set a flag (except gd?).
202 * For now it must work.
206 /* Now that the FPGA is loaded, set up the Dual UART chip
207 * selects. Must be done here since it may be used as the console.
209 upmconfig(UPMB, (uint *)duart_table, sizeof(duart_table)/sizeof(uint));
211 memctl->memc_mbmr = DUART_MBMR;
212 memctl->memc_or5 = DUART_OR_VALUE;
213 memctl->memc_br5 = DUART_BR5_VALUE;
214 memctl->memc_or6 = DUART_OR_VALUE;
215 memctl->memc_br6 = DUART_BR6_VALUE;
220 /* ------------------------------------------------------------------------- */
222 /* base address for SRAM, assume 32-bit port, valid */
223 #define NVRAM_BR_VALUE (CFG_SRAM_BASE | BR_PS_32 | BR_V)
225 /* up to 64MB - will be adjusted for actual size */
226 #define NVRAM_OR_PRELIM (ORMASK(CFG_SRAM_SIZE) \
227 | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_5_CLK | OR_EHTR)
229 * Miscellaneous platform dependent initializations after running in RAM.
232 int misc_init_r (void)
234 DECLARE_GLOBAL_DATA_PTR;
236 volatile immap_t *immap = (immap_t *)CFG_IMMR;
237 volatile memctl8xx_t *memctl = &immap->im_memctl;
240 memctl->memc_or2 = NVRAM_OR_PRELIM;
241 memctl->memc_br2 = NVRAM_BR_VALUE;
243 /* Is there any SRAM? Is it 16 or 32 bits wide? */
245 /* First look for 32-bit SRAM */
246 bd->bi_sramsize = ram_size((ulong*)CFG_SRAM_BASE, CFG_SRAM_SIZE);
248 if (bd->bi_sramsize == 0) {
249 /* no 32-bit SRAM, but there could be 16-bit SRAM since
250 * it would report size 0 when configured for 32-bit bus.
251 * Try again with a 16-bit bus.
253 memctl->memc_br2 |= BR_PS_16;
254 bd->bi_sramsize = ram_size((ulong*)CFG_SRAM_BASE, CFG_SRAM_SIZE);
257 if (bd->bi_sramsize == 0) {
258 memctl->memc_br2 = 0; /* disable select since nothing there */
261 /* adjust or2 for actual size of SRAM */
262 memctl->memc_or2 |= ORMASK(bd->bi_sramsize);
263 bd->bi_sramstart = CFG_SRAM_BASE;
264 printf("SRAM: %lu KB\n", bd->bi_sramsize >> 10);
268 /* set standard MPC8xx clock so kernel will see the time
269 * even if it doesn't have a DS1306 clock driver.
270 * This helps with experimenting with standard kernels.
276 rtc_get(&tmp); /* get time from DS1306 RTC */
278 /* convert to seconds since 1970 */
279 tim = mktime(tmp.tm_year, tmp.tm_mon, tmp.tm_mday,
280 tmp.tm_hour, tmp.tm_min, tmp.tm_sec);
282 immap->im_sitk.sitk_rtck = KAPWR_KEY;
283 immap->im_sit.sit_rtc = tim;
287 /* The code below is no longer valid since the prototype of
288 * eth_init() and eth_halt() have been changed to support
289 * multi-ethernet feature in U-Boot; the eth_initialize()
290 * routine should be called before any access to the ethernet
294 /* FIXME - for now init ethernet to force PHY special mode */
301 /* ------------------------------------------------------------------------- */
304 * Check memory range for valid RAM. A simple memory test determines
305 * the actually available RAM size between addresses `base' and
308 * The memory size MUST be a power of 2 for this to work.
310 * The only memory modified is 4 bytes at offset 0. This is important
311 * since for the SRAM this location is reserved for autosizing, so if
312 * it is modified and the board is reset before ram_size() completes
313 * no damage is done. Normally even the memory at 0 is preserved. The
314 * higher SRAM addresses may contain battery backed RAM disk data which
315 * must never be corrupted.
318 static long ram_size(ulong *base, long maxsize)
320 volatile long *test_addr;
321 volatile long *base_addr = base;
322 volatile long *flash = (volatile long*)CFG_FLASH_BASE;
323 ulong ofs; /* byte offset from base_addr */
324 ulong save; /* to make test non-destructive */
326 long ramsize = -1; /* size not determined yet */
328 save = *base_addr; /* save value at 0 so can restore */
330 /* is any SRAM present? */
331 *base_addr = 0x5555aaaa;
333 /* use flash read to modify data bus, since with no SRAM present
334 * the data bus may retain the value if our code is running
335 * completely in the cache.
339 if (*base_addr != 0x5555aaaa)
340 ramsize = 0; /* no RAM present, or defective */
342 *base_addr = 0xaaaa5555;
343 junk = *flash; /* use flash read to modify data bus */
344 if (*base_addr != 0xaaaa5555)
345 ramsize = 0; /* no RAM present, or defective */
348 /* now size it if any is present */
349 for (ofs = 4; ofs < maxsize && ramsize < 0; ofs <<= 1) {
350 test_addr = (long*)((long)base_addr + ofs); /* location to test */
352 *base_addr = ~*test_addr;
353 if (*base_addr == *test_addr)
354 ramsize = ofs; /* wrapped back to 0, so this is the size */
357 *base_addr = save; /* restore value at 0 */
361 /* ------------------------------------------------------------------------- */
362 /* sdram table based on the FADS manual */
363 /* for chip MB811171622A-100 */
365 /* this table is for 50MHz operation, it should work at all lower speeds */
367 const uint sdram_table[] =
369 /* single read. (offset 0 in upm RAM) */
370 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
373 /* precharge and Mode Register Set initialization (offset 5).
374 * This is also entered at offset 6 to do Mode Register Set
375 * without the precharge.
377 0x1ff77c34, 0xefeabc34, 0x1fb57c35,
379 /* burst read. (offset 8 in upm RAM) */
380 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
381 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
382 _not_used_, _not_used_, _not_used_, _not_used_,
383 _not_used_, _not_used_, _not_used_, _not_used_,
385 /* single write. (offset 18 in upm RAM) */
386 /* FADS had 0x1f27fc04, ...
387 * but most other boards have 0x1f07fc04, which
388 * sets GPL0 from A11MPC to 0 1/4 clock earlier,
389 * like the single read.
390 * This seems better so I am going with the change.
392 0x1f07fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
393 _not_used_, _not_used_, _not_used_, _not_used_,
395 /* burst write. (offset 20 in upm RAM) */
396 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
397 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _not_used_,
398 _not_used_, _not_used_, _not_used_, _not_used_,
399 _not_used_, _not_used_, _not_used_, _not_used_,
401 /* refresh. (offset 30 in upm RAM) */
402 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
403 0xfffffc84, 0xfffffc07, _not_used_, _not_used_,
404 _not_used_, _not_used_, _not_used_, _not_used_,
406 /* exception. (offset 3c in upm RAM) */
407 0x7ffffc07, _not_used_, _not_used_, _not_used_ };
409 /* ------------------------------------------------------------------------- */
411 #define SDRAM_MAX_SIZE 0x10000000 /* max 256 MB SDRAM */
413 /* precharge and set Mode Register */
414 #define SDRAM_MCR_PRE (MCR_OP_RUN | MCR_UPM_A | /* select UPM */ \
415 MCR_MB_CS3 | /* chip select */ \
416 MCR_MLCF(1) | MCR_MAD(5)) /* 1 time at 0x05 */
418 /* set Mode Register, no precharge */
419 #define SDRAM_MCR_MRS (MCR_OP_RUN | MCR_UPM_A | /* select UPM */ \
420 MCR_MB_CS3 | /* chip select */ \
421 MCR_MLCF(1) | MCR_MAD(6)) /* 1 time at 0x06 */
423 /* runs refresh loop twice so get 8 refresh cycles */
424 #define SDRAM_MCR_REFR (MCR_OP_RUN | MCR_UPM_A | /* select UPM */ \
425 MCR_MB_CS3 | /* chip select */ \
426 MCR_MLCF(2) | MCR_MAD(0x30)) /* twice at 0x30 */
428 /* MAMR values work in either mamr or mbmr */
430 #define SDRAM_MAMR_8COL /* refresh at 50MHz */ \
431 ((195 << MAMR_PTA_SHIFT) | MAMR_PTAE \
432 | MAMR_AMA_TYPE_0 /* Address MUX 0 */ \
433 | MAMR_DSA_1_CYCL /* 1 cycle disable */ \
434 | MAMR_G0CLA_A11 /* GPL0 A11[MPC] */ \
435 | MAMR_RLFA_1X /* Read loop 1 time */ \
436 | MAMR_WLFA_1X /* Write loop 1 time */ \
437 | MAMR_TLFA_4X) /* Timer loop 4 times */
440 #define SDRAM_MAMR_9COL ((SDRAM_MAMR_8COL & (~MAMR_G0CLA_A11)) | MAMR_G0CLA_A10)
442 /* base address 0, 32-bit port, SDRAM UPM, valid */
443 #define SDRAM_BR_VALUE (BR_PS_32 | BR_MS_UPMA | BR_V)
445 /* up to 256MB, SAM, G5LS - will be adjusted for actual size */
446 #define SDRAM_OR_PRELIM (ORMASK(SDRAM_MAX_SIZE) | OR_CSNT_SAM | OR_G5LS)
448 /* This is the Mode Select Register value for the SDRAM.
450 * Burst Type: sequential
452 * Write Burst Length: burst
454 #define SDRAM_MODE 0x22 /* CAS latency 2, burst length 4 */
456 /* ------------------------------------------------------------------------- */
458 long int initdram(int board_type)
460 volatile immap_t *immap = (immap_t *)CFG_IMMR;
461 volatile memctl8xx_t *memctl = &immap->im_memctl;
463 uint size_sdram9 = 0;
464 uint base = 0; /* SDRAM must start at 0 */
467 upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
469 /* Configure the refresh (mostly). This needs to be
470 * based upon processor clock speed and optimized to provide
471 * the highest level of performance.
473 * Preliminary prescaler for refresh.
474 * This value is selected for four cycles in 31.2 us,
475 * which gives 8192 cycles in 64 milliseconds.
476 * This may be too fast, but works for any memory.
477 * It is adjusted to 4096 cycles in 64 milliseconds if
478 * possible once we know what memory we have.
480 * We have to be careful changing UPM registers after we
481 * ask it to run these commands.
483 * PTA - periodic timer period for our design is
485 * --------------- = 195
489 * 31.2us refresh interval
494 memctl->memc_mptpr = MPTPR_PTP_DIV8; /* 0x0800 */
495 memctl->memc_mamr = SDRAM_MAMR_8COL & (~MAMR_PTAE); /* no refresh yet */
497 /* The SDRAM Mode Register value is shifted left 2 bits since
498 * A30 and A31 don't connect to the SDRAM for 32-bit wide memory.
500 memctl->memc_mar = SDRAM_MODE << 2; /* MRS code */
501 udelay(200); /* SDRAM needs 200uS before set it up */
503 /* Now run the precharge/nop/mrs commands. */
504 memctl->memc_mcr = SDRAM_MCR_PRE;
507 /* Run 8 refresh cycles (2 sets of 4) */
508 memctl->memc_mcr = SDRAM_MCR_REFR; /* run refresh twice */
511 /* some brands want Mode Register set after the refresh
512 * cycles. This shouldn't hurt anything for the brands
513 * that were happy with the first time we set it.
515 memctl->memc_mcr = SDRAM_MCR_MRS;
518 memctl->memc_mamr = SDRAM_MAMR_8COL; /* enable refresh */
519 memctl->memc_or3 = SDRAM_OR_PRELIM;
520 memctl->memc_br3 = SDRAM_BR_VALUE + base;
522 /* Some brands need at least 10 DRAM accesses to stabilize.
523 * It wont hurt the brands that don't.
525 for (i=0; i<10; ++i) {
526 volatile ulong *addr = (volatile ulong *)base;
533 /* Check SDRAM memory Size in 8 column mode.
534 * For a 9 column memory we will get half the actual size.
536 size_sdram = ram_size((ulong *)0, SDRAM_MAX_SIZE);
538 /* Check SDRAM memory Size in 9 column mode.
539 * For an 8 column memory we will see at most 4 megabytes.
541 memctl->memc_mamr = SDRAM_MAMR_9COL;
542 size_sdram9 = ram_size((ulong *)0, SDRAM_MAX_SIZE);
544 if (size_sdram < size_sdram9) /* leave configuration at 9 columns */
545 size_sdram = size_sdram9;
546 else /* go back to 8 columns */
547 memctl->memc_mamr = SDRAM_MAMR_8COL;
549 /* adjust or3 for actual size of SDRAM
551 memctl->memc_or3 |= ORMASK(size_sdram);
553 /* Adjust refresh rate depending on SDRAM type.
554 * For types > 128 MBit (32 Mbyte for 2 x16 devices) leave
555 * it at the current (fast) rate.
556 * For 16, 64 and 128 MBit half the rate will do.
558 if (size_sdram <= 32 * 1024 * 1024)
559 memctl->memc_mptpr = MPTPR_PTP_DIV16; /* 0x0400 */