4 prompt "Sunxi SoC Variant"
7 bool "sun4i (Allwinner A10)"
12 bool "sun5i (Allwinner A13)"
17 bool "sun6i (Allwinner A31)"
22 bool "sun7i (Allwinner A20)"
24 select CPU_V7_HAS_NONSEC
25 select CPU_V7_HAS_VIRT
27 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
30 bool "sun8i (Allwinner A23)"
37 int "sunxi dram clock speed"
38 default 312 if MACH_SUN6I || MACH_SUN8I
39 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
41 Set the dram clock speed, valid range 240 - 480, must be a multiple
44 if MACH_SUN5I || MACH_SUN7I
46 int "sunxi mbus clock speed"
49 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
54 int "sunxi dram zq value"
55 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
56 default 127 if MACH_SUN7I
58 Set the dram zq value.
60 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
62 int "sunxi dram emr1 value"
63 default 0 if MACH_SUN4I
64 default 4 if MACH_SUN5I || MACH_SUN7I
66 Set the dram controller emr1 value.
69 int "sunxi dram odt_en value"
72 Set the dram controller odt_en parameter. This can be used to
73 enable/disable the ODT feature.
76 hex "sunxi dram tpr3 value"
79 Set the dram controller tpr3 parameter. This parameter configures
80 the delay on the command lane and also phase shifts, which are
81 applied for sampling incoming read data. The default value 0
82 means that no phase/delay adjustments are necessary. Properly
83 configuring this parameter increases reliability at high DRAM
86 config DRAM_DQS_GATING_DELAY
87 hex "sunxi dram dqs_gating_delay value"
90 Set the dram controller dqs_gating_delay parmeter. Each byte
91 encodes the DQS gating delay for each byte lane. The delay
92 granularity is 1/4 cycle. For example, the value 0x05060606
93 means that the delay is 5 quarter-cycles for one lane (1.25
94 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
95 The default value 0 means autodetection. The results of hardware
96 autodetection are not very reliable and depend on the chip
97 temperature (sometimes producing different results on cold start
98 and warm reboot). But the accuracy of hardware autodetection
99 is usually good enough, unless running at really high DRAM
100 clocks speeds (up to 600MHz). If unsure, keep as 0.
103 prompt "sunxi dram timings"
104 default DRAM_TIMINGS_VENDOR_MAGIC
106 Select the timings of the DDR3 chips.
108 config DRAM_TIMINGS_VENDOR_MAGIC
109 bool "Magic vendor timings from Android"
111 The same DRAM timings as in the Allwinner boot0 bootloader.
113 config DRAM_TIMINGS_DDR3_1066F_1333H
114 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
116 Use the timings of the standard JEDEC DDR3-1066F speed bin for
117 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
118 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
119 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
120 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
121 that down binning to DDR3-1066F is supported (because DDR3-1066F
122 uses a bit faster timings than DDR3-1333H).
124 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
125 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
127 Use the timings of the slowest possible JEDEC speed bin for the
128 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
129 DDR3-800E, DDR3-1066G or DDR3-1333J.
136 default 912000000 if MACH_SUN7I
137 default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
139 config SYS_CONFIG_NAME
140 default "sun4i" if MACH_SUN4I
141 default "sun5i" if MACH_SUN5I
142 default "sun6i" if MACH_SUN6I
143 default "sun7i" if MACH_SUN7I
144 default "sun8i" if MACH_SUN8I
153 bool "SPL/FEL mode support"
157 This enables support for Fast Early Loader (FEL) mode. This
158 allows U-Boot to be loaded to the board over USB by the on-chip
159 boot rom. U-Boot should be sent in two parts: SPL first, with
160 'fel write 0x2000 u-boot-spl.bin; fel exe 0x2000' then U-Boot with
161 'fel write 0x4a000000 u-boot.bin; fel exe 0x4a000000'. This option
162 shrinks the amount of SRAM available to SPL, so only enable it if
163 you need FEL. Note that enabling this option only allows FEL to be
164 used; it is still possible to boot U-Boot from boot media. U-Boot
165 SPL detects when it is being loaded using FEL.
168 bool "UART0 on MicroSD breakout board"
172 Repurpose the SD card slot for getting access to the UART0 serial
173 console. Primarily useful only for low level u-boot debugging on
174 tablets, where normal UART0 is difficult to access and requires
175 device disassembly and/or soldering. As the SD card can't be used
176 at the same time, the system can be only booted in the FEL mode.
177 Only enable this if you really know what you are doing.
180 string "Default fdtfile env setting for this board"
182 config OLD_SUNXI_KERNEL_COMPAT
183 boolean "Enable workarounds for booting old kernels"
186 Set this to enable various workarounds for old kernels, this results in
187 sub-optimal settings for newer kernels, only enable if needed.
190 string "Card detect pin for mmc0"
193 Set the card detect pin for mmc0, leave empty to not use cd. This
194 takes a string in the format understood by sunxi_name_to_gpio, e.g.
195 PH1 for pin 1 of port H.
198 string "Card detect pin for mmc1"
201 See MMC0_CD_PIN help text.
204 string "Card detect pin for mmc2"
207 See MMC0_CD_PIN help text.
210 string "Card detect pin for mmc3"
213 See MMC0_CD_PIN help text.
215 config MMC_SUNXI_SLOT_EXTRA
216 int "mmc extra slot number"
219 sunxi builds always enable mmc0, some boards also have a second sdcard
220 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
224 string "Vbus enable pin for usb0 (otg)"
227 Set the Vbus enable pin for usb0 (otg). This takes a string in the
228 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
231 string "Vbus detect pin for usb0 (otg)"
234 Set the Vbus detect pin for usb0 (otg). This takes a string in the
235 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
238 string "Vbus enable pin for usb1 (ehci0)"
239 default "PH6" if MACH_SUN4I || MACH_SUN7I
240 default "PH27" if MACH_SUN6I
242 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
243 a string in the format understood by sunxi_name_to_gpio, e.g.
244 PH1 for pin 1 of port H.
247 string "Vbus enable pin for usb2 (ehci1)"
248 default "PH3" if MACH_SUN4I || MACH_SUN7I
249 default "PH24" if MACH_SUN6I
251 See USB1_VBUS_PIN help text.
254 boolean "Enable graphical uboot console on HDMI, LCD or VGA"
257 Say Y here to add support for using a cfb console on the HDMI, LCD
258 or VGA output found on most sunxi devices. See doc/README.video for
259 info on how to select the video output and mode.
262 boolean "HDMI output support"
263 depends on VIDEO && !MACH_SUN8I
266 Say Y here to add support for outputting video over HDMI.
269 boolean "VGA output support"
270 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
273 Say Y here to add support for outputting video over VGA.
275 config VIDEO_VGA_VIA_LCD
276 boolean "VGA via LCD controller support"
277 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
280 Say Y here to add support for external DACs connected to the parallel
281 LCD interface driving a VGA connector, such as found on the
284 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
285 boolean "Force sync active high for VGA via LCD controller support"
286 depends on VIDEO_VGA_VIA_LCD
289 Say Y here if you've a board which uses opendrain drivers for the vga
290 hsync and vsync signals. Opendrain drivers cannot generate steep enough
291 positive edges for a stable video output, so on boards with opendrain
292 drivers the sync signals must always be active high.
294 config VIDEO_VGA_EXTERNAL_DAC_EN
295 string "LCD panel power enable pin"
296 depends on VIDEO_VGA_VIA_LCD
299 Set the enable pin for the external VGA DAC. This takes a string in the
300 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
302 config VIDEO_LCD_MODE
303 string "LCD panel timing details"
307 LCD panel timing details string, leave empty if there is no LCD panel.
308 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
309 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
311 config VIDEO_LCD_DCLK_PHASE
312 int "LCD panel display clock phase"
316 Select LCD panel display clock phase shift, range 0-3.
318 config VIDEO_LCD_POWER
319 string "LCD panel power enable pin"
323 Set the power enable pin for the LCD panel. This takes a string in the
324 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
326 config VIDEO_LCD_RESET
327 string "LCD panel reset pin"
331 Set the reset pin for the LCD panel. This takes a string in the format
332 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
334 config VIDEO_LCD_BL_EN
335 string "LCD panel backlight enable pin"
339 Set the backlight enable pin for the LCD panel. This takes a string in the
340 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
343 config VIDEO_LCD_BL_PWM
344 string "LCD panel backlight pwm pin"
348 Set the backlight pwm pin for the LCD panel. This takes a string in the
349 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
351 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
352 bool "LCD panel backlight pwm is inverted"
356 Set this if the backlight pwm output is active low.
358 config VIDEO_LCD_PANEL_I2C
359 bool "LCD panel needs to be configured via i2c"
363 Say y here if the LCD panel needs to be configured via i2c. This
364 will add a bitbang i2c controller using gpios to talk to the LCD.
366 config VIDEO_LCD_PANEL_I2C_SDA
367 string "LCD panel i2c interface SDA pin"
368 depends on VIDEO_LCD_PANEL_I2C
371 Set the SDA pin for the LCD i2c interface. This takes a string in the
372 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
374 config VIDEO_LCD_PANEL_I2C_SCL
375 string "LCD panel i2c interface SCL pin"
376 depends on VIDEO_LCD_PANEL_I2C
379 Set the SCL pin for the LCD i2c interface. This takes a string in the
380 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
383 # Note only one of these may be selected at a time! But hidden choices are
384 # not supported by Kconfig
385 config VIDEO_LCD_IF_PARALLEL
388 config VIDEO_LCD_IF_LVDS
393 prompt "LCD panel support"
396 Select which type of LCD panel to support.
398 config VIDEO_LCD_PANEL_PARALLEL
399 bool "Generic parallel interface LCD panel"
400 select VIDEO_LCD_IF_PARALLEL
402 config VIDEO_LCD_PANEL_LVDS
403 bool "Generic lvds interface LCD panel"
404 select VIDEO_LCD_IF_LVDS
406 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
407 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
408 select VIDEO_LCD_SSD2828
409 select VIDEO_LCD_IF_PARALLEL
411 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
413 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
414 bool "Hitachi tx18d42vm LCD panel"
415 select VIDEO_LCD_HITACHI_TX18D42VM
416 select VIDEO_LCD_IF_LVDS
418 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
420 config VIDEO_LCD_TL059WV5C0
421 bool "tl059wv5c0 LCD panel"
422 select VIDEO_LCD_PANEL_I2C
423 select VIDEO_LCD_IF_PARALLEL
425 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
426 Aigo M60/M608/M606 tablets.
431 config USB_MUSB_SUNXI
432 bool "Enable sunxi OTG / DRC USB controller in host mode"
435 Say y here to enable support for the sunxi OTG / DRC USB controller
436 used on almost all sunxi boards. Note currently u-boot can only have
437 one usb host controller enabled at a time, so enabling this on boards
438 which also use the ehci host controller will result in build errors.
441 boolean "Enable USB keyboard support"
444 Say Y here to add support for using a USB keyboard (typically used
445 in combination with a graphical console).
448 int "GMAC Transmit Clock Delay Chain"
451 Set the GMAC Transmit Clock Delay Chain value.