3 config SPL_GPIO_SUPPORT
6 config SPL_LIBCOMMON_SUPPORT
9 config SPL_LIBDISK_SUPPORT
12 config SPL_LIBGENERIC_SUPPORT
15 # Note only one of these may be selected at a time! But hidden choices are
16 # not supported by Kconfig
17 config SUNXI_GEN_SUN4I
20 Select this for sunxi SoCs which have resets and clocks set up
21 as the original A10 (mach-sun4i).
23 config SUNXI_GEN_SUN6I
26 Select this for sunxi SoCs which have sun6i like periphery, like
27 separate ahb reset control registers, custom pmic bus, new style
32 prompt "Sunxi SoC Variant"
36 bool "sun4i (Allwinner A10)"
38 select SUNXI_GEN_SUN4I
42 bool "sun5i (Allwinner A13)"
44 select SUNXI_GEN_SUN4I
48 bool "sun6i (Allwinner A31)"
50 select CPU_V7_HAS_NONSEC
51 select CPU_V7_HAS_VIRT
52 select ARCH_SUPPORT_PSCI
53 select SUNXI_GEN_SUN6I
55 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
58 bool "sun7i (Allwinner A20)"
60 select CPU_V7_HAS_NONSEC
61 select CPU_V7_HAS_VIRT
62 select ARCH_SUPPORT_PSCI
63 select SUNXI_GEN_SUN4I
65 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
68 bool "sun8i (Allwinner A23)"
70 select CPU_V7_HAS_NONSEC
71 select CPU_V7_HAS_VIRT
72 select ARCH_SUPPORT_PSCI
73 select SUNXI_GEN_SUN6I
75 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
78 bool "sun8i (Allwinner A33)"
80 select CPU_V7_HAS_NONSEC
81 select CPU_V7_HAS_VIRT
82 select ARCH_SUPPORT_PSCI
83 select SUNXI_GEN_SUN6I
85 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
87 config MACH_SUN8I_A83T
88 bool "sun8i (Allwinner A83T)"
90 select SUNXI_GEN_SUN6I
94 bool "sun8i (Allwinner H3)"
96 select CPU_V7_HAS_NONSEC
97 select CPU_V7_HAS_VIRT
98 select ARCH_SUPPORT_PSCI
99 select SUNXI_GEN_SUN6I
101 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
104 bool "sun9i (Allwinner A80)"
106 select SUNXI_GEN_SUN6I
109 bool "sun50i (Allwinner A64)"
111 select SUNXI_GEN_SUN6I
115 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
118 default y if MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_H3 || MACH_SUN8I_A83T
121 int "sunxi dram type"
122 depends on MACH_SUN8I_A83T
125 Set the dram type, 3: DDR3, 7: LPDDR3
128 int "sunxi dram clock speed"
129 default 312 if MACH_SUN6I || MACH_SUN8I
130 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
132 Set the dram clock speed, valid range 240 - 480, must be a multiple
135 if MACH_SUN5I || MACH_SUN7I
137 int "sunxi mbus clock speed"
140 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
145 int "sunxi dram zq value"
146 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
147 default 127 if MACH_SUN7I
149 Set the dram zq value.
152 bool "sunxi dram odt enable"
153 default n if !MACH_SUN8I_A23
154 default y if MACH_SUN8I_A23
156 Select this to enable dram odt (on die termination).
158 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
160 int "sunxi dram emr1 value"
161 default 0 if MACH_SUN4I
162 default 4 if MACH_SUN5I || MACH_SUN7I
164 Set the dram controller emr1 value.
167 hex "sunxi dram tpr3 value"
170 Set the dram controller tpr3 parameter. This parameter configures
171 the delay on the command lane and also phase shifts, which are
172 applied for sampling incoming read data. The default value 0
173 means that no phase/delay adjustments are necessary. Properly
174 configuring this parameter increases reliability at high DRAM
177 config DRAM_DQS_GATING_DELAY
178 hex "sunxi dram dqs_gating_delay value"
181 Set the dram controller dqs_gating_delay parmeter. Each byte
182 encodes the DQS gating delay for each byte lane. The delay
183 granularity is 1/4 cycle. For example, the value 0x05060606
184 means that the delay is 5 quarter-cycles for one lane (1.25
185 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
186 The default value 0 means autodetection. The results of hardware
187 autodetection are not very reliable and depend on the chip
188 temperature (sometimes producing different results on cold start
189 and warm reboot). But the accuracy of hardware autodetection
190 is usually good enough, unless running at really high DRAM
191 clocks speeds (up to 600MHz). If unsure, keep as 0.
194 prompt "sunxi dram timings"
195 default DRAM_TIMINGS_VENDOR_MAGIC
197 Select the timings of the DDR3 chips.
199 config DRAM_TIMINGS_VENDOR_MAGIC
200 bool "Magic vendor timings from Android"
202 The same DRAM timings as in the Allwinner boot0 bootloader.
204 config DRAM_TIMINGS_DDR3_1066F_1333H
205 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
207 Use the timings of the standard JEDEC DDR3-1066F speed bin for
208 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
209 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
210 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
211 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
212 that down binning to DDR3-1066F is supported (because DDR3-1066F
213 uses a bit faster timings than DDR3-1333H).
215 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
216 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
218 Use the timings of the slowest possible JEDEC speed bin for the
219 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
220 DDR3-800E, DDR3-1066G or DDR3-1333J.
227 config DRAM_ODT_CORRECTION
228 int "sunxi dram odt correction value"
231 Set the dram odt correction value (range -255 - 255). In allwinner
232 fex files, this option is found in bits 8-15 of the u32 odt_en variable
233 in the [dram] section. When bit 31 of the odt_en variable is set
234 then the correction is negative. Usually the value for this is 0.
238 default 816000000 if MACH_SUN50I
239 default 912000000 if MACH_SUN7I
240 default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
242 config SYS_CONFIG_NAME
243 default "sun4i" if MACH_SUN4I
244 default "sun5i" if MACH_SUN5I
245 default "sun6i" if MACH_SUN6I
246 default "sun7i" if MACH_SUN7I
247 default "sun8i" if MACH_SUN8I
248 default "sun9i" if MACH_SUN9I
249 default "sun50i" if MACH_SUN50I
258 bool "UART0 on MicroSD breakout board"
261 Repurpose the SD card slot for getting access to the UART0 serial
262 console. Primarily useful only for low level u-boot debugging on
263 tablets, where normal UART0 is difficult to access and requires
264 device disassembly and/or soldering. As the SD card can't be used
265 at the same time, the system can be only booted in the FEL mode.
266 Only enable this if you really know what you are doing.
268 config OLD_SUNXI_KERNEL_COMPAT
269 bool "Enable workarounds for booting old kernels"
272 Set this to enable various workarounds for old kernels, this results in
273 sub-optimal settings for newer kernels, only enable if needed.
276 depends on !UART0_PORT_F
277 default y if ARCH_SUNXI
280 string "Card detect pin for mmc0"
281 default "PF6" if MACH_SUN8I_A83T || MACH_SUN8I_H3 || MACH_SUN50I
284 Set the card detect pin for mmc0, leave empty to not use cd. This
285 takes a string in the format understood by sunxi_name_to_gpio, e.g.
286 PH1 for pin 1 of port H.
289 string "Card detect pin for mmc1"
292 See MMC0_CD_PIN help text.
295 string "Card detect pin for mmc2"
298 See MMC0_CD_PIN help text.
301 string "Card detect pin for mmc3"
304 See MMC0_CD_PIN help text.
307 string "Pins for mmc1"
310 Set the pins used for mmc1, when applicable. This takes a string in the
311 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
314 string "Pins for mmc2"
317 See MMC1_PINS help text.
320 string "Pins for mmc3"
323 See MMC1_PINS help text.
325 config MMC_SUNXI_SLOT_EXTRA
326 int "mmc extra slot number"
329 sunxi builds always enable mmc0, some boards also have a second sdcard
330 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
333 config INITIAL_USB_SCAN_DELAY
334 int "delay initial usb scan by x ms to allow builtin devices to init"
337 Some boards have on board usb devices which need longer than the
338 USB spec's 1 second to connect from board powerup. Set this config
339 option to a non 0 value to add an extra delay before the first usb
343 string "Vbus enable pin for usb0 (otg)"
346 Set the Vbus enable pin for usb0 (otg). This takes a string in the
347 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
350 string "Vbus detect pin for usb0 (otg)"
353 Set the Vbus detect pin for usb0 (otg). This takes a string in the
354 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
357 string "ID detect pin for usb0 (otg)"
360 Set the ID detect pin for usb0 (otg). This takes a string in the
361 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
364 string "Vbus enable pin for usb1 (ehci0)"
365 default "PH6" if MACH_SUN4I || MACH_SUN7I
366 default "PH27" if MACH_SUN6I
368 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
369 a string in the format understood by sunxi_name_to_gpio, e.g.
370 PH1 for pin 1 of port H.
373 string "Vbus enable pin for usb2 (ehci1)"
374 default "PH3" if MACH_SUN4I || MACH_SUN7I
375 default "PH24" if MACH_SUN6I
377 See USB1_VBUS_PIN help text.
380 string "Vbus enable pin for usb3 (ehci2)"
383 See USB1_VBUS_PIN help text.
386 bool "Enable I2C/TWI controller 0"
387 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
388 default n if MACH_SUN6I || MACH_SUN8I
391 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
392 its clock and setting up the bus. This is especially useful on devices
393 with slaves connected to the bus or with pins exposed through e.g. an
394 expansion port/header.
397 bool "Enable I2C/TWI controller 1"
401 See I2C0_ENABLE help text.
404 bool "Enable I2C/TWI controller 2"
408 See I2C0_ENABLE help text.
410 if MACH_SUN6I || MACH_SUN7I
412 bool "Enable I2C/TWI controller 3"
416 See I2C0_ENABLE help text.
421 bool "Enable the PRCM I2C/TWI controller"
422 # This is used for the pmic on H3
423 default y if SY8106A_POWER
426 Set this to y to enable the I2C controller which is part of the PRCM.
431 bool "Enable I2C/TWI controller 4"
435 See I2C0_ENABLE help text.
439 bool "Enable support for gpio-s on axp PMICs"
442 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
445 bool "Enable graphical uboot console on HDMI, LCD or VGA"
446 depends on !MACH_SUN8I_A83T && !MACH_SUN8I_H3 && !MACH_SUN9I && !MACH_SUN50I
449 Say Y here to add support for using a cfb console on the HDMI, LCD
450 or VGA output found on most sunxi devices. See doc/README.video for
451 info on how to select the video output and mode.
454 bool "HDMI output support"
455 depends on VIDEO && !MACH_SUN8I
458 Say Y here to add support for outputting video over HDMI.
461 bool "VGA output support"
462 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
465 Say Y here to add support for outputting video over VGA.
467 config VIDEO_VGA_VIA_LCD
468 bool "VGA via LCD controller support"
469 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
472 Say Y here to add support for external DACs connected to the parallel
473 LCD interface driving a VGA connector, such as found on the
476 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
477 bool "Force sync active high for VGA via LCD controller support"
478 depends on VIDEO_VGA_VIA_LCD
481 Say Y here if you've a board which uses opendrain drivers for the vga
482 hsync and vsync signals. Opendrain drivers cannot generate steep enough
483 positive edges for a stable video output, so on boards with opendrain
484 drivers the sync signals must always be active high.
486 config VIDEO_VGA_EXTERNAL_DAC_EN
487 string "LCD panel power enable pin"
488 depends on VIDEO_VGA_VIA_LCD
491 Set the enable pin for the external VGA DAC. This takes a string in the
492 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
494 config VIDEO_COMPOSITE
495 bool "Composite video output support"
496 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
499 Say Y here to add support for outputting composite video.
501 config VIDEO_LCD_MODE
502 string "LCD panel timing details"
506 LCD panel timing details string, leave empty if there is no LCD panel.
507 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
508 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
509 Also see: http://linux-sunxi.org/LCD
511 config VIDEO_LCD_DCLK_PHASE
512 int "LCD panel display clock phase"
516 Select LCD panel display clock phase shift, range 0-3.
518 config VIDEO_LCD_POWER
519 string "LCD panel power enable pin"
523 Set the power enable pin for the LCD panel. This takes a string in the
524 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
526 config VIDEO_LCD_RESET
527 string "LCD panel reset pin"
531 Set the reset pin for the LCD panel. This takes a string in the format
532 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
534 config VIDEO_LCD_BL_EN
535 string "LCD panel backlight enable pin"
539 Set the backlight enable pin for the LCD panel. This takes a string in the
540 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
543 config VIDEO_LCD_BL_PWM
544 string "LCD panel backlight pwm pin"
548 Set the backlight pwm pin for the LCD panel. This takes a string in the
549 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
551 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
552 bool "LCD panel backlight pwm is inverted"
556 Set this if the backlight pwm output is active low.
558 config VIDEO_LCD_PANEL_I2C
559 bool "LCD panel needs to be configured via i2c"
564 Say y here if the LCD panel needs to be configured via i2c. This
565 will add a bitbang i2c controller using gpios to talk to the LCD.
567 config VIDEO_LCD_PANEL_I2C_SDA
568 string "LCD panel i2c interface SDA pin"
569 depends on VIDEO_LCD_PANEL_I2C
572 Set the SDA pin for the LCD i2c interface. This takes a string in the
573 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
575 config VIDEO_LCD_PANEL_I2C_SCL
576 string "LCD panel i2c interface SCL pin"
577 depends on VIDEO_LCD_PANEL_I2C
580 Set the SCL pin for the LCD i2c interface. This takes a string in the
581 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
584 # Note only one of these may be selected at a time! But hidden choices are
585 # not supported by Kconfig
586 config VIDEO_LCD_IF_PARALLEL
589 config VIDEO_LCD_IF_LVDS
594 prompt "LCD panel support"
597 Select which type of LCD panel to support.
599 config VIDEO_LCD_PANEL_PARALLEL
600 bool "Generic parallel interface LCD panel"
601 select VIDEO_LCD_IF_PARALLEL
603 config VIDEO_LCD_PANEL_LVDS
604 bool "Generic lvds interface LCD panel"
605 select VIDEO_LCD_IF_LVDS
607 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
608 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
609 select VIDEO_LCD_SSD2828
610 select VIDEO_LCD_IF_PARALLEL
612 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
614 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
615 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
616 select VIDEO_LCD_ANX9804
617 select VIDEO_LCD_IF_PARALLEL
618 select VIDEO_LCD_PANEL_I2C
620 Select this for eDP LCD panels with 4 lanes running at 1.62G,
621 connected via an ANX9804 bridge chip.
623 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
624 bool "Hitachi tx18d42vm LCD panel"
625 select VIDEO_LCD_HITACHI_TX18D42VM
626 select VIDEO_LCD_IF_LVDS
628 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
630 config VIDEO_LCD_TL059WV5C0
631 bool "tl059wv5c0 LCD panel"
632 select VIDEO_LCD_PANEL_I2C
633 select VIDEO_LCD_IF_PARALLEL
635 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
636 Aigo M60/M608/M606 tablets.
642 int "GMAC Transmit Clock Delay Chain"
645 Set the GMAC Transmit Clock Delay Chain value.
647 config SPL_STACK_R_ADDR
648 default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I || MACH_SUN50I
649 default 0x2fe00000 if MACH_SUN9I