board/sunxi/gmac.c

   1 #include <common.h>
   2 #include <netdev.h>
   3 #include <miiphy.h>
   4 #include <asm/gpio.h>
   5 #include <asm/io.h>
   6 #include <asm/arch/clock.h>
   7 #include <asm/arch/gpio.h>
   8
   9 int sunxi_gmac_initialize(bd_t *bis)
  10 {
  11         int pin;
  12         struct sunxi_ccm_reg *const ccm =
  13                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  14
  15         /* Set up clock gating */
  16         setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
  17
  18         /* Set MII clock */
  19 #ifdef CONFIG_RGMII
  20         setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
  21                 CCM_GMAC_CTRL_GPIT_RGMII);
  22 #else
  23         setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII |
  24                 CCM_GMAC_CTRL_GPIT_MII);
  25 #endif
  26
  27         /* Configure pin mux settings for GMAC */
  28         for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
  29 #ifdef CONFIG_RGMII
  30                 /* skip unused pins in RGMII mode */
  31                 if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
  32                         continue;
  33 #endif
  34                 sunxi_gpio_set_cfgpin(pin, SUN7I_GPA0_GMAC);
  35                 sunxi_gpio_set_drv(pin, 3);
  36         }
  37
  38 #ifdef CONFIG_RGMII
  39         return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_RGMII);
  40 #else
  41         return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_MII);
  42 #endif
  43 }