2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
4 * Author: Felipe Balbi <balbi@ti.com>
6 * Based on board/ti/dra7xx/evm.c
8 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/omap_common.h>
18 #include <asm/arch/gpio.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/dra7xx_iodelay.h>
21 #include <asm/arch/sys_proto.h>
22 #include <asm/arch/mmc_host_def.h>
23 #include <asm/arch/sata.h>
24 #include <asm/arch/gpio.h>
25 #include <environment.h>
29 #ifdef CONFIG_DRIVER_TI_CPSW
33 DECLARE_GLOBAL_DATA_PTR;
36 #define GPIO_DDR_VTT_EN 203
38 const struct omap_sysinfo sysinfo = {
39 "Board: BeagleBoard x15\n"
42 static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
43 .dmm_lisa_map_3 = 0x80740300,
47 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
49 *dmm_lisa_regs = &beagle_x15_lisa_regs;
52 static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
53 .sdram_config_init = 0x61851b32,
54 .sdram_config = 0x61851b32,
55 .sdram_config2 = 0x00000000,
56 .ref_ctrl = 0x000040F1,
57 .ref_ctrl_final = 0x00001035,
58 .sdram_tim1 = 0xceef266b,
59 .sdram_tim2 = 0x328f7fda,
60 .sdram_tim3 = 0x027f88a8,
61 .read_idle_ctrl = 0x00050000,
62 .zq_config = 0x0007190b,
63 .temp_alert_config = 0x00000000,
64 .emif_ddr_phy_ctlr_1_init = 0x0024400b,
65 .emif_ddr_phy_ctlr_1 = 0x0e24400b,
66 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
67 .emif_ddr_ext_phy_ctrl_2 = 0x00740074,
68 .emif_ddr_ext_phy_ctrl_3 = 0x00780078,
69 .emif_ddr_ext_phy_ctrl_4 = 0x007c007c,
70 .emif_ddr_ext_phy_ctrl_5 = 0x007b007b,
71 .emif_rd_wr_lvl_rmp_win = 0x00000000,
72 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
73 .emif_rd_wr_lvl_ctl = 0x00000000,
74 .emif_rd_wr_exec_thresh = 0x00000305
77 /* Ext phy ctrl regs 1-35 */
78 static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
120 static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
121 .sdram_config_init = 0x61851b32,
122 .sdram_config = 0x61851b32,
123 .sdram_config2 = 0x00000000,
124 .ref_ctrl = 0x000040F1,
125 .ref_ctrl_final = 0x00001035,
126 .sdram_tim1 = 0xceef266b,
127 .sdram_tim2 = 0x328f7fda,
128 .sdram_tim3 = 0x027f88a8,
129 .read_idle_ctrl = 0x00050000,
130 .zq_config = 0x0007190b,
131 .temp_alert_config = 0x00000000,
132 .emif_ddr_phy_ctlr_1_init = 0x0024400b,
133 .emif_ddr_phy_ctlr_1 = 0x0e24400b,
134 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
135 .emif_ddr_ext_phy_ctrl_2 = 0x00820082,
136 .emif_ddr_ext_phy_ctrl_3 = 0x008b008b,
137 .emif_ddr_ext_phy_ctrl_4 = 0x00800080,
138 .emif_ddr_ext_phy_ctrl_5 = 0x007e007e,
139 .emif_rd_wr_lvl_rmp_win = 0x00000000,
140 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
141 .emif_rd_wr_lvl_ctl = 0x00000000,
142 .emif_rd_wr_exec_thresh = 0x00000305
145 static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
185 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
189 *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
192 *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
197 void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
201 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
202 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
205 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
206 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
211 struct vcores_data beagle_x15_volts = {
212 .mpu.value = VDD_MPU_DRA752,
213 .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM,
214 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
215 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
216 .mpu.pmic = &tps659038,
218 .eve.value = VDD_EVE_DRA752,
219 .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
220 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
221 .eve.addr = TPS659038_REG_ADDR_SMPS45,
222 .eve.pmic = &tps659038,
224 .gpu.value = VDD_GPU_DRA752,
225 .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
226 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
227 .gpu.addr = TPS659038_REG_ADDR_SMPS45,
228 .gpu.pmic = &tps659038,
230 .core.value = VDD_CORE_DRA752,
231 .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
232 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
233 .core.addr = TPS659038_REG_ADDR_SMPS6,
234 .core.pmic = &tps659038,
236 .iva.value = VDD_IVA_DRA752,
237 .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM,
238 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
239 .iva.addr = TPS659038_REG_ADDR_SMPS45,
240 .iva.pmic = &tps659038,
243 void hw_data_init(void)
245 *prcm = &dra7xx_prcm;
246 *dplls_data = &dra7xx_dplls;
247 *omap_vcores = &beagle_x15_volts;
248 *ctrl = &dra7xx_ctrl;
254 gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
259 int board_late_init(void)
263 * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
264 * This is the POWERHOLD-in-Low behavior.
266 palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
270 void set_muxconf_regs_essential(void)
272 do_set_mux32((*ctrl)->control_padconf_core_base,
273 early_padconf, ARRAY_SIZE(early_padconf));
276 #ifdef CONFIG_IODELAY_RECALIBRATION
277 void recalibrate_iodelay(void)
279 __recalibrate_iodelay(core_padconf_array_essential,
280 ARRAY_SIZE(core_padconf_array_essential),
281 iodelay_cfg_array, ARRAY_SIZE(iodelay_cfg_array));
285 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
286 int board_mmc_init(bd_t *bis)
288 omap_mmc_init(0, 0, 0, -1, -1);
289 omap_mmc_init(1, 0, 0, -1, -1);
294 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
295 int spl_start_uboot(void)
297 /* break into full u-boot on 'c' */
298 if (serial_tstc() && serial_getc() == 'c')
301 #ifdef CONFIG_SPL_ENV_SUPPORT
304 if (getenv_yesno("boot_os") != 1)
312 #ifdef CONFIG_DRIVER_TI_CPSW
314 /* Delay value to add to calibrated value */
315 #define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
316 #define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
317 #define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
318 #define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
319 #define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
320 #define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
321 #define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
322 #define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
323 #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
324 #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
326 static void cpsw_control(int enabled)
328 /* VTP can be added here */
331 static struct cpsw_slave_data cpsw_slaves[] = {
333 .slave_reg_ofs = 0x208,
334 .sliver_reg_ofs = 0xd80,
338 .slave_reg_ofs = 0x308,
339 .sliver_reg_ofs = 0xdc0,
344 static struct cpsw_platform_data cpsw_data = {
345 .mdio_base = CPSW_MDIO_BASE,
346 .cpsw_base = CPSW_BASE,
349 .cpdma_reg_ofs = 0x800,
351 .slave_data = cpsw_slaves,
352 .ale_reg_ofs = 0xd00,
354 .host_port_reg_ofs = 0x108,
355 .hw_stats_reg_ofs = 0x900,
356 .bd_ram_ofs = 0x2000,
357 .mac_control = (1 << 5),
358 .control = cpsw_control,
360 .version = CPSW_CTRL_VERSION_2,
363 int board_eth_init(bd_t *bis)
367 uint32_t mac_hi, mac_lo;
370 /* try reading mac address from efuse */
371 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
372 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
373 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
374 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
375 mac_addr[2] = mac_hi & 0xFF;
376 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
377 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
378 mac_addr[5] = mac_lo & 0xFF;
380 if (!getenv("ethaddr")) {
381 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
383 if (is_valid_ethaddr(mac_addr))
384 eth_setenv_enetaddr("ethaddr", mac_addr);
387 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
388 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
389 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
390 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
391 mac_addr[2] = mac_hi & 0xFF;
392 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
393 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
394 mac_addr[5] = mac_lo & 0xFF;
396 if (!getenv("eth1addr")) {
397 if (is_valid_ethaddr(mac_addr))
398 eth_setenv_enetaddr("eth1addr", mac_addr);
401 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
403 writel(ctrl_val, (*ctrl)->control_core_control_io1);
405 ret = cpsw_register(&cpsw_data);
407 printf("Error %d registering CPSW switch\n", ret);
413 #ifdef CONFIG_BOARD_EARLY_INIT_F
414 /* VTT regulator enable */
415 static inline void vtt_regulator_enable(void)
417 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
420 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
421 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
424 int board_early_init_f(void)
426 vtt_regulator_enable();