4 * Stefan Roese, DENX Software Engineering, sr@denx.de.
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
27 #include <asm/immap_85xx.h>
28 #include <asm/processor.h>
35 unsigned long refresh;
36 #endif /* CONFIG_TQM8548 */
39 typedef struct sdram_conf_s sdram_conf_t;
42 #ifdef CONFIG_TQM8548_AG
43 sdram_conf_t ddr_cs_conf[] = {
44 {(1024 << 20), 0x80044202, 0x0002D000}, /* 1024MB, 14x10(4) */
45 { (512 << 20), 0x80044102, 0x0001A000}, /* 512MB, 13x10(4) */
46 { (256 << 20), 0x80040102, 0x00014000}, /* 256MB, 13x10(4) */
47 { (128 << 20), 0x80040101, 0x0000C000}, /* 128MB, 13x9(4) */
49 #else /* !CONFIG_TQM8548_AG */
50 sdram_conf_t ddr_cs_conf[] = {
51 {(512 << 20), 0x80044102, 0x0001A000}, /* 512MB, 13x10(4) */
52 {(256 << 20), 0x80040102, 0x00014000}, /* 256MB, 13x10(4) */
53 {(128 << 20), 0x80040101, 0x0000C000}, /* 128MB, 13x9(4) */
55 #endif /* CONFIG_TQM8548_AG */
56 #else /* !CONFIG_TQM8548 */
57 sdram_conf_t ddr_cs_conf[] = {
58 {(512 << 20), 0x80000202}, /* 512MB, 14x10(4) */
59 {(256 << 20), 0x80000102}, /* 256MB, 13x10(4) */
60 {(128 << 20), 0x80000101}, /* 128MB, 13x9(4) */
61 {( 64 << 20), 0x80000001}, /* 64MB, 12x9(4) */
63 #endif /* CONFIG_TQM8548 */
65 #define N_DDR_CS_CONF (sizeof(ddr_cs_conf) / sizeof(ddr_cs_conf[0]))
67 int cas_latency (void);
70 * Autodetect onboard DDR SDRAM on 85xx platforms
72 * NOTE: Some of the hardcoded values are hardware dependant,
73 * so this should be extended for other future boards
76 long int sdram_setup (int casl)
79 volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
81 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
82 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
83 #else /* !CONFIG_TQM8548 */
84 unsigned long cfg_ddr_timing1;
85 unsigned long cfg_ddr_mode;
86 #endif /* CONFIG_TQM8548 */
89 * Disable memory controller.
95 /* Timing and refresh settings for DDR2-533 and below */
97 ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24;
98 ddr->cs0_config = ddr_cs_conf[0].reg;
99 ddr->timing_cfg_3 = 0x00020000;
101 /* TIMING CFG 1, 533MHz
103 * ACTTOPRE: 12 Clocks
106 * REFREC: EXT_REFREC:REFREC 53 Clocks
111 ddr->timing_cfg_1 = 0x4C47D432;
113 /* TIMING CFG 2, 533MHz
117 * RD_TO_PRE: 2 Clocks
118 * WR_DATA_DELAY: 1/2 Clock
120 * FOUR_ACT: 14 Clocks
122 ddr->timing_cfg_2 = 0x331848CE;
124 /* DDR SDRAM Mode, 533MHz
125 * MRS: Extended Mode Register
126 * OUT: Outputs enabled
131 * Posted CAS: 3 Clocks
132 * ODS: reduced strength
139 * CAS latency: 4 Clocks
143 ddr->sdram_mode = 0x439E0642;
145 /* DDR SDRAM Interval, 533MHz
146 * REFINT: 1040 Clocks
149 ddr->sdram_interval = (1040 << 16) | 0x100;
152 * Workaround for erratum DDR19 according to MPC8548 Device Errata
153 * document, Rev. 1: DDR IO receiver must be set to an acceptable
154 * bias point by modifying a hidden register.
156 if (SVR_REV (get_svr ()) < 0x21)
157 gur->ddrioovcr = 0x90000000; /* enable, VSEL 1.8V */
160 * FRC_SR: normal mode
161 * SR_IE: no self-refresh interrupt
162 * DLL_RST_DIS: don't care, leave at reset value
163 * DQS_CFG: differential DQS signals
164 * ODT_CFG: assert ODT to internal IOs only during reads to DRAM
165 * LVWx_CFG: don't care, leave at reset value
166 * NUM_PR: 1 refresh will be issued at a time
167 * DM_CFG: don't care, leave at reset value
168 * D_INIT: no data initialization
170 ddr->sdram_cfg_2 = 0x04401000;
173 * MRS: Extended Mode Register 2
175 ddr->sdram_mode_2 = 0x8000C000;
177 /* DDR SDRAM CLK CNTL
178 * CLK_ADJUST: 1/2 Clock 0x02000000
179 * CLK_ADJUST: 5/8 Clock 0x02800000
181 ddr->sdram_clk_cntl = 0x02800000;
183 /* wait for clock stabilization */
184 asm ("sync;isync;msync");
187 #if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE)
189 * Workaround for erratum DDR20 according to MPC8548 Device Errata
190 * document, Rev. 1: "CKE signal may not function correctly after
191 * assertion of HRESET"
194 /* 1. Configure DDR register as is done in normal DDR configuration.
195 * Do not set DDR_SDRAM_CFG[MEM_EN].
197 * 2. Set reserved bit EEBACR[3] at offset 0x1000
199 ecm->eebacr |= 0x10000000;
202 * 3. Before DDR_SDRAM_CFG[MEM_EN] is set, write DDR_SDRAM_CFG_2[D_INIT]
205 * FRC_SR: normal mode
206 * SR_IE: no self-refresh interrupt
207 * DLL_RST_DIS: don't care, leave at reset value
208 * DQS_CFG: differential DQS signals
209 * ODT_CFG: assert ODT to internal IOs only during reads to DRAM
210 * LVWx_CFG: don't care, leave at reset value
211 * NUM_PR: 1 refresh will be issued at a time
212 * DM_CFG: don't care, leave at reset value
213 * D_INIT: enable data initialization
215 ddr->sdram_cfg_2 |= 0x00000010;
218 * 4. Before DDR_SDRAM_CFG[MEM_EN] set, write D3[21] to disable data
221 ddr->debug_3 |= 0x00000400;
224 * 5. Wait 200 micro-seconds
229 * 6. Set DDR_SDRAM_CFG[MEM_EN]
231 * BTW, initialize DDR_SDRAM_CFG:
233 * SREN: don't care, leave at reset value
234 * ECC_EN: no error report
235 * RD_EN: no registered DIMMs
237 * DYN_PWR: no power management
238 * 32_BE: don't care, leave at reset value
240 * NCAP: don't care, leave at reset value
242 * BA_INTLV_CTL: no interleaving
243 * x32_EN: x16 organization
244 * PCHB8: MA[10] for auto-precharge
245 * HSE: half strength for single and 2-layer stacks
246 * (full strength for 3- and 4-layer stacks not
249 * BI: automatic initialization
251 ddr->sdram_cfg = 0x83000008;
254 * 7. Poll DDR_SDRAM_CFG_2[D_INIT] until it is cleared by hardware
256 asm ("sync;isync;msync");
257 while (ddr->sdram_cfg_2 & 0x00000010)
261 * 8. Clear D3[21] to re-enable data training
263 ddr->debug_3 &= ~0x00000400;
266 * 9. Set D2(21) to force data training to run
268 ddr->debug_2 |= 0x00000400;
271 * 10. Poll on D2[21] until it is cleared by hardware
273 asm ("sync;isync;msync");
274 while (ddr->debug_2 & 0x00000400)
278 * 11. Clear reserved bit EEBACR[3] at offset 0x1000
280 ecm->eebacr &= ~0x10000000;
282 #else /* !(CONFIG_TQM8548_AG || CONFIG_TQM8548_BE) */
284 /* DDR SDRAM CLK CNTL
286 * SREN: don't care, leave at reset value
287 * ECC_EN: no error report
288 * RD_EN: no register DIMMs
290 * DYN_PWR: no power management
291 * 32_BE: don't care, leave at reset value
293 * NCAP: don't care, leave at reset value
295 * BA_INTLV_CTL: no interleaving
296 * x32_EN: x16 organization
297 * PCHB8: MA[10] for auto-precharge
298 * HSE: half strength for single and 2-layer stacks
299 * (full strength for 3- and 4-layer stacks no yet considered)
301 * BI: automatic initialization
303 ddr->sdram_cfg = 0x83000008;
305 #endif /* CONFIG_TQM8548_AG || CONFIG_TQM8548_BE */
307 asm ("sync; isync; msync");
309 #else /* !CONFIG_TQM8548 */
312 cfg_ddr_timing1 = 0x47405331 | (3 << 16);
313 cfg_ddr_mode = 0x40020002 | (2 << 4);
317 cfg_ddr_timing1 = 0x47405331 | (4 << 16);
318 cfg_ddr_mode = 0x40020002 | (6 << 4);
323 cfg_ddr_timing1 = 0x47405331 | (5 << 16);
324 cfg_ddr_mode = 0x40020002 | (3 << 4);
328 ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24;
329 ddr->cs0_config = ddr_cs_conf[0].reg;
330 ddr->timing_cfg_1 = cfg_ddr_timing1;
331 ddr->timing_cfg_2 = 0x00000800; /* P9-45,may need tuning */
332 ddr->sdram_mode = cfg_ddr_mode;
333 ddr->sdram_interval = 0x05160100; /* autocharge,no open page */
334 ddr->err_disable = 0x0000000D;
336 asm ("sync; isync; msync");
339 ddr->sdram_cfg = 0xc2000000; /* unbuffered,no DYN_PWR */
340 asm ("sync; isync; msync");
342 #endif /* CONFIG_TQM8548 */
344 for (i = 0; i < N_DDR_CS_CONF; i++) {
345 ddr->cs0_config = ddr_cs_conf[i].reg;
347 if (get_ram_size (0, ddr_cs_conf[i].size) ==
348 ddr_cs_conf[i].size) {
350 * size detected -> set Chip Select Bounds Register
352 ddr->cs0_bnds = (ddr_cs_conf[i].size - 1) >> 24;
358 #ifdef CONFIG_TQM8548
359 if (i < N_DDR_CS_CONF) {
360 /* Adjust refresh rate for DDR2 */
362 ddr->timing_cfg_3 = ddr_cs_conf[i].refresh & 0x00070000;
364 ddr->timing_cfg_1 = (ddr->timing_cfg_1 & 0xFFFF0FFF) |
365 (ddr_cs_conf[i].refresh & 0x0000F000);
367 return ddr_cs_conf[i].size;
369 #endif /* CONFIG_TQM8548 */
371 /* return size if detected, else return 0 */
372 return (i < N_DDR_CS_CONF) ? ddr_cs_conf[i].size : 0;
375 void board_add_ram_info (int use_default)
380 casl = CONFIG_DDR_DEFAULT_CL;
382 casl = cas_latency ();
400 phys_size_t initdram (int board_type)
405 #if defined(CONFIG_DDR_DLL)
407 * This DLL-Override only used on TQM8540 and TQM8560
410 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
416 * Work around to stabilize DDR DLL
418 gur->ddrdllcr = 0x81000000;
419 asm ("sync; isync; msync");
421 while (gur->ddrdllcr != 0x81000100) {
422 gur->devdisr = gur->devdisr | 0x00010000;
423 asm ("sync; isync; msync");
424 for (i = 0; i < x; i++)
426 gur->devdisr = gur->devdisr & 0xfff7ffff;
427 asm ("sync; isync; msync");
433 casl = cas_latency ();
434 dram_size = sdram_setup (casl);
435 if ((dram_size == 0) && (casl != CONFIG_DDR_DEFAULT_CL)) {
437 * Try again with default CAS latency
439 puts ("Problem with CAS lantency");
440 board_add_ram_info (1);
441 puts (", using default CL!\n");
442 casl = CONFIG_DDR_DEFAULT_CL;
443 dram_size = sdram_setup (casl);
450 #if defined(CONFIG_SYS_DRAM_TEST)
453 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
454 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
457 printf ("SDRAM test phase 1:\n");
458 for (p = pstart; p < pend; p++)
461 for (p = pstart; p < pend; p++) {
462 if (*p != 0xaaaaaaaa) {
463 printf ("SDRAM test fails at: %08x\n", (uint) p);
468 printf ("SDRAM test phase 2:\n");
469 for (p = pstart; p < pend; p++)
472 for (p = pstart; p < pend; p++) {
473 if (*p != 0x55555555) {
474 printf ("SDRAM test fails at: %08x\n", (uint) p);
479 printf ("SDRAM test passed.\n");