2 * (C) Copyright 2003-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
8 * (C) Copyright 2004-2006
9 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/processor.h>
35 #ifdef CONFIG_VIDEO_SM501
39 #if defined(CONFIG_MPC5200_DDR)
40 #include "mt46v16m16-75.h"
42 #include "mt48lc16m16a2-75.h"
46 void ps2mult_early_init(void);
50 static void sdram_start (int hi_addr)
52 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
54 /* unlock mode register */
55 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
57 __asm__ volatile ("sync");
59 /* precharge all banks */
60 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
62 __asm__ volatile ("sync");
65 /* set mode register: extended mode */
66 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
67 __asm__ volatile ("sync");
69 /* set mode register: reset DLL */
70 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
71 __asm__ volatile ("sync");
74 /* precharge all banks */
75 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
77 __asm__ volatile ("sync");
80 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
82 __asm__ volatile ("sync");
84 /* set mode register */
85 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
86 __asm__ volatile ("sync");
88 /* normal operation */
89 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
90 __asm__ volatile ("sync");
95 * ATTENTION: Although partially referenced initdram does NOT make real use
96 * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
97 * is something else than 0x00000000.
100 #if defined(CONFIG_MPC5200)
101 long int initdram (int board_type)
110 /* setup SDRAM chip selects */
111 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
112 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
113 __asm__ volatile ("sync");
115 /* setup config registers */
116 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
117 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
118 __asm__ volatile ("sync");
122 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
123 __asm__ volatile ("sync");
126 /* find RAM size using SDRAM CS0 only */
128 test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
130 test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
138 /* memory smaller than 1MB is impossible */
139 if (dramsize < (1 << 20)) {
143 /* set SDRAM CS0 size according to the amount of RAM found */
145 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
146 __builtin_ffs(dramsize >> 20) - 1;
148 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
151 /* let SDRAM CS1 start right after CS0 */
152 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */
154 /* find RAM size using SDRAM CS1 only */
156 test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
158 test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
166 /* memory smaller than 1MB is impossible */
167 if (dramsize2 < (1 << 20)) {
171 /* set SDRAM CS1 size according to the amount of RAM found */
173 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
174 | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
176 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
179 #else /* CFG_RAMBOOT */
181 /* retrieve size of memory connected to SDRAM CS0 */
182 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
183 if (dramsize >= 0x13) {
184 dramsize = (1 << (dramsize - 0x13)) << 20;
189 /* retrieve size of memory connected to SDRAM CS1 */
190 dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
191 if (dramsize2 >= 0x13) {
192 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
196 #endif /* CFG_RAMBOOT */
199 * On MPC5200B we need to set the special configuration delay in the
200 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
201 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
203 * "The SDelay should be written to a value of 0x00000004. It is
204 * required to account for changes caused by normal wafer processing
209 if ((SVR_MJREV(svr) >= 2) &&
210 (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
212 *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
213 __asm__ volatile ("sync");
216 #if defined(CONFIG_TQM5200_B)
217 return dramsize + dramsize2;
220 #endif /* CONFIG_TQM5200_B */
223 #elif defined(CONFIG_MGT5100)
225 long int initdram (int board_type)
231 /* setup and enable SDRAM chip selects */
232 *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
233 *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
234 *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
235 __asm__ volatile ("sync");
237 /* setup config registers */
238 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
239 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
241 /* address select register */
242 *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
243 __asm__ volatile ("sync");
247 test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
249 test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
257 /* set SDRAM end address according to size */
258 *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
260 #else /* CFG_RAMBOOT */
262 /* Retrieve amount of SDRAM available */
263 dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
265 #endif /* CFG_RAMBOOT */
271 #error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
274 int checkboard (void)
276 #if defined (CONFIG_AEVFIFO)
277 puts ("Board: AEVFIFO\n");
280 #if defined (CONFIG_TQM5200)
281 #if defined(CONFIG_TQM5200_B)
282 puts ("Board: TQM5200 or TQM5200S (TQ-Components GmbH)\n");
284 puts ("Board: TQM5200 (TQ-Components GmbH)\n");
285 #endif /* CONFIG_TQM5200_B */
287 #if defined (CONFIG_STK52XX)
288 puts (" on a STK52XX baseboard\n");
290 #if defined (CONFIG_TB5200)
291 puts (" on a TB5200 baseboard\n");
297 void flash_preinit(void)
300 * Now, when we are in RAM, enable flash write
301 * access for detection process.
302 * Note that CS_BOOT cannot be cleared when
303 * executing in flash.
305 #if defined(CONFIG_MGT5100)
306 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
307 *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
309 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
314 static struct pci_controller hose;
316 extern void pci_mpc5xxx_init(struct pci_controller *);
318 void pci_init_board(void)
320 pci_mpc5xxx_init(&hose);
324 #if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
326 #if defined (CONFIG_MINIFAP)
327 #define SM501_POWER_MODE0_GATE 0x00000040UL
328 #define SM501_POWER_MODE1_GATE 0x00000048UL
329 #define POWER_MODE_GATE_GPIO_PWM_I2C 0x00000040UL
330 #define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL
331 #define SM501_GPIO_DATA_HIGH 0x00010004UL
332 #define SM501_GPIO_51 0x00080000UL
334 #define GPIO_PSC1_4 0x01000000UL
337 void init_ide_reset (void)
339 debug ("init_ide_reset\n");
341 #if defined (CONFIG_MINIFAP)
342 /* Configure GPIO_51 of the SM501 grafic controller as ATA reset */
344 /* enable GPIO control (in both power modes) */
345 *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |=
346 POWER_MODE_GATE_GPIO_PWM_I2C;
347 *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |=
348 POWER_MODE_GATE_GPIO_PWM_I2C;
349 /* configure GPIO51 as output */
350 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |=
353 /* Configure PSC1_4 as GPIO output for ATA reset */
354 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
355 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
359 void ide_set_reset (int idereset)
361 debug ("ide_reset(%d)\n", idereset);
363 #if defined (CONFIG_MINIFAP)
365 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
368 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
373 *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
375 *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
379 #endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
383 * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
384 * is left open, no keypress is detected.
386 int post_hotkeys_pressed(void)
388 struct mpc5xxx_gpio *gpio;
390 gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO;
393 * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in
394 * CODEC or UART mode. Consumer IrDA should still be possible.
396 gpio->port_config &= ~(0x07000000);
397 gpio->port_config |= 0x03000000;
399 /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
400 gpio->simple_gpioe |= 0x20000000;
402 /* Configure GPIO_IRDA_1 as input */
403 gpio->simple_ddr &= ~(0x20000000);
405 return ((gpio->simple_ival & 0x20000000) ? 0 : 1);
409 #if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
411 void post_word_store (ulong a)
413 volatile ulong *save_addr =
414 (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
419 ulong post_word_load (void)
421 volatile ulong *save_addr =
422 (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
426 #endif /* CONFIG_POST || CONFIG_LOGBUFFER*/
428 #ifdef CONFIG_PS2MULT
429 #ifdef CONFIG_BOARD_EARLY_INIT_R
430 int board_early_init_r (void)
432 ps2mult_early_init();
436 #endif /* CONFIG_PS2MULT */
438 #if defined(CONFIG_CS_AUTOCONF)
439 int last_stage_init (void)
442 * auto scan for really existing devices and re-set chip select
449 * Check for SRAM and SRAM size
452 /* save original SRAM content */
453 save = *(volatile u16 *)CFG_CS2_START;
456 /* write test pattern to SRAM */
457 *(volatile u16 *)CFG_CS2_START = 0xA5A5;
458 __asm__ volatile ("sync");
460 * Put a different pattern on the data lines: otherwise they may float
461 * long enough to read back what we wrote.
463 tmp = *(volatile u16 *)CFG_FLASH_BASE;
465 puts ("!! possible error in SRAM detection\n");
467 if (*(volatile u16 *)CFG_CS2_START != 0xA5A5) {
468 /* no SRAM at all, disable cs */
469 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18);
470 *(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF;
471 *(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF;
473 __asm__ volatile ("sync");
474 } else if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0xA5A5) {
475 /* make sure that we access a mirrored address */
476 *(volatile u16 *)CFG_CS2_START = 0x1111;
477 __asm__ volatile ("sync");
478 if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0x1111) {
479 /* SRAM size = 512 kByte */
480 *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CFG_CS2_START,
482 __asm__ volatile ("sync");
483 puts ("SRAM: 512 kB\n");
486 puts ("!! possible error in SRAM detection\n");
488 puts ("SRAM: 1 MB\n");
490 /* restore origianl SRAM content */
492 *(volatile u16 *)CFG_CS2_START = save;
493 __asm__ volatile ("sync");
497 * Check for Grafic Controller
500 /* save origianl FB content */
501 save = *(volatile u16 *)CFG_CS1_START;
504 /* write test pattern to FB memory */
505 *(volatile u16 *)CFG_CS1_START = 0xA5A5;
506 __asm__ volatile ("sync");
508 * Put a different pattern on the data lines: otherwise they may float
509 * long enough to read back what we wrote.
511 tmp = *(volatile u16 *)CFG_FLASH_BASE;
513 puts ("!! possible error in grafic controller detection\n");
515 if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) {
516 /* no grafic controller at all, disable cs */
517 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17);
518 *(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF;
519 *(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF;
521 __asm__ volatile ("sync");
523 puts ("VGA: SMI501 (Voyager) with 8 MB\n");
525 /* restore origianl FB content */
527 *(volatile u16 *)CFG_CS1_START = save;
528 __asm__ volatile ("sync");
533 #endif /* CONFIG_CS_AUTOCONF */
535 #ifdef CONFIG_VIDEO_SM501
537 #define DISPLAY_WIDTH 640
538 #define DISPLAY_HEIGHT 480
540 #ifdef CONFIG_VIDEO_SM501_8BPP
541 #error CONFIG_VIDEO_SM501_8BPP not supported.
542 #endif /* CONFIG_VIDEO_SM501_8BPP */
544 #ifdef CONFIG_VIDEO_SM501_16BPP
545 #error CONFIG_VIDEO_SM501_16BPP not supported.
546 #endif /* CONFIG_VIDEO_SM501_16BPP */
547 #ifdef CONFIG_VIDEO_SM501_32BPP
548 static const SMI_REGS init_regs [] =
552 {0x00048, 0x00021807},
553 {0x0004C, 0x10090a01},
555 {0x00040, 0x00021807},
556 {0x00044, 0x10090a01},
558 {0x80200, 0x00010000},
560 {0x80208, 0x0A000A00},
561 {0x8020C, 0x02fa027f},
562 {0x80210, 0x004a028b},
563 {0x80214, 0x020c01df},
564 {0x80218, 0x000201e9},
565 {0x80200, 0x00013306},
566 #else /* panel + CRT */
568 {0x00048, 0x00021807},
569 {0x0004C, 0x091a0a01},
571 {0x00040, 0x00021807},
572 {0x00044, 0x091a0a01},
574 {0x80000, 0x0f013106},
575 {0x80004, 0xc428bb17},
576 {0x8000C, 0x00000000},
577 {0x80010, 0x0a000a00},
578 {0x80014, 0x02800000},
579 {0x80018, 0x01e00000},
580 {0x8001C, 0x00000000},
581 {0x80020, 0x01e00280},
582 {0x80024, 0x02fa027f},
583 {0x80028, 0x004a028b},
584 {0x8002C, 0x020c01df},
585 {0x80030, 0x000201e9},
586 {0x80200, 0x00010000},
590 #endif /* CONFIG_VIDEO_SM501_32BPP */
592 #ifdef CONFIG_CONSOLE_EXTRA_INFO
594 * Return text to be printed besides the logo.
596 void video_get_info_str (int line_number, char *info)
598 if (line_number == 1) {
599 strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
600 #if defined (CONFIG_STK52XX) || defined (CONFIG_TB5200)
601 } else if (line_number == 2) {
602 #if defined (CONFIG_STK52XX)
603 strcpy (info, " on a STK52XX baseboard");
605 #if defined (CONFIG_TB5200)
606 strcpy (info, " on a TB5200 baseboard");
617 * Returns SM501 register base address. First thing called in the
618 * driver. Checks if SM501 is physically present.
620 unsigned int board_video_init (void)
626 * Check for Grafic Controller
629 /* save origianl FB content */
630 save = *(volatile u16 *)CFG_CS1_START;
633 /* write test pattern to FB memory */
634 *(volatile u16 *)CFG_CS1_START = 0xA5A5;
635 __asm__ volatile ("sync");
637 * Put a different pattern on the data lines: otherwise they may float
638 * long enough to read back what we wrote.
640 tmp = *(volatile u16 *)CFG_FLASH_BASE;
642 puts ("!! possible error in grafic controller detection\n");
644 if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) {
645 /* no grafic controller found */
649 ret = SM501_MMIO_BASE;
653 *(volatile u16 *)CFG_CS1_START = save;
654 __asm__ volatile ("sync");
660 * Returns SM501 framebuffer address
662 unsigned int board_video_get_fb (void)
664 return SM501_FB_BASE;
668 * Called after initializing the SM501 and before clearing the screen.
670 void board_validate_screen (unsigned int base)
675 * Return a pointer to the initialization sequence.
677 const SMI_REGS *board_get_regs (void)
682 int board_get_width (void)
684 return DISPLAY_WIDTH;
687 int board_get_height (void)
689 return DISPLAY_HEIGHT;
692 #endif /* CONFIG_VIDEO_SM501 */