2 * (C) Copyright 2007 Michal Simek
4 * Michal SIMEK <monstr@monstr.eu>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * CAUTION: This file is automatically generated by libgen.
26 * Version: Xilinx EDK 6.3 EDK_Gmm.12.3
29 /* System Clock Frequency */
30 #define XILINX_CLOCK_FREQ 100000000
32 /* Microblaze is microblaze_0 */
33 #define XILINX_FSL_NUMBER 2
35 /* Interrupt controller is intc_0 */
36 #define XILINX_INTC_BASEADDR 0x41200000
37 #define XILINX_INTC_NUM_INTR_INPUTS 4
39 /* Timer pheriphery is opb_timer_0 */
40 #define XILINX_TIMER_BASEADDR 0x41c00000
41 #define XILINX_TIMER_IRQ 0
43 /* Uart pheriphery is console_uart */
44 #define XILINX_UART_BASEADDR 0x40600000
45 #define XILINX_UART_BAUDRATE 115200
47 /* GPIO is opb_gpio_0*/
48 #define XILINX_GPIO_BASEADDR 0x90000000
50 /* Flash Memory is opb_emc_0 */
51 #define XILINX_FLASH_START 0x2c000000
52 #define XILINX_FLASH_SIZE 0x00800000
54 /* Main Memory is plb_ddr_0 */
55 #define XILINX_RAM_START 0x28000000
56 #define XILINX_RAM_SIZE 0x04000000
58 /* Sysace Controller is opb_sysace_0 */
59 #define XILINX_SYSACE_BASEADDR 0x41800000
60 #define XILINX_SYSACE_HIGHADDR 0x4180FFFF
61 #define XILINX_SYSACE_MEM_WIDTH 16
63 /* Ethernet controller is opb_ethernet_0 */
64 #define XPAR_XEMAC_NUM_INSTANCES 1
65 #define XPAR_OPB_ETHERNET_0_DEVICE_ID 0
66 #define XPAR_OPB_ETHERNET_0_BASEADDR 0x40c00000
67 #define XPAR_OPB_ETHERNET_0_HIGHADDR 0x40c0fFFF
68 #define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1
69 #define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1
70 #define XPAR_OPB_ETHERNET_0_MII_EXIST 1