3 * Subodh Nijsure, SkyStream Networks, snijsure@skystream.com
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #if defined(CONFIG_8xx)
28 #elif defined (CONFIG_405GP) || defined(CONFIG_405EP)
29 #include <asm/processor.h>
30 #elif defined (CONFIG_5xx)
33 #if (CONFIG_COMMANDS & CFG_CMD_REGINFO)
35 int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
37 #if defined(CONFIG_8xx)
38 volatile immap_t *immap = (immap_t *)CFG_IMMR;
39 volatile memctl8xx_t *memctl = &immap->im_memctl;
40 volatile sysconf8xx_t *sysconf = &immap->im_siu_conf;
41 volatile sit8xx_t *timers = &immap->im_sit;
43 /* Hopefully more PowerPC knowledgable people will add code to display
44 * other useful registers
47 printf ("\nSystem Configuration registers\n"
49 "\tIMMR\t0x%08X\n", get_immr(0));
51 printf("\tSIUMCR\t0x%08X", sysconf->sc_siumcr);
52 printf("\tSYPCR\t0x%08X\n",sysconf->sc_sypcr);
54 printf("\tSWT\t0x%08X", sysconf->sc_swt);
55 printf("\tSWSR\t0x%04X\n", sysconf->sc_swsr);
57 printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X\n",
58 sysconf->sc_sipend, sysconf->sc_simask);
59 printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X\n",
60 sysconf->sc_siel, sysconf->sc_sivec);
61 printf("\tTESR\t0x%08X\tSDCR\t0x%08X\n",
62 sysconf->sc_tesr, sysconf->sc_sdcr);
64 printf ("Memory Controller Registers\n"
66 "\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
67 printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
68 printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
69 printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
70 printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", memctl->memc_br4, memctl->memc_or4);
71 printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", memctl->memc_br5, memctl->memc_or5);
72 printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", memctl->memc_br6, memctl->memc_or6);
73 printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", memctl->memc_br7, memctl->memc_or7);
75 "\tmamr\t0x%08X\tmbmr\t0x%08X \n",
76 memctl->memc_mamr, memctl->memc_mbmr );
77 printf("\tmstat\t0x%08X\tmptpr\t0x%08X \n",
78 memctl->memc_mstat, memctl->memc_mptpr );
79 printf("\tmdr\t0x%08X \n", memctl->memc_mdr);
81 printf ("\nSystem Integration Timers\n"
82 "\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n",
83 timers->sit_tbscr, timers->sit_rtcsc);
84 printf("\tPISCR\t0x%08X \n", timers->sit_piscr);
87 * May be some CPM info here?
90 /* DBU[dave@cray.com] For the CRAY-L1, but should be generically 405gp */
91 #elif defined (CONFIG_405GP)
92 printf ("\n405GP registers; MSR=%08x\n",mfmsr());
93 printf ("\nUniversal Interrupt Controller Regs\n"
94 "uicsr uicsrs uicer uiccr uicpr uictr uicmsr uicvr uicvcr"
96 "%08x %08x %08x %08x %08x %08x %08x %08x %08x\n",
107 puts ("\nMemory (SDRAM) Configuration\n"
108 "besra besrsa besrb besrsb bear mcopt1 rtr pmit\n");
110 mtdcr(memcfga,mem_besra); printf ("%08x ", mfdcr(memcfgd));
111 mtdcr(memcfga,mem_besrsa); printf ("%08x ", mfdcr(memcfgd));
112 mtdcr(memcfga,mem_besrb); printf ("%08x ", mfdcr(memcfgd));
113 mtdcr(memcfga,mem_besrsb); printf ("%08x ", mfdcr(memcfgd));
114 mtdcr(memcfga,mem_bear); printf ("%08x ", mfdcr(memcfgd));
115 mtdcr(memcfga,mem_mcopt1); printf ("%08x ", mfdcr(memcfgd));
116 mtdcr(memcfga,mem_rtr); printf ("%08x ", mfdcr(memcfgd));
117 mtdcr(memcfga,mem_pmit); printf ("%08x ", mfdcr(memcfgd));
120 "mb0cf mb1cf mb2cf mb3cf sdtr1 ecccf eccerr\n");
121 mtdcr(memcfga,mem_mb0cf); printf ("%08x ", mfdcr(memcfgd));
122 mtdcr(memcfga,mem_mb1cf); printf ("%08x ", mfdcr(memcfgd));
123 mtdcr(memcfga,mem_mb2cf); printf ("%08x ", mfdcr(memcfgd));
124 mtdcr(memcfga,mem_mb3cf); printf ("%08x ", mfdcr(memcfgd));
125 mtdcr(memcfga,mem_sdtr1); printf ("%08x ", mfdcr(memcfgd));
126 mtdcr(memcfga,mem_ecccf); printf ("%08x ", mfdcr(memcfgd));
127 mtdcr(memcfga,mem_eccerr); printf ("%08x ", mfdcr(memcfgd));
131 "dmasr dmasgc dmaadr\n"
133 "dmacr_0 dmact_0 dmada_0 dmasa_0 dmasb_0\n"
134 "%08x %08x %08x %08x %08x\n"
135 "dmacr_1 dmact_1 dmada_1 dmasa_1 dmasb_1\n"
136 "%08x %08x %08x %08x %08x\n",
137 mfdcr(dmasr), mfdcr(dmasgc),mfdcr(dmaadr),
138 mfdcr(dmacr0), mfdcr(dmact0),mfdcr(dmada0), mfdcr(dmasa0), mfdcr(dmasb0),
139 mfdcr(dmacr1), mfdcr(dmact1),mfdcr(dmada1), mfdcr(dmasa1), mfdcr(dmasb1));
142 "dmacr_2 dmact_2 dmada_2 dmasa_2 dmasb_2\n" "%08x %08x %08x %08x %08x\n"
143 "dmacr_3 dmact_3 dmada_3 dmasa_3 dmasb_3\n" "%08x %08x %08x %08x %08x\n",
144 mfdcr(dmacr2), mfdcr(dmact2),mfdcr(dmada2), mfdcr(dmasa2), mfdcr(dmasb2),
145 mfdcr(dmacr3), mfdcr(dmact3),mfdcr(dmada3), mfdcr(dmasa3), mfdcr(dmasb3) );
149 "pbear pbesr0 pbesr1 epcr\n");
150 mtdcr(ebccfga,pbear); printf ("%08x ", mfdcr(ebccfgd));
151 mtdcr(ebccfga,pbesr0); printf ("%08x ", mfdcr(ebccfgd));
152 mtdcr(ebccfga,pbesr1); printf ("%08x ", mfdcr(ebccfgd));
153 mtdcr(ebccfga,epcr); printf ("%08x ", mfdcr(ebccfgd));
156 "pb0cr pb0ap pb1cr pb1ap pb2cr pb2ap pb3cr pb3ap\n");
157 mtdcr(ebccfga,pb0cr); printf ("%08x ", mfdcr(ebccfgd));
158 mtdcr(ebccfga,pb0ap); printf ("%08x ", mfdcr(ebccfgd));
159 mtdcr(ebccfga,pb1cr); printf ("%08x ", mfdcr(ebccfgd));
160 mtdcr(ebccfga,pb1ap); printf ("%08x ", mfdcr(ebccfgd));
161 mtdcr(ebccfga,pb2cr); printf ("%08x ", mfdcr(ebccfgd));
162 mtdcr(ebccfga,pb2ap); printf ("%08x ", mfdcr(ebccfgd));
163 mtdcr(ebccfga,pb3cr); printf ("%08x ", mfdcr(ebccfgd));
164 mtdcr(ebccfga,pb3ap); printf ("%08x ", mfdcr(ebccfgd));
167 "pb4cr pb4ap pb5cr bp5ap pb6cr pb6ap pb7cr pb7ap\n");
168 mtdcr(ebccfga,pb4cr); printf ("%08x ", mfdcr(ebccfgd));
169 mtdcr(ebccfga,pb4ap); printf ("%08x ", mfdcr(ebccfgd));
170 mtdcr(ebccfga,pb5cr); printf ("%08x ", mfdcr(ebccfgd));
171 mtdcr(ebccfga,pb5ap); printf ("%08x ", mfdcr(ebccfgd));
172 mtdcr(ebccfga,pb6cr); printf ("%08x ", mfdcr(ebccfgd));
173 mtdcr(ebccfga,pb6ap); printf ("%08x ", mfdcr(ebccfgd));
174 mtdcr(ebccfga,pb7cr); printf ("%08x ", mfdcr(ebccfgd));
175 mtdcr(ebccfga,pb7ap); printf ("%08x ", mfdcr(ebccfgd));
178 /* For the BUBINGA (IBM 405EP eval) but should be generically 405ep */
179 #elif defined(CONFIG_405EP)
180 printf ("\n405EP registers; MSR=%08x\n",mfmsr());
181 printf ("\nUniversal Interrupt Controller Regs\n"
182 "uicsr uicer uiccr uicpr uictr uicmsr uicvr uicvcr"
184 "%08x %08x %08x %08x %08x %08x %08x %08x\n",
194 puts ("\nMemory (SDRAM) Configuration\n"
195 "mcopt1 rtr pmit mb0cf mb1cf sdtr1\n");
197 mtdcr(memcfga,mem_mcopt1); printf ("%08x ", mfdcr(memcfgd));
198 mtdcr(memcfga,mem_rtr); printf ("%08x ", mfdcr(memcfgd));
199 mtdcr(memcfga,mem_pmit); printf ("%08x ", mfdcr(memcfgd));
200 mtdcr(memcfga,mem_mb0cf); printf ("%08x ", mfdcr(memcfgd));
201 mtdcr(memcfga,mem_mb1cf); printf ("%08x ", mfdcr(memcfgd));
202 mtdcr(memcfga,mem_sdtr1); printf ("%08x ", mfdcr(memcfgd));
206 "dmasr dmasgc dmaadr\n" "%08x %08x %08x\n"
207 "dmacr_0 dmact_0 dmada_0 dmasa_0 dmasb_0\n" "%08x %08x %08x %08x %08x\n"
208 "dmacr_1 dmact_1 dmada_1 dmasa_1 dmasb_1\n" "%08x %08x %08x %08x %08x\n",
209 mfdcr(dmasr), mfdcr(dmasgc),mfdcr(dmaadr),
210 mfdcr(dmacr0), mfdcr(dmact0),mfdcr(dmada0), mfdcr(dmasa0), mfdcr(dmasb0),
211 mfdcr(dmacr1), mfdcr(dmact1),mfdcr(dmada1), mfdcr(dmasa1), mfdcr(dmasb1));
214 "dmacr_2 dmact_2 dmada_2 dmasa_2 dmasb_2\n" "%08x %08x %08x %08x %08x\n"
215 "dmacr_3 dmact_3 dmada_3 dmasa_3 dmasb_3\n" "%08x %08x %08x %08x %08x\n",
216 mfdcr(dmacr2), mfdcr(dmact2),mfdcr(dmada2), mfdcr(dmasa2), mfdcr(dmasb2),
217 mfdcr(dmacr3), mfdcr(dmact3),mfdcr(dmada3), mfdcr(dmasa3), mfdcr(dmasb3) );
221 "pbear pbesr0 pbesr1 epcr\n");
222 mtdcr(ebccfga,pbear); printf ("%08x ", mfdcr(ebccfgd));
223 mtdcr(ebccfga,pbesr0); printf ("%08x ", mfdcr(ebccfgd));
224 mtdcr(ebccfga,pbesr1); printf ("%08x ", mfdcr(ebccfgd));
225 mtdcr(ebccfga,epcr); printf ("%08x ", mfdcr(ebccfgd));
228 "pb0cr pb0ap pb1cr pb1ap pb2cr pb2ap pb3cr pb3ap\n");
229 mtdcr(ebccfga,pb0cr); printf ("%08x ", mfdcr(ebccfgd));
230 mtdcr(ebccfga,pb0ap); printf ("%08x ", mfdcr(ebccfgd));
231 mtdcr(ebccfga,pb1cr); printf ("%08x ", mfdcr(ebccfgd));
232 mtdcr(ebccfga,pb1ap); printf ("%08x ", mfdcr(ebccfgd));
233 mtdcr(ebccfga,pb2cr); printf ("%08x ", mfdcr(ebccfgd));
234 mtdcr(ebccfga,pb2ap); printf ("%08x ", mfdcr(ebccfgd));
235 mtdcr(ebccfga,pb3cr); printf ("%08x ", mfdcr(ebccfgd));
236 mtdcr(ebccfga,pb3ap); printf ("%08x ", mfdcr(ebccfgd));
240 mtdcr(ebccfga,pb4cr); printf ("%08x ", mfdcr(ebccfgd));
241 mtdcr(ebccfga,pb4ap); printf ("%08x ", mfdcr(ebccfgd));
244 #elif defined(CONFIG_5xx)
246 volatile immap_t *immap = (immap_t *)CFG_IMMR;
247 volatile memctl5xx_t *memctl = &immap->im_memctl;
248 volatile sysconf5xx_t *sysconf = &immap->im_siu_conf;
249 volatile sit5xx_t *timers = &immap->im_sit;
250 volatile car5xx_t *car = &immap->im_clkrst;
251 volatile uimb5xx_t *uimb = &immap->im_uimb;
253 puts ("\nSystem Configuration registers\n");
254 printf("\tIMMR\t0x%08X\tSIUMCR\t0x%08X \n", get_immr(0), sysconf->sc_siumcr);
255 printf("\tSYPCR\t0x%08X\tSWSR\t0x%04X \n" ,sysconf->sc_sypcr, sysconf->sc_swsr);
256 printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X \n", sysconf->sc_sipend, sysconf->sc_simask);
257 printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X \n", sysconf->sc_siel, sysconf->sc_sivec);
258 printf("\tTESR\t0x%08X\n", sysconf->sc_tesr);
260 puts ("\nMemory Controller Registers\n");
261 printf("\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
262 printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
263 printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
264 printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
265 printf("\tDMBR\t0x%08X\tDMOR\t0x%08X \n", memctl->memc_dmbr, memctl->memc_dmor );
266 printf("\tMSTAT\t0x%08X\n", memctl->memc_mstat);
268 puts ("\nSystem Integration Timers\n");
269 printf("\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n", timers->sit_tbscr, timers->sit_rtcsc);
270 printf("\tPISCR\t0x%08X \n", timers->sit_piscr);
272 puts ("\nClocks and Reset\n");
273 printf("\tSCCR\t0x%08X\tPLPRCR\t0x%08X \n", car->car_sccr, car->car_plprcr);
275 puts ("\nU-Bus to IMB3 Bus Interface\n");
276 printf("\tUMCR\t0x%08X\tUIPEND\t0x%08X \n", uimb->uimb_umcr, uimb->uimb_uipend);
278 #endif /* CONFIG_5xx */
282 #endif /* CONFIG_COMMANDS & CFG_CMD_REGINFO */
285 /**************************************************/
287 #if (defined(CONFIG_8xx) || defined(CONFIG_405GP) || defined(CONFIG_405EP)) && \
288 (CONFIG_COMMANDS & CFG_CMD_REGINFO)
291 reginfo, 2, 1, do_reginfo,
292 "reginfo - print register information\n",