3 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * Configuration support for Xilinx Spartan3 devices. Based
27 * on spartan2.c (Rich Ireland, rireland@enterasys.com).
30 #include <common.h> /* core U-Boot definitions */
31 #include <spartan3.h> /* Spartan-II device family */
33 /* Define FPGA_DEBUG to get debug printf's */
35 #define PRINTF(fmt,args...) printf (fmt ,##args)
37 #define PRINTF(fmt,args...)
40 #undef CONFIG_SYS_FPGA_CHECK_BUSY
41 #undef CONFIG_SYS_FPGA_PROG_FEEDBACK
43 /* Note: The assumption is that we cannot possibly run fast enough to
44 * overrun the device (the Slave Parallel mode can free run at 50MHz).
45 * If there is a need to operate slower, define CONFIG_FPGA_DELAY in
46 * the board config file to slow things down.
48 #ifndef CONFIG_FPGA_DELAY
49 #define CONFIG_FPGA_DELAY()
52 #ifndef CONFIG_SYS_FPGA_WAIT
53 #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
56 static int Spartan3_sp_load( Xilinx_desc *desc, void *buf, size_t bsize );
57 static int Spartan3_sp_dump( Xilinx_desc *desc, void *buf, size_t bsize );
58 /* static int Spartan3_sp_info( Xilinx_desc *desc ); */
59 static int Spartan3_sp_reloc( Xilinx_desc *desc, ulong reloc_offset );
61 static int Spartan3_ss_load( Xilinx_desc *desc, void *buf, size_t bsize );
62 static int Spartan3_ss_dump( Xilinx_desc *desc, void *buf, size_t bsize );
63 /* static int Spartan3_ss_info( Xilinx_desc *desc ); */
64 static int Spartan3_ss_reloc( Xilinx_desc *desc, ulong reloc_offset );
66 /* ------------------------------------------------------------------------- */
67 /* Spartan-II Generic Implementation */
68 int Spartan3_load (Xilinx_desc * desc, void *buf, size_t bsize)
70 int ret_val = FPGA_FAIL;
72 switch (desc->iface) {
74 PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__);
75 ret_val = Spartan3_ss_load (desc, buf, bsize);
79 PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__);
80 ret_val = Spartan3_sp_load (desc, buf, bsize);
84 printf ("%s: Unsupported interface type, %d\n",
85 __FUNCTION__, desc->iface);
91 int Spartan3_dump (Xilinx_desc * desc, void *buf, size_t bsize)
93 int ret_val = FPGA_FAIL;
95 switch (desc->iface) {
97 PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__);
98 ret_val = Spartan3_ss_dump (desc, buf, bsize);
102 PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__);
103 ret_val = Spartan3_sp_dump (desc, buf, bsize);
107 printf ("%s: Unsupported interface type, %d\n",
108 __FUNCTION__, desc->iface);
114 int Spartan3_info( Xilinx_desc *desc )
120 int Spartan3_reloc (Xilinx_desc * desc, ulong reloc_offset)
122 int ret_val = FPGA_FAIL; /* assume a failure */
124 if (desc->family != Xilinx_Spartan3) {
125 printf ("%s: Unsupported family type, %d\n",
126 __FUNCTION__, desc->family);
129 switch (desc->iface) {
131 ret_val = Spartan3_ss_reloc (desc, reloc_offset);
135 ret_val = Spartan3_sp_reloc (desc, reloc_offset);
139 printf ("%s: Unsupported interface type, %d\n",
140 __FUNCTION__, desc->iface);
147 /* ------------------------------------------------------------------------- */
148 /* Spartan-II Slave Parallel Generic Implementation */
150 static int Spartan3_sp_load (Xilinx_desc * desc, void *buf, size_t bsize)
152 int ret_val = FPGA_FAIL; /* assume the worst */
153 Xilinx_Spartan3_Slave_Parallel_fns *fn = desc->iface_fns;
155 PRINTF ("%s: start with interface functions @ 0x%p\n",
159 size_t bytecount = 0;
160 unsigned char *data = (unsigned char *) buf;
161 int cookie = desc->cookie; /* make a local copy */
162 unsigned long ts; /* timestamp */
164 PRINTF ("%s: Function Table:\n"
175 "write data:\t0x%p\n"
179 __FUNCTION__, &fn, fn, fn->pre, fn->pgm, fn->init, fn->err,
180 fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata, fn->busy,
181 fn->abort, fn->post);
184 * This code is designed to emulate the "Express Style"
185 * Continuous Data Loading in Slave Parallel Mode for
186 * the Spartan-II Family.
188 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
189 printf ("Loading FPGA Device %d...\n", cookie);
192 * Run the pre configuration function if there is one.
198 /* Establish the initial state */
199 (*fn->pgm) (TRUE, TRUE, cookie); /* Assert the program, commit */
201 /* Get ready for the burn */
202 CONFIG_FPGA_DELAY ();
203 (*fn->pgm) (FALSE, TRUE, cookie); /* Deassert the program, commit */
205 ts = get_timer (0); /* get current time */
206 /* Now wait for INIT and BUSY to go high */
208 CONFIG_FPGA_DELAY ();
209 if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
210 puts ("** Timeout waiting for INIT to clear.\n");
211 (*fn->abort) (cookie); /* abort the burn */
214 } while ((*fn->init) (cookie) && (*fn->busy) (cookie));
216 (*fn->wr) (TRUE, TRUE, cookie); /* Assert write, commit */
217 (*fn->cs) (TRUE, TRUE, cookie); /* Assert chip select, commit */
218 (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
221 while (bytecount < bsize) {
222 /* XXX - do we check for an Ctrl-C press in here ??? */
223 /* XXX - Check the error bit? */
225 (*fn->wdata) (data[bytecount++], TRUE, cookie); /* write the data */
226 CONFIG_FPGA_DELAY ();
227 (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
228 CONFIG_FPGA_DELAY ();
229 (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
231 #ifdef CONFIG_SYS_FPGA_CHECK_BUSY
232 ts = get_timer (0); /* get current time */
233 while ((*fn->busy) (cookie)) {
234 /* XXX - we should have a check in here somewhere to
235 * make sure we aren't busy forever... */
237 CONFIG_FPGA_DELAY ();
238 (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
239 CONFIG_FPGA_DELAY ();
240 (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
242 if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
243 puts ("** Timeout waiting for BUSY to clear.\n");
244 (*fn->abort) (cookie); /* abort the burn */
250 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
251 if (bytecount % (bsize / 40) == 0)
252 putc ('.'); /* let them know we are alive */
256 CONFIG_FPGA_DELAY ();
257 (*fn->cs) (FALSE, TRUE, cookie); /* Deassert the chip select */
258 (*fn->wr) (FALSE, TRUE, cookie); /* Deassert the write pin */
260 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
261 putc ('\n'); /* terminate the dotted line */
264 /* now check for done signal */
265 ts = get_timer (0); /* get current time */
266 ret_val = FPGA_SUCCESS;
267 while ((*fn->done) (cookie) == FPGA_FAIL) {
268 /* XXX - we should have a check in here somewhere to
269 * make sure we aren't busy forever... */
271 CONFIG_FPGA_DELAY ();
272 (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
273 CONFIG_FPGA_DELAY ();
274 (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
276 if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
277 puts ("** Timeout waiting for DONE to clear.\n");
278 (*fn->abort) (cookie); /* abort the burn */
284 if (ret_val == FPGA_SUCCESS) {
285 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
290 * Run the post configuration function if there is one.
293 (*fn->post) (cookie);
297 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
303 printf ("%s: NULL Interface function table!\n", __FUNCTION__);
309 static int Spartan3_sp_dump (Xilinx_desc * desc, void *buf, size_t bsize)
311 int ret_val = FPGA_FAIL; /* assume the worst */
312 Xilinx_Spartan3_Slave_Parallel_fns *fn = desc->iface_fns;
315 unsigned char *data = (unsigned char *) buf;
316 size_t bytecount = 0;
317 int cookie = desc->cookie; /* make a local copy */
319 printf ("Starting Dump of FPGA Device %d...\n", cookie);
321 (*fn->cs) (TRUE, TRUE, cookie); /* Assert chip select, commit */
322 (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
325 while (bytecount < bsize) {
326 /* XXX - do we check for an Ctrl-C press in here ??? */
328 (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
329 (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
330 (*fn->rdata) (&(data[bytecount++]), cookie); /* read the data */
331 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
332 if (bytecount % (bsize / 40) == 0)
333 putc ('.'); /* let them know we are alive */
337 (*fn->cs) (FALSE, FALSE, cookie); /* Deassert the chip select */
338 (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
339 (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
341 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
342 putc ('\n'); /* terminate the dotted line */
346 /* XXX - checksum the data? */
348 printf ("%s: NULL Interface function table!\n", __FUNCTION__);
355 static int Spartan3_sp_reloc (Xilinx_desc * desc, ulong reloc_offset)
357 int ret_val = FPGA_FAIL; /* assume the worst */
358 Xilinx_Spartan3_Slave_Parallel_fns *fn_r, *fn =
359 (Xilinx_Spartan3_Slave_Parallel_fns *) (desc->iface_fns);
364 /* Get the relocated table address */
365 addr = (ulong) fn + reloc_offset;
366 fn_r = (Xilinx_Spartan3_Slave_Parallel_fns *) addr;
368 if (!fn_r->relocated) {
370 if (memcmp (fn_r, fn,
371 sizeof (Xilinx_Spartan3_Slave_Parallel_fns))
373 /* good copy of the table, fix the descriptor pointer */
374 desc->iface_fns = fn_r;
376 PRINTF ("%s: Invalid function table at 0x%p\n",
381 PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__,
384 addr = (ulong) (fn->pre) + reloc_offset;
385 fn_r->pre = (Xilinx_pre_fn) addr;
387 addr = (ulong) (fn->pgm) + reloc_offset;
388 fn_r->pgm = (Xilinx_pgm_fn) addr;
390 addr = (ulong) (fn->init) + reloc_offset;
391 fn_r->init = (Xilinx_init_fn) addr;
393 addr = (ulong) (fn->done) + reloc_offset;
394 fn_r->done = (Xilinx_done_fn) addr;
396 addr = (ulong) (fn->clk) + reloc_offset;
397 fn_r->clk = (Xilinx_clk_fn) addr;
399 addr = (ulong) (fn->err) + reloc_offset;
400 fn_r->err = (Xilinx_err_fn) addr;
402 addr = (ulong) (fn->cs) + reloc_offset;
403 fn_r->cs = (Xilinx_cs_fn) addr;
405 addr = (ulong) (fn->wr) + reloc_offset;
406 fn_r->wr = (Xilinx_wr_fn) addr;
408 addr = (ulong) (fn->rdata) + reloc_offset;
409 fn_r->rdata = (Xilinx_rdata_fn) addr;
411 addr = (ulong) (fn->wdata) + reloc_offset;
412 fn_r->wdata = (Xilinx_wdata_fn) addr;
414 addr = (ulong) (fn->busy) + reloc_offset;
415 fn_r->busy = (Xilinx_busy_fn) addr;
417 addr = (ulong) (fn->abort) + reloc_offset;
418 fn_r->abort = (Xilinx_abort_fn) addr;
420 addr = (ulong) (fn->post) + reloc_offset;
421 fn_r->post = (Xilinx_post_fn) addr;
423 fn_r->relocated = TRUE;
426 /* this table has already been moved */
427 /* XXX - should check to see if the descriptor is correct */
428 desc->iface_fns = fn_r;
431 ret_val = FPGA_SUCCESS;
433 printf ("%s: NULL Interface function table!\n", __FUNCTION__);
440 /* ------------------------------------------------------------------------- */
442 static int Spartan3_ss_load (Xilinx_desc * desc, void *buf, size_t bsize)
444 int ret_val = FPGA_FAIL; /* assume the worst */
445 Xilinx_Spartan3_Slave_Serial_fns *fn = desc->iface_fns;
449 PRINTF ("%s: start with interface functions @ 0x%p\n",
453 size_t bytecount = 0;
454 unsigned char *data = (unsigned char *) buf;
455 int cookie = desc->cookie; /* make a local copy */
456 unsigned long ts; /* timestamp */
458 PRINTF ("%s: Function Table:\n"
466 __FUNCTION__, &fn, fn, fn->pgm, fn->init,
467 fn->clk, fn->wr, fn->done);
468 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
469 printf ("Loading FPGA Device %d...\n", cookie);
473 * Run the pre configuration function if there is one.
479 /* Establish the initial state */
480 (*fn->pgm) (TRUE, TRUE, cookie); /* Assert the program, commit */
482 /* Wait for INIT state (init low) */
483 ts = get_timer (0); /* get current time */
485 CONFIG_FPGA_DELAY ();
486 if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
487 puts ("** Timeout waiting for INIT to start.\n");
490 } while (!(*fn->init) (cookie));
492 /* Get ready for the burn */
493 CONFIG_FPGA_DELAY ();
494 (*fn->pgm) (FALSE, TRUE, cookie); /* Deassert the program, commit */
496 ts = get_timer (0); /* get current time */
497 /* Now wait for INIT to go high */
499 CONFIG_FPGA_DELAY ();
500 if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
501 puts ("** Timeout waiting for INIT to clear.\n");
504 } while ((*fn->init) (cookie));
507 while (bytecount < bsize) {
509 /* Xilinx detects an error if INIT goes low (active)
510 while DONE is low (inactive) */
511 if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) {
512 puts ("** CRC error during FPGA load.\n");
515 val = data [bytecount ++];
518 /* Deassert the clock */
519 (*fn->clk) (FALSE, TRUE, cookie);
520 CONFIG_FPGA_DELAY ();
522 (*fn->wr) ((val & 0x80), TRUE, cookie);
523 CONFIG_FPGA_DELAY ();
524 /* Assert the clock */
525 (*fn->clk) (TRUE, TRUE, cookie);
526 CONFIG_FPGA_DELAY ();
531 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
532 if (bytecount % (bsize / 40) == 0)
533 putc ('.'); /* let them know we are alive */
537 CONFIG_FPGA_DELAY ();
539 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
540 putc ('\n'); /* terminate the dotted line */
543 /* now check for done signal */
544 ts = get_timer (0); /* get current time */
545 ret_val = FPGA_SUCCESS;
546 (*fn->wr) (TRUE, TRUE, cookie);
548 while (! (*fn->done) (cookie)) {
549 /* XXX - we should have a check in here somewhere to
550 * make sure we aren't busy forever... */
552 CONFIG_FPGA_DELAY ();
553 (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
554 CONFIG_FPGA_DELAY ();
555 (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
559 if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
560 puts ("** Timeout waiting for DONE to clear.\n");
565 putc ('\n'); /* terminate the dotted line */
568 * Run the post configuration function if there is one.
571 (*fn->post) (cookie);
574 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
575 if (ret_val == FPGA_SUCCESS) {
584 printf ("%s: NULL Interface function table!\n", __FUNCTION__);
590 static int Spartan3_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize)
592 /* Readback is only available through the Slave Parallel and */
593 /* boundary-scan interfaces. */
594 printf ("%s: Slave Serial Dumping is unavailable\n",
599 static int Spartan3_ss_reloc (Xilinx_desc * desc, ulong reloc_offset)
601 int ret_val = FPGA_FAIL; /* assume the worst */
602 Xilinx_Spartan3_Slave_Serial_fns *fn_r, *fn =
603 (Xilinx_Spartan3_Slave_Serial_fns *) (desc->iface_fns);
608 /* Get the relocated table address */
609 addr = (ulong) fn + reloc_offset;
610 fn_r = (Xilinx_Spartan3_Slave_Serial_fns *) addr;
612 if (!fn_r->relocated) {
614 if (memcmp (fn_r, fn,
615 sizeof (Xilinx_Spartan3_Slave_Serial_fns))
617 /* good copy of the table, fix the descriptor pointer */
618 desc->iface_fns = fn_r;
620 PRINTF ("%s: Invalid function table at 0x%p\n",
625 PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__,
629 addr = (ulong) (fn->pre) + reloc_offset;
630 fn_r->pre = (Xilinx_pre_fn) addr;
633 addr = (ulong) (fn->pgm) + reloc_offset;
634 fn_r->pgm = (Xilinx_pgm_fn) addr;
636 addr = (ulong) (fn->init) + reloc_offset;
637 fn_r->init = (Xilinx_init_fn) addr;
639 addr = (ulong) (fn->done) + reloc_offset;
640 fn_r->done = (Xilinx_done_fn) addr;
642 addr = (ulong) (fn->clk) + reloc_offset;
643 fn_r->clk = (Xilinx_clk_fn) addr;
645 addr = (ulong) (fn->wr) + reloc_offset;
646 fn_r->wr = (Xilinx_wr_fn) addr;
649 addr = (ulong) (fn->post) + reloc_offset;
650 fn_r->post = (Xilinx_post_fn) addr;
653 fn_r->relocated = TRUE;
656 /* this table has already been moved */
657 /* XXX - should check to see if the descriptor is correct */
658 desc->iface_fns = fn_r;
661 ret_val = FPGA_SUCCESS;
663 printf ("%s: NULL Interface function table!\n", __FUNCTION__);