4 * Richard Woodruff <r-woodruff2@ti.com>
\r
7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
8 * Marius Groeger <mgroeger@sysgo.de>
11 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
12 * Alex Zuepke <azu@sysgo.de>
15 * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
17 * See file CREDITS for list of people who contributed to this
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License as
22 * published by the Free Software Foundation; either version 2 of
23 * the License, or (at your option) any later version.
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
37 #include <asm/arch/bits.h>
38 #include <asm/arch/omap2420.h>
39 #include <asm/proc-armv/ptrace.h>
41 extern void reset_cpu(ulong addr);
42 #define TIMER_LOAD_VAL 0
44 /* macro to read the 32 bit timer */
45 #define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+TCRR))
48 /* enable IRQ interrupts */
49 void enable_interrupts (void)
52 __asm__ __volatile__("mrs %0, cpsr\n"
61 * disable IRQ/FIQ interrupts
62 * returns true if interrupts had been enabled before we disabled them
64 int disable_interrupts (void)
66 unsigned long old,temp;
67 __asm__ __volatile__("mrs %0, cpsr\n"
70 : "=r" (old), "=r" (temp)
73 return(old & 0x80) == 0;
76 void enable_interrupts (void)
80 int disable_interrupts (void)
89 panic ("Resetting CPU ...\n");
93 void show_regs (struct pt_regs *regs)
96 const char *processor_modes[] = {
97 "USER_26", "FIQ_26", "IRQ_26", "SVC_26",
98 "UK4_26", "UK5_26", "UK6_26", "UK7_26",
99 "UK8_26", "UK9_26", "UK10_26", "UK11_26",
100 "UK12_26", "UK13_26", "UK14_26", "UK15_26",
101 "USER_32", "FIQ_32", "IRQ_32", "SVC_32",
102 "UK4_32", "UK5_32", "UK6_32", "ABT_32",
103 "UK8_32", "UK9_32", "UK10_32", "UND_32",
104 "UK12_32", "UK13_32", "UK14_32", "SYS_32",
107 flags = condition_codes (regs);
109 printf ("pc : [<%08lx>] lr : [<%08lx>]\n"
110 "sp : %08lx ip : %08lx fp : %08lx\n",
111 instruction_pointer (regs),
112 regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
113 printf ("r10: %08lx r9 : %08lx r8 : %08lx\n",
114 regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
115 printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n",
116 regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
117 printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n",
118 regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
119 printf ("Flags: %c%c%c%c",
120 flags & CC_N_BIT ? 'N' : 'n',
121 flags & CC_Z_BIT ? 'Z' : 'z',
122 flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
123 printf (" IRQs %s FIQs %s Mode %s%s\n",
124 interrupts_enabled (regs) ? "on" : "off",
125 fast_interrupts_enabled (regs) ? "on" : "off",
126 processor_modes[processor_mode (regs)],
127 thumb_mode (regs) ? " (T)" : "");
130 void do_undefined_instruction (struct pt_regs *pt_regs)
132 printf ("undefined instruction\n");
137 void do_software_interrupt (struct pt_regs *pt_regs)
139 printf ("software interrupt\n");
144 void do_prefetch_abort (struct pt_regs *pt_regs)
146 printf ("prefetch abort\n");
151 void do_data_abort (struct pt_regs *pt_regs)
153 printf ("data abort\n");
158 void do_not_used (struct pt_regs *pt_regs)
160 printf ("not used\n");
165 void do_fiq (struct pt_regs *pt_regs)
167 printf ("fast interrupt request\n");
172 void do_irq (struct pt_regs *pt_regs)
174 printf ("interrupt request\n");
179 static ulong timestamp;
180 static ulong lastinc;
182 /* nothing really to do with interrupts, just starts up a counter. */
183 int interrupt_init (void)
187 /* Start the counter ticking up */
188 *((int32_t *) (CFG_TIMERBASE + TLDR)) = TIMER_LOAD_VAL; /* reload value on overflow*/
189 val = (CFG_PVT << 2) | BIT5 | BIT1 | BIT0; /* mask to enable timer*/
190 *((int32_t *) (CFG_TIMERBASE + TCLR)) = val; /* start timer */
192 reset_timer_masked(); /* init the timestamp and lastinc value */
198 * timer without interrupts
200 void reset_timer (void)
202 reset_timer_masked ();
205 ulong get_timer (ulong base)
207 return get_timer_masked () - base;
210 void set_timer (ulong t)
215 /* delay x useconds AND perserve advance timstamp value */
216 void udelay (unsigned long usec)
220 if (usec >= 1000) { /* if "big" number, spread normalization to seconds */
221 tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
222 tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */
223 tmo /= 1000; /* finish normalize. */
224 } else { /* else small number, don't kill it prior to HZ multiply */
229 tmp = get_timer (0); /* get current timestamp */
230 if ( (tmo + tmp + 1) < tmp )/* if setting this forward will roll time stamp */
231 reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastinc value */
233 tmo += tmp; /* else, set advancing stamp wake up time */
234 while (get_timer_masked () < tmo)/* loop till event */
238 void reset_timer_masked (void)
241 lastinc = READ_TIMER; /* capture current incrementer value time */
242 timestamp = 0; /* start "advancing" time stamp from 0 */
245 ulong get_timer_masked (void)
247 ulong now = READ_TIMER; /* current tick value */
249 if (now >= lastinc) /* normal mode (non roll) */
250 timestamp += (now - lastinc); /* move stamp fordward with absoulte diff ticks */
251 else /* we have rollover of incrementer */
252 timestamp += (0xFFFFFFFF - lastinc) + now;
257 /* waits specified delay value and resets timestamp */
258 void udelay_masked (unsigned long usec)
262 if (usec >= 1000) { /* if "big" number, spread normalization to seconds */
263 tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
264 tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */
265 tmo /= 1000; /* finish normalize. */
266 } else { /* else small number, don't kill it prior to HZ multiply */
270 reset_timer_masked (); /* set "advancing" timestamp to 0, set lastinc vaule */
271 while (get_timer_masked () < tmo) /* wait for time stamp to overtake tick number.*/
276 * This function is derived from PowerPC code (read timebase as long long).
277 * On ARM it just returns the timer value.
279 unsigned long long get_ticks(void)
285 * This function is derived from PowerPC code (timebase clock frequency).
286 * On ARM it returns the number of timer ticks per second.
288 ulong get_tbclk (void)