3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
8 * Alex Zuepke <azu@sysgo.de>
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/proc-armv/ptrace.h>
32 #include <asm/hardware.h>
34 extern void reset_cpu(ulong addr);
37 /* we always count down the max. */
38 #define TIMER_LOAD_VAL 0xffff
39 /* macro to read the 16 bit timer */
40 #define READ_TIMER (IO_TC1D & 0xffff)
42 #define IRQEN (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_INTR_ENABLE))
43 #define TM2CTRL (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_CONTROL))
44 #define TM2STAT (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_STATUS))
45 #define TIMER_LOAD_VAL NETARM_GEN_TSTAT_CTC_MASK
46 #define READ_TIMER (TM2STAT & NETARM_GEN_TSTAT_CTC_MASK)
49 #ifdef CONFIG_S3C4510B
50 /* require interrupts for the S3C4510B */
51 # ifndef CONFIG_USE_IRQ
52 # error CONFIG_USE_IRQ _must_ be defined when using CONFIG_S3C4510B
54 static struct _irq_handler IRQ_HANDLER[N_IRQS];
56 #endif /* CONFIG_S3C4510B */
59 /* enable IRQ/FIQ interrupts */
60 void enable_interrupts (void)
63 __asm__ __volatile__("mrs %0, cpsr\n"
73 * disable IRQ/FIQ interrupts
74 * returns true if interrupts had been enabled before we disabled them
76 int disable_interrupts (void)
78 unsigned long old,temp;
79 __asm__ __volatile__("mrs %0, cpsr\n"
82 : "=r" (old), "=r" (temp)
85 return (old & 0x80) == 0;
87 #else /* CONFIG_USE_IRQ */
88 void enable_interrupts (void)
92 int disable_interrupts (void)
100 panic ("Resetting CPU ...\n");
104 void show_regs (struct pt_regs *regs)
107 const char *processor_modes[] =
108 { "USER_26", "FIQ_26", "IRQ_26", "SVC_26", "UK4_26", "UK5_26",
110 "UK8_26", "UK9_26", "UK10_26", "UK11_26", "UK12_26", "UK13_26",
111 "UK14_26", "UK15_26",
112 "USER_32", "FIQ_32", "IRQ_32", "SVC_32", "UK4_32", "UK5_32",
114 "UK8_32", "UK9_32", "UK10_32", "UND_32", "UK12_32", "UK13_32",
118 flags = condition_codes (regs);
120 printf ("pc : [<%08lx>] lr : [<%08lx>]\n"
121 "sp : %08lx ip : %08lx fp : %08lx\n",
122 instruction_pointer (regs),
123 regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
124 printf ("r10: %08lx r9 : %08lx r8 : %08lx\n",
125 regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
126 printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n",
127 regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
128 printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n",
129 regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
130 printf ("Flags: %c%c%c%c",
131 flags & CC_N_BIT ? 'N' : 'n',
132 flags & CC_Z_BIT ? 'Z' : 'z',
133 flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
134 printf (" IRQs %s FIQs %s Mode %s%s\n",
135 interrupts_enabled (regs) ? "on" : "off",
136 fast_interrupts_enabled (regs) ? "on" : "off",
137 processor_modes[processor_mode (regs)],
138 thumb_mode (regs) ? " (T)" : "");
141 void do_undefined_instruction (struct pt_regs *pt_regs)
143 printf ("undefined instruction\n");
148 void do_software_interrupt (struct pt_regs *pt_regs)
150 printf ("software interrupt\n");
155 void do_prefetch_abort (struct pt_regs *pt_regs)
157 printf ("prefetch abort\n");
162 void do_data_abort (struct pt_regs *pt_regs)
164 printf ("data abort\n");
169 void do_not_used (struct pt_regs *pt_regs)
171 printf ("not used\n");
176 void do_fiq (struct pt_regs *pt_regs)
178 printf ("fast interrupt request\n");
183 void do_irq (struct pt_regs *pt_regs)
185 #if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM)
186 printf ("interrupt request\n");
189 #elif defined(CONFIG_S3C4510B)
190 unsigned int pending;
192 while ( (pending = GET_REG( REG_INTOFFSET)) != 0x54) { /* sentinal value for no pending interrutps */
193 IRQ_HANDLER[pending>>2].m_func( IRQ_HANDLER[pending>>2].m_data);
195 /* clear pending interrupt */
196 PUT_REG( REG_INTPEND, (1<<(pending>>2)));
199 #error do_irq() not defined for this CPU type
204 #ifdef CONFIG_S3C4510B
205 static void default_isr( void *data) {
206 printf ("default_isr(): called for IRQ %d\n", (int)data);
209 static void timer_isr( void *data) {
210 unsigned int *pTime = (unsigned int *)data;
213 if ( !(*pTime % (CFG_HZ/4))) {
215 PUT_REG( REG_IOPDATA, GET_REG(REG_IOPDATA) ^ 0x1);
221 static ulong timestamp;
222 static ulong lastdec;
224 int interrupt_init (void)
227 #if defined(CONFIG_NETARM)
228 /* disable all interrupts */
231 /* operate timer 2 in non-prescale mode */
232 TM2CTRL = ( NETARM_GEN_TIMER_SET_HZ(CFG_HZ) |
233 NETARM_GEN_TCTL_ENABLE |
234 NETARM_GEN_TCTL_INIT_COUNT(TIMER_LOAD_VAL));
236 /* set timer 2 counter */
237 lastdec = TIMER_LOAD_VAL;
238 #elif defined(CONFIG_IMPA7) || defined(CONFIG_EP7312)
239 /* disable all interrupts */
242 /* operate timer 1 in prescale mode */
243 IO_SYSCON1 |= SYSCON1_TC1M;
245 /* select 2kHz clock source for timer 1 */
246 IO_SYSCON1 &= ~SYSCON1_TC1S;
248 /* set timer 1 counter */
249 lastdec = IO_TC1D = TIMER_LOAD_VAL;
250 #elif defined(CONFIG_S3C4510B)
253 /* install default interrupt handlers */
254 for ( i = 0; i < N_IRQS; i++) {
255 IRQ_HANDLER[i].m_data = (void *)i;
256 IRQ_HANDLER[i].m_func = default_isr;
259 /* configure interrupts for IRQ mode */
260 PUT_REG( REG_INTMODE, 0x0);
261 /* clear any pending interrupts */
262 PUT_REG( REG_INTPEND, 0x1FFFFF);
266 /* install interrupt handler for timer */
267 IRQ_HANDLER[INT_TIMER0].m_data = (void *)×tamp;
268 IRQ_HANDLER[INT_TIMER0].m_func = timer_isr;
270 /* configure free running timer 0 */
271 PUT_REG( REG_TMOD, 0x0);
273 CLR_REG( REG_TMOD, TM0_RUN);
275 /* Configure for interval mode */
276 CLR_REG( REG_TMOD, TM1_TOGGLE);
279 * Load Timer data register with count down value.
280 * count_down_val = CFG_SYS_CLK_FREQ/CFG_HZ
282 PUT_REG( REG_TDATA0, (CFG_SYS_CLK_FREQ / CFG_HZ));
285 * Enable global interrupt
286 * Enable timer0 interrupt
288 CLR_REG( REG_INTMASK, ((1<<INT_GLOBAL) | (1<<INT_TIMER0)));
291 SET_REG( REG_TMOD, TM0_RUN);
294 #error No interrupt_init() defined for this CPU type
302 * timer without interrupts
306 #if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM)
308 void reset_timer (void)
310 reset_timer_masked ();
313 ulong get_timer (ulong base)
315 return get_timer_masked () - base;
318 void set_timer (ulong t)
323 void udelay (unsigned long usec)
331 tmo += get_timer (0);
333 while (get_timer_masked () < tmo)
337 void reset_timer_masked (void)
340 lastdec = READ_TIMER;
344 ulong get_timer_masked (void)
346 ulong now = READ_TIMER;
348 if (lastdec >= now) {
350 timestamp += lastdec - now;
352 /* we have an overflow ... */
353 timestamp += lastdec + TIMER_LOAD_VAL - now;
360 void udelay_masked (unsigned long usec)
368 reset_timer_masked ();
370 while (get_timer_masked () < tmo)
374 #elif defined(CONFIG_S3C4510B)
376 ulong get_timer (ulong base)
378 return timestamp - base;
381 void udelay (unsigned long usec)
385 ticks = (usec * CFG_HZ) / 1000000;
387 ticks += get_timer (0);
389 while (get_timer (0) < ticks)
395 #error Timer routines not defined for this CPU type