2 * Memory Setup stuff - taken from blob memsetup.S
4 * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
5 * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
7 * Modified for the at91rm9200dk board by
9 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
35 * some parameters for the board
37 * This is based on rm9200dk.cfg for the BDI2000 from ABATRON which in
38 * turn is based on the boot.bin code from ATMEL
43 #define MC_PUIA 0xFFFFFF10
44 #define MC_PUP 0xFFFFFF50
45 #define MC_PUER 0xFFFFFF54
46 #define MC_ASR 0xFFFFFF04
47 #define MC_AASR 0xFFFFFF08
48 #define EBI_CFGR 0xFFFFFF64
49 #define SMC_CSR0 0xFFFFFF70
52 #define PLLAR 0xFFFFFC28
53 #define PLLBR 0xFFFFFC2C
54 #define MCKR 0xFFFFFC30
56 #define AT91C_BASE_CKGR 0xFFFFFC20
60 #define PIOC_ASR 0xFFFFF870
61 #define PIOC_BSR 0xFFFFF874
62 #define PIOC_PDR 0xFFFFF804
63 #define EBI_CSA 0xFFFFFF60
64 #define SDRC_CR 0xFFFFFF98
65 #define SDRC_MR 0xFFFFFF90
66 #define SDRC_TR 0xFFFFFF94
72 .word TEXT_BASE-PHYS_FLASH_1
79 /* Get the CKGR Base Address */
80 ldr r1, =AT91C_BASE_CKGR
81 /* Main oscillator Enable register */
82 #ifdef CONFIG_SYS_USE_MAIN_OSCILLATOR
83 ldr r0, =0x0000FF01 /* Enable main oscillator, OSCOUNT = 0xFF */
85 ldr r0, =0x0000FF00 /* Disable main oscillator, OSCOUNT = 0xFF */
87 str r0, [r1, #CKGR_MOR]
88 /* Add loop to compensate Main Oscillator startup time */
94 /* memory control configuration */
95 /* this isn't very elegant, but what the heck */
108 /* delay - this is all done by guess */
126 /* switch from FastBus to Asynchronous clock mode */
127 mrc p15, 0, r0, c1, c0, 0
128 orr r0, r0, #0xC0000000 @ set bit 31 (iA) and 30 (nF)
129 mcr p15, 0, r0, c1, c0, 0
131 /* everything is fine now */
157 /* SMRDATA is 80 bytes long */
158 /* here there's a delay of 100 */
204 /* SMRDATA1 is 176 bytes long */
205 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */