3 * Texas Instruments, <www.ti.com>
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
10 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
11 * Alex Zuepke <azu@sysgo.de>
14 * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
16 * See file CREDITS for list of people who contributed to this
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License as
21 * published by the Free Software Foundation; either version 2 of
22 * the License, or (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
37 #include <configs/omap1510.h>
39 #include <asm/proc-armv/ptrace.h>
41 extern void reset_cpu(ulong addr);
42 #define TIMER_LOAD_VAL 0xffffffff
44 /* macro to read the 32 bit timer */
45 #define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+8))
48 /* enable IRQ interrupts */
49 void enable_interrupts (void)
52 __asm__ __volatile__("mrs %0, cpsr\n"
62 * disable IRQ/FIQ interrupts
63 * returns true if interrupts had been enabled before we disabled them
65 int disable_interrupts (void)
67 unsigned long old,temp;
68 __asm__ __volatile__("mrs %0, cpsr\n"
71 : "=r" (old), "=r" (temp)
74 return (old & 0x80) == 0;
77 void enable_interrupts (void)
81 int disable_interrupts (void)
90 panic ("Resetting CPU ...\n");
94 void show_regs (struct pt_regs *regs)
97 const char *processor_modes[] = {
98 "USER_26", "FIQ_26", "IRQ_26", "SVC_26",
99 "UK4_26", "UK5_26", "UK6_26", "UK7_26",
100 "UK8_26", "UK9_26", "UK10_26", "UK11_26",
101 "UK12_26", "UK13_26", "UK14_26", "UK15_26",
102 "USER_32", "FIQ_32", "IRQ_32", "SVC_32",
103 "UK4_32", "UK5_32", "UK6_32", "ABT_32",
104 "UK8_32", "UK9_32", "UK10_32", "UND_32",
105 "UK12_32", "UK13_32", "UK14_32", "SYS_32",
108 flags = condition_codes (regs);
110 printf ("pc : [<%08lx>] lr : [<%08lx>]\n"
111 "sp : %08lx ip : %08lx fp : %08lx\n",
112 instruction_pointer (regs),
113 regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
114 printf ("r10: %08lx r9 : %08lx r8 : %08lx\n",
115 regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
116 printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n",
117 regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
118 printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n",
119 regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
120 printf ("Flags: %c%c%c%c",
121 flags & CC_N_BIT ? 'N' : 'n',
122 flags & CC_Z_BIT ? 'Z' : 'z',
123 flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
124 printf (" IRQs %s FIQs %s Mode %s%s\n",
125 interrupts_enabled (regs) ? "on" : "off",
126 fast_interrupts_enabled (regs) ? "on" : "off",
127 processor_modes[processor_mode (regs)],
128 thumb_mode (regs) ? " (T)" : "");
131 void do_undefined_instruction (struct pt_regs *pt_regs)
133 printf ("undefined instruction\n");
138 void do_software_interrupt (struct pt_regs *pt_regs)
140 printf ("software interrupt\n");
145 void do_prefetch_abort (struct pt_regs *pt_regs)
147 printf ("prefetch abort\n");
152 void do_data_abort (struct pt_regs *pt_regs)
154 printf ("data abort\n");
159 void do_not_used (struct pt_regs *pt_regs)
161 printf ("not used\n");
166 void do_fiq (struct pt_regs *pt_regs)
168 printf ("fast interrupt request\n");
173 void do_irq (struct pt_regs *pt_regs)
175 printf ("interrupt request\n");
180 static ulong timestamp;
181 static ulong lastdec;
183 /* nothing really to do with interrupts, just starts up a counter. */
184 int interrupt_init (void)
188 *((int32_t *) (CFG_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL;
189 val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CFG_PVT << MPUTIM_PTV_BIT);
190 *((int32_t *) (CFG_TIMERBASE + CNTL_TIMER)) = val;
195 * timer without interrupts
198 void reset_timer (void)
200 reset_timer_masked ();
203 ulong get_timer (ulong base)
205 return get_timer_masked () - base;
208 void set_timer (ulong t)
213 /* very rough timer... */
214 void udelay (unsigned long usec)
216 #ifdef CONFIG_INNOVATOROMAP1510
217 #define LOOPS_PER_MSEC 60 /* tuned on omap1510 */
218 volatile int i, time_remaining = LOOPS_PER_MSEC * usec;
220 for (i = time_remaining; i > 0; i--) {
230 tmo += get_timer (0);
232 while (get_timer_masked () < tmo)
237 void reset_timer_masked (void)
240 lastdec = READ_TIMER;
244 ulong get_timer_masked (void)
246 ulong now = READ_TIMER; /* current tick value */
248 if (lastdec >= now) { /* did I roll (rem decrementer) */
250 timestamp += lastdec - now; /* record amount of time since last check */
252 /* we have an overflow ... */
253 timestamp += lastdec + TIMER_LOAD_VAL - now;
260 void udelay_masked (unsigned long usec)
262 #ifdef CONFIG_INNOVATOROMAP1510
263 #define LOOPS_PER_MSEC 60 /* tuned on omap1510 */
264 volatile int i, time_remaining = LOOPS_PER_MSEC*usec;
265 for (i=time_remaining; i>0; i--) { }
274 reset_timer_masked ();
276 while (get_timer_masked () < tmo)
282 * This function is derived from PowerPC code (read timebase as long long).
283 * On ARM it just returns the timer value.
285 unsigned long long get_ticks(void)
291 * This function is derived from PowerPC code (timebase clock frequency).
292 * On ARM it returns the number of timer ticks per second.
294 ulong get_tbclk (void)
295 { /* poor timer, may need to improve especiall for bootp. */